Lines Matching refs:x1
102 mov x1, xzr
190 mov x1, x0
194 lsr x1, x0, #32
207 ldr x1, =NXP_SEC_REGFILE_ADDR
212 str w0, [x1, #CORE_HOLD_OFFSET]
215 mov x1, #NXP_RESET_ADDR
216 ldr w2, [x1, #BRR_OFFSET]
220 str w2, [x1, #BRR_OFFSET]
242 ldr x1, =NXP_DCFG_ADDR
245 ldr w1, [x1, #DCFG_COREDISABLEDSR_OFFSET]
291 and x1, x0, #MPIDR_AFFINITY0_MASK
293 lsl x2, x2, x1
296 and x1, x0, #MPIDR_AFFINITY1_MASK
297 lsl x1, x1, #8
298 orr x2, x2, x1
327 mrs x1, CORTEX_A72_ECTLR_EL1
330 orr x1, x1, #CPUECTLR_SMPEN_EN
331 orr x1, x1, #CPUECTLR_DISABLE_TWALK_PREFETCH
332 bic x1, x1, #CPUECTLR_INS_PREFETCH_MASK
333 bic x1, x1, #CPUECTLR_DAT_PREFETCH_MASK
336 bic x1, x1, #CPUECTLR_TIMER_MASK
337 orr x1, x1, #CPUECTLR_TIMER_8TICKS
338 msr CORTEX_A72_ECTLR_EL1, x1
426 mov x1, #CNTP_CTL_EL0_EN
427 orr x1, x1, #CNTP_CTL_EL0_IMASK
428 msr cntp_ctl_el0, x1
584 mov x1, #SCTLR_I_C_M_MASK
586 bic x0, x0, x1
591 bic x1, x1, #CPUECTLR_TIMER_MASK
598 mov x1, #NXP_CCN_HN_F_0_ADDR
600 str x0, [x1, #CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET]
602 ldr w2, [x1, #CCN_HN_F_SNP_DMN_CTL_OFFSET]
636 mrs x1, spsr_el1
637 orr x1, x1, x2
638 msr spsr_el1, x1
640 mrs x1, spsr_el2
641 orr x1, x1, x2
642 msr spsr_el2, x1
692 mrs x1, CORTEX_A72_ECTLR_EL1
693 bic x1, x1, #CPUECTLR_TIMER_MASK
694 msr CORTEX_A72_ECTLR_EL1, x1
732 mrs x1, CORTEX_A72_ECTLR_EL1
733 bic x1, x1, #CPUECTLR_RET_MASK
734 orr x1, x1, #CPUECTLR_TIMER_8TICKS
735 orr x1, x1, #CPUECTLR_SMPEN_EN
736 msr CORTEX_A72_ECTLR_EL1, x1
782 mrs x1, CORTEX_A72_ECTLR_EL1
783 bic x1, x1, #CPUECTLR_TIMER_MASK
784 msr CORTEX_A72_ECTLR_EL1, x1
822 mrs x1, CORTEX_A72_ECTLR_EL1
823 bic x1, x1, #CPUECTLR_RET_MASK
824 orr x1, x1, #CPUECTLR_TIMER_8TICKS
825 orr x1, x1, #CPUECTLR_SMPEN_EN
826 msr CORTEX_A72_ECTLR_EL1, x1
854 mrs x1, CORTEX_A72_ECTLR_EL1
855 bic x1, x1, #CPUECTLR_TIMER_MASK
856 msr CORTEX_A72_ECTLR_EL1, x1
882 mrs x1, CORTEX_A72_ECTLR_EL1
884 orr x1, x1, #CPUECTLR_SMPEN_MASK
886 orr x1, x1, #CPUECTLR_RET_8CLK
888 orr x1, x1, #CPUECTLR_DISABLE_TWALK_PREFETCH
889 msr CORTEX_A72_ECTLR_EL1, x1
909 ldr x1, =NXP_CCN_HN_F_0_ADDR
910 ldr x7, [x1, #CCN_HN_F_SNP_DMN_CTL_OFFSET]
913 str x7, [x1, #CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET]
915 add x1, x1, #CCN_HNF_OFFSET
922 ldr x1, =NXP_PMU_CCSR_ADDR
967 ldr w9, [x1, x15]
969 ldr w10, [x1, x16]
971 ldr w11, [x1, x17]
973 ldr w12, [x1, x18]
975 ldr w13, [x1, x19]
977 ldr w14, [x1, x20]
998 ldr w4, [x1, x21]
1002 str w7, [x1, x15]
1009 ldr w6, [x1, x21]
1011 str w8, [x1, x16]
1016 ldr w4, [x1, x21]
1018 str w9, [x1, x17]
1023 ldr w6, [x1, x21]
1025 str w10, [x1, x18]
1044 ldr w4, [x1, x21]
1046 str w11, [x1, x19]
1051 ldr w6, [x1, x21]
1053 str w12, [x1, x20]
1070 ldr w5, [x1, x21]
1081 ldr w5, [x1, x21]
1092 ldr w5, [x1, x21]
1103 ldr w5, [x1, x21]
1114 ldr w5, [x1, x21]
1125 ldr w5, [x1, x21]
1243 str w14, [x1, x15]
1245 str w13, [x1, x16]
1247 str w12, [x1, x17]
1249 str w11, [x1, x18]
1251 str w10, [x1, x19]
1253 str w9, [x1, x20]
1260 ldr w5, [x1, x15]
1270 ldr w5, [x1, x15]
1280 ldr w5, [x1, x15]
1290 ldr w5, [x1, x15]
1300 ldr w5, [x1, x15]
1310 ldr w5, [x1, x15]
1353 mrs x1, CORTEX_A72_ECTLR_EL1
1355 orr x1, x1, #CPUECTLR_SMPEN_MASK
1358 bic x1, x1, x2
1361 bic x1, x1, x2
1362 msr CORTEX_A72_ECTLR_EL1, x1
1411 str w9, [x1, x16]
1423 ldr w8, [x1, x17]
1434 str w8, [x1, x12]
1438 str w9, [x1, x13]
1455 str w9, [x1, x15]
1459 str w8, [x1, x14]
1465 str w6, [x1, x16]
1478 ldr w8, [x1, x17]
1519 mov x1, #NXP_DCFG_ADDR
1520 ldr w2, [x1, #RCW_SR27_OFFSET]
1590 mov x1, #CORE_STATE_DATA
1606 mov x1, #CORE_STATE_DATA
1663 ldr x1, =TZPCDECPROT_0_SET_BASE
1666 str w0, [x1]
1669 ldr x1, =TZPCDECPROT_1_SET_BASE
1672 str w0, [x1]
1675 ldr x1, =TZPCDECPROT_2_SET_BASE
1678 str w0, [x1]
1682 ldr x1, =TZPC_BASE
1685 str w0, [x1]
1755 mov x1, #GIC_RD_OFFSET
1762 add x0, x0, x1
1783 mov x1, #GIC_SGI_OFFSET
1788 add x0, x0, x1
1813 ldr x1, =NXP_RESET_ADDR
1814 ldr w0, [x1, x0]