soc-ls1046a/aarch64/ls1046a.S

99 	mov	x1, #NXP_SCFG_ADDR
101 	str	w3, [x1, #SCFG_COREBCR_OFFSET]
105 	mov	x1, #NXP_DCFG_ADDR
106 	ldr	w2, [x1, #DCFG_BRR_OFFSET]
110 	str	w2, [x1, #DCFG_BRR_OFFSET]
135 	ldr	x1, =NXP_RCPM_ADDR
137 	str	w2, [x1, #RCPM_PCPH20CLRR_OFFSET]
182 	mov	x1, #NXP_DCFG_ADDR
185 	ldr	w1, [x1, #DCFG_COREDISR_OFFSET]
239 	mrs	x1, DAIF
241 	orr	x0, x1, x0
245 	mov	x1, #SCTLR_I_C_M_MASK
247 	bic	x0, x0, x1
251 	mrs	x1, SCTLR_EL3
252 	bic	x1, x1, #SCTLR_C_MASK
254 	orr	x1, x1, #SCTLR_I_MASK
255 	msr	SCTLR_EL3, x1
266 	ldr	x1, =COREPMCR_WFIL2
272 	orr	x1, x0, #RCPM_POWMGTCSR_LPM20_REQ
363 	mov	x1, #TIMER_CNTRL_DATA
441 	mov	x1, x6
510 	mov	x1, x0
513 	ldr	w0, [x1, #GICC_IAR_OFFSET]
516 	str	w0, [x1, #GICC_EOIR_OFFSET]
519 	str	w0, [x1, #GICC_DIR_OFFSET]
522 	ldr	w3, [x1, #GICC_CTLR_OFFSET]
524 	str	w3, [x1, #GICC_CTLR_OFFSET]
540 	mov	x1, #TIMER_CNTRL_DATA
563 	mov	x1, x0
568 	lsr	x1, x0, #32
631 	mrs	x1, CORTEX_A72_ECTLR_EL1
632 	bic	x1, x1, #CPUECTLR_TIMER_MASK
633 	msr	CORTEX_A72_ECTLR_EL1, x1
661 	mrs	x1, CORTEX_A72_ECTLR_EL1
662 	orr	x1, x1, #0x1
663 	orr	x1, x1, #CPUECTLR_SMPEN_MASK
664 	msr	CORTEX_A72_ECTLR_EL1, x1
682 	mov	x1, x4
720 	mov	x1, x4
749 	mrs	x1, CORTEX_A72_ECTLR_EL1
750 	bic	x1, x1, #CPUECTLR_TIMER_MASK
751 	msr	CORTEX_A72_ECTLR_EL1, x1
779 	mrs	x1, CORTEX_A72_ECTLR_EL1
780 	orr	x1, x1, #0x1
781 	orr	x1, x1, #CPUECTLR_SMPEN_MASK
782 	msr	CORTEX_A72_ECTLR_EL1, x1
800 	mov	x1, x4
823 	mov	x1, x4
852 	mrs	x1, CORTEX_A72_ECTLR_EL1
853 	bic	x1, x1, #CPUECTLR_TIMER_MASK
854 	msr	CORTEX_A72_ECTLR_EL1, x1
889 	ldr	x1, =COREPMCR_WFIL2
912 	orr	x1, x0, #RCPM_POWMGTCSR_LPM20_REQ
933 	mov	x1, #NXP_SCFG_ADDR
934 	str	wzr, [x1, #SCFG_COREPMCR_OFFSET]