Lines Matching refs:x1
67 and x1, x0, #MPIDR_CPU_MASK
69 add x0, x1, x0, LSR #6
92 mov_imm x1, (RCC_BASE + DEBUG_UART_RST_REG)
94 ldr w0, [x1]
96 str w0, [x1]
98 ldr w0, [x1]
102 str w0, [x1]
104 ldr w0, [x1]
108 mov_imm x1, (RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
109 ldr w2, [x1]
112 str w2, [x1]
113 mov_imm x1, DEBUG_UART_TX_GPIO_BANK_ADDRESS
115 ldr w2, [x1, #GPIO_MODE_OFFSET]
118 str w2, [x1, #GPIO_MODE_OFFSET]
120 ldr w2, [x1, #GPIO_SPEED_OFFSET]
122 str w2, [x1, #GPIO_SPEED_OFFSET]
124 ldr w2, [x1, #GPIO_PUPD_OFFSET]
126 str w2, [x1, #GPIO_PUPD_OFFSET]
129 ldr w2, [x1, #GPIO_AFRH_OFFSET]
134 str w2, [x1, #GPIO_AFRH_OFFSET]
136 ldr w2, [x1, #GPIO_AFRL_OFFSET]
139 str w2, [x1, #GPIO_AFRL_OFFSET]
142 mov_imm x1, (RCC_BASE + DEBUG_UART_PREDIV_CFGR)
144 str w2, [x1]
145 mov_imm x1, (RCC_BASE + DEBUG_UART_FINDIV_CFGR)
147 str w2, [x1]
149 mov_imm x1, (RCC_BASE + DEBUG_UART_TX_CLKSRC_REG)
151 str w2, [x1]
152 mov_imm x1, (RCC_BASE + DEBUG_UART_TX_EN_REG)
153 ldr w2, [x1]
155 str w2, [x1]
158 mov_imm x1, STM32MP_DEBUG_USART_CLK_FRQ
169 mov_imm x1, STM32MP_DEBUG_USART_BASE