| /rk3399_ARM-atf/plat/imx/imx8m/ddr/ |
| H A D | dram.c | 141 void dram_umctl2_init(struct dram_timing_info *timing) in dram_umctl2_init() argument
143 struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg; in dram_umctl2_init()
146 for (i = 0U; i < timing->ddrc_cfg_num; i++) { in dram_umctl2_init()
156 void dram_phy_init(struct dram_timing_info *timing) in dram_phy_init() argument
158 struct dram_cfg_param *cfg = timing->ddrphy_cfg; in dram_phy_init()
162 cfg = timing->ddrphy_cfg; in dram_phy_init()
163 for (i = 0U; i < timing->ddrphy_cfg_num; i++) { in dram_phy_init()
169 cfg = timing->ddrphy_trained_csr; in dram_phy_init()
170 for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) { in dram_phy_init()
176 cfg = timing->ddrphy_pie; in dram_phy_init()
[all …]
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| /rk3399_ARM-atf/plat/imx/imx8m/include/ |
| H A D | dram.h | 73 void dram_umctl2_init(struct dram_timing_info *timing);
74 void dram_phy_init(struct dram_timing_info *timing);
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| /rk3399_ARM-atf/drivers/st/fmc/ |
| H A D | stm32_fmc2_nand.c | 167 unsigned long timing, tar, tclr, thiz, twait; in stm32_fmc2_nand_setup_timing() local
172 timing = div_round_up(tar, hclkp) - 1U; in stm32_fmc2_nand_setup_timing()
173 tims.tar = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); in stm32_fmc2_nand_setup_timing()
176 timing = div_round_up(tclr, hclkp) - 1U; in stm32_fmc2_nand_setup_timing()
177 tims.tclr = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); in stm32_fmc2_nand_setup_timing()
190 timing = div_round_up(twait, hclkp); in stm32_fmc2_nand_setup_timing()
191 tims.twait = CLAMP(timing, 1UL, in stm32_fmc2_nand_setup_timing()
207 timing = div_round_up(tset_mem, hclkp); in stm32_fmc2_nand_setup_timing()
208 tims.tset_mem = CLAMP(timing, 1UL, in stm32_fmc2_nand_setup_timing()
229 timing = div_round_up(thold_mem, hclkp); in stm32_fmc2_nand_setup_timing()
[all …]
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| /rk3399_ARM-atf/fdts/ |
| H A D | stm32mp15-ddr.dtsi | 39 st,ctl-timing = <
100 st,phy-timing = <
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| H A D | stm32mp13-ddr.dtsi | 39 st,ctl-timing = <
92 st,phy-timing = <
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| H A D | stm32mp25-ddr.dtsi | 62 st,ctl-timing = <
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| H A D | stm32mp13-ddr3-1x4Gb-1066-binF.dtsi | 14 * timing mode optimized
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| H A D | stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 14 * timing mode optimized
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| H A D | tc-base.dtsi | 397 panel-timing {
412 timing-panel {
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| /rk3399_ARM-atf/drivers/st/ddr/ |
| H A D | stm32mp1_ram.c | 65 CTL_PARAM(timing), in stm32mp1_ddr_setup()
69 PHY_PARAM(timing), in stm32mp1_ddr_setup()
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| H A D | stm32mp2_ram.c | 83 CTL_PARAM(timing), in stm32mp2_ddr_setup()
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| /rk3399_ARM-atf/docs/security_advisories/ |
| H A D | security-advisory-tfv-5.rst | 6 | | secure world timing information |
18 | Impact | Leakage of sensitive secure world timing information |
37 cause leakage of secure world timing information. This register should be added
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| H A D | security-advisory-tfv-6.rst | 6 | | vulnerabilities using cache timing side-channels |
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| /rk3399_ARM-atf/docs/process/ |
| H A D | security-hardening.rst | 28 Preventing Secure-world timing information leakage via PMU counters
32 world from making it leak timing information. In general, higher privilege
44 Secure and Non-secure state. Thus, it attempts to leak timing information from
72 would allow it to carry out side-channel timing attacks against the Secure
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| H A D | security.rst | 59 | | world timing information |
62 | | vulnerabilities using cache timing side-channels |
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| /rk3399_ARM-atf/drivers/st/i2c/ |
| H A D | stm32_i2c.c | 139 uint32_t timing = I2C_TIMING; in stm32_i2c_init() local
158 timing & TIMINGR_CLEAR_MASK); in stm32_i2c_init()
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| /rk3399_ARM-atf/docs/threat_model/firmware_threat_model/ |
| H A D | threat_model.rst | 345 | | | Do not log high precision timing information. |
630 | Threat | | **An attacker could analyse the timing behaviour |
634 | | | A timing side-channel attack is a type of attack |
641 | | these timing differences, an attacker can gain |
670 | | exploiting timing differences to infer |
673 | | | Introduce random delays/timing jitter or dummy |
674 | | operations to make the timing behavior of program|
1124 | | side-channel timing attacks against TF-A. |
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| /rk3399_ARM-atf/docs/ |
| H A D | change-log.md | 2669 …- bridge ack timing issue causing fpga config hung ([9a402d2](https://review.trustedfirmware.org/p…
|