| #
5864b58a |
| 09-Mar-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "imx8m_misc_changes" into integration
* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(im
Merge changes from topic "imx8m_misc_changes" into integration
* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(imx8mq): correct the slot ack setting for STOP mode
feat(imx8mq): add anamix pll override setting for DSM mode
feat(imx8mq): add workaround code for ERR11171 on imx8mq
feat(imx8mq): add the dram retention support for imx8mq
feat(imx8mq): add version for B2
fix(imx8m): backup mr12/14 value from lpddr4 chip
fix(imx8m): add ddr4 dvfs sw workaround for ERR050712
fix(imx8m): fix coverity out of bound access issue
fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0
feat(imx8m): add more dram pll setting
fix(imx8m): fix the current fsp init
fix(imx8m): fix the rank to rank space issue
fix(imx8m): fix the dfiphymaster setting after dvfs
feat(imx8m): update the ddr4 dvfs flow to include ddr3l support
fix(imx8m): correct the rank info get fro mstr
feat(imx8m): fix the ddr4 dvfs random hang on imx8m
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| #
8962bdd6 |
| 14-Jan-2020 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8mq): enable dram dvfs support on imx8mq
Enable DRAM DVFS support on i.MX8MQ.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id72c5eb9625936052ec51e5a52d9d31175ed1b1b
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| #
dd108c3c |
| 07-Jan-2020 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8mq): add the dram retention support for imx8mq
Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be co
feat(imx8mq): add the dram retention support for imx8mq
Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be copied from dram into ocram.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id8264c342fd62e297b1969cba5ed505450c78a25
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| #
a2655f48 |
| 20-Dec-2021 |
Jacky Bai <ping.bai@nxp.com> |
fix(imx8m): backup mr12/14 value from lpddr4 chip
Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.
Signed-off-by: Jacky Bai <ping.bai@nxp.co
fix(imx8m): backup mr12/14 value from lpddr4 chip
Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: If04733b34a3b4c080828bb7c82e83f0badbeaafd
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| #
0331b1c6 |
| 08-Sep-2020 |
Jacky Bai <ping.bai@nxp.com> |
fix(imx8m): fix coverity out of bound access issue
Fix the out of bound access to the rank setting array.
Fix Coverity issue:
CID 6474575: Out-of-bounds access (OVERRUN)
CID 11014855: Unused value
fix(imx8m): fix coverity out of bound access issue
Fix the out of bound access to the rank setting array.
Fix Coverity issue:
CID 6474575: Out-of-bounds access (OVERRUN)
CID 11014855: Unused value (UNUSED_VALUE)
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I5d9ef90f1479e5d46d1b6c8693a27e3abd614766
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| #
25c43233 |
| 03-Aug-2020 |
Jacky Bai <ping.bai@nxp.com> |
fix(imx8m): fix the current fsp init
The dfimisc reg value should be shift right 8 bit to
get the current fsp.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.
fix(imx8m): fix the current fsp init
The dfimisc reg value should be shift right 8 bit to
get the current fsp.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Change-Id: I4c8c166bc3ad4cc1376961cbf47631c68b5900cc
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| #
33300849 |
| 08-May-2020 |
Jacky Bai <ping.bai@nxp.com> |
fix(imx8m): fix the rank to rank space issue
update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed
fix(imx8m): fix the rank to rank space issue
update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I0fab18cdc378fda760daa0f89c4dd84eb46f7e11
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| #
0e39488f |
| 22-Apr-2020 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8m): update the ddr4 dvfs flow to include ddr3l support
the DDR3L & DDR4 can share same piece of code for DDR frequency scaling.
So update the ddr4 dvfs flow to support DDR3L too.
Signed-of
feat(imx8m): update the ddr4 dvfs flow to include ddr3l support
the DDR3L & DDR4 can share same piece of code for DDR frequency scaling.
So update the ddr4 dvfs flow to support DDR3L too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: Ifc6981f05ed8a4e399adad97690197a9680f554d
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| #
5277c096 |
| 13-Apr-2020 |
Jacky Bai <ping.bai@nxp.com> |
fix(imx8m): correct the rank info get fro mstr
the bitfield of active_ranks in MSTR is defined as below.
Correct the rank num get in dram_info.
0x01: one rank;
0x11: two rank;
Signed-off-by: J
fix(imx8m): correct the rank info get fro mstr
the bitfield of active_ranks in MSTR is defined as below.
Correct the rank num get in dram_info.
0x01: one rank;
0x11: two rank;
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: Idcadb39f492a8fe81c973ac4136d9a1eaa32f54b
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| #
0f0a9dbf |
| 01-Nov-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(imx8m): fix dram retention fsp_table access" into integration
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| #
6c8f5231 |
| 21-Sep-2022 |
Marco Felsch <m.felsch@pengutronix.de> |
fix(imx8m): fix dram retention fsp_table access
The fsp_table access by [i-1] can cause invalid memory access in case of
i=0. This can be the case if no fsp_table is available. Fix this by
adding th
fix(imx8m): fix dram retention fsp_table access
The fsp_table access by [i-1] can cause invalid memory access in case of
i=0. This can be the case if no fsp_table is available. Fix this by
adding the idx variable which tracks the correct index.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: If2285517eb9fe837f3ad54360307a77a658bf62c
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| #
0cb8dd7a |
| 08-Jul-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Iec22dcab,Ib88b4b5d,I50cd6b82,If1167785,I9b3a08ef, ... into integration
* changes:
feat(imx8m): keep pu domains in default state during boot stage
feat(imx8m): add the PU power dom
Merge changes Iec22dcab,Ib88b4b5d,I50cd6b82,If1167785,I9b3a08ef, ... into integration
* changes:
feat(imx8m): keep pu domains in default state during boot stage
feat(imx8m): add the PU power domain support on imx8mm/mn
feat(imx8m): add the anamix pll override setting
feat(imx8m): add the ddr frequency change support for imx8m family
feat(imx8mn): enable dram retention suuport on imx8mn
feat(imx8mm): enable dram retention suuport on imx8mm
feat(imx8m): add dram retention flow for imx8m family
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| #
9c336f61 |
| 25-Nov-2019 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8m): add the ddr frequency change support for imx8m family
Add the DDR frequency change support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If1167785796b8678c351569b83d2922c66f6
feat(imx8m): add the ddr frequency change support for imx8m family
Add the DDR frequency change support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If1167785796b8678c351569b83d2922c66f6e530
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| #
c71793c6 |
| 25-Nov-2019 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8m): add dram retention flow for imx8m family
Add the dram retention flow for i.MX8M SoC family.
Change-Id: Ifb8ba5b2f6f002133cf47c07fef73df29c51c890
Signed-off-by: Jacky Bai <ping.bai@nxp.
feat(imx8m): add dram retention flow for imx8m family
Add the dram retention flow for i.MX8M SoC family.
Change-Id: Ifb8ba5b2f6f002133cf47c07fef73df29c51c890
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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