xref: /rk3399_ARM-atf/docs/security_advisories/security-advisory-tfv-5.rst (revision 87d35d933db1a6766ab34b16915b90aee5764ccb)
1267f8085SPaul BeesleyAdvisory TFV-5 (CVE-2017-15031)
2267f8085SPaul Beesley===============================
3267f8085SPaul Beesley
44fe91230SJoel Hutton+----------------+-------------------------------------------------------------+
54fe91230SJoel Hutton| Title          | Not initializing or saving/restoring ``PMCR_EL0`` can leak  |
64fe91230SJoel Hutton|                | secure world timing information                             |
74fe91230SJoel Hutton+================+=============================================================+
812fc6ba7SPaul Beesley| CVE ID         | `CVE-2017-15031`_                                           |
94fe91230SJoel Hutton+----------------+-------------------------------------------------------------+
10*c605ecd1SAlexei Fedorov| Date           | 02 Oct 2017, updated on 04 Nov 2019                         |
114fe91230SJoel Hutton+----------------+-------------------------------------------------------------+
12*c605ecd1SAlexei Fedorov| Versions       | All, up to and including v2.1                               |
134fe91230SJoel Hutton| Affected       |                                                             |
144fe91230SJoel Hutton+----------------+-------------------------------------------------------------+
154fe91230SJoel Hutton| Configurations | All                                                         |
164fe91230SJoel Hutton| Affected       |                                                             |
174fe91230SJoel Hutton+----------------+-------------------------------------------------------------+
184fe91230SJoel Hutton| Impact         | Leakage of sensitive secure world timing information        |
194fe91230SJoel Hutton+----------------+-------------------------------------------------------------+
204fe91230SJoel Hutton| Fix Version    | `Pull Request #1127`_ (merged on 18 October 2017)           |
21*c605ecd1SAlexei Fedorov|                |                                                             |
22*c605ecd1SAlexei Fedorov|                | `Commit e290a8fcbc`_ (merged on 23 August 2019)             |
23*c605ecd1SAlexei Fedorov|                |                                                             |
24*c605ecd1SAlexei Fedorov|                | `Commit c3e8b0be9b`_ (merged on 27 September 2019)          |
254fe91230SJoel Hutton+----------------+-------------------------------------------------------------+
26*c605ecd1SAlexei Fedorov| Credit         | Arm, Marek Bykowski                                         |
274fe91230SJoel Hutton+----------------+-------------------------------------------------------------+
284fe91230SJoel Hutton
294fe91230SJoel HuttonThe ``PMCR_EL0`` (Performance Monitors Control Register) provides details of the
304fe91230SJoel HuttonPerformance Monitors implementation, including the number of counters
314fe91230SJoel Huttonimplemented, and configures and controls the counters. If the ``PMCR_EL0.DP``
324fe91230SJoel Huttonbit is set to zero, the cycle counter (when enabled) counts during secure world
334fe91230SJoel Huttonexecution, even when prohibited by the debug signals.
344fe91230SJoel Hutton
35*c605ecd1SAlexei FedorovSince TF-A does not save and restore ``PMCR_EL0`` when switching between the
364fe91230SJoel Huttonnormal and secure worlds, normal world code can set ``PMCR_EL0.DP`` to zero to
374fe91230SJoel Huttoncause leakage of secure world timing information. This register should be added
38*c605ecd1SAlexei Fedorovto the list of saved/restored registers both when entering EL3 and also
39*c605ecd1SAlexei Fedorovtransitioning to S-EL1.
404fe91230SJoel Hutton
414fe91230SJoel HuttonFurthermore, ``PMCR_EL0.DP`` has an architecturally ``UNKNOWN`` reset value.
424fe91230SJoel HuttonSince Arm TF does not initialize this register, it's possible that on at least
434fe91230SJoel Huttonsome implementations, ``PMCR_EL0.DP`` is set to zero by default. This and other
444fe91230SJoel Huttonbits with an architecturally UNKNOWN reset value should be initialized to
454fe91230SJoel Huttonsensible default values in the secure context.
464fe91230SJoel Hutton
474fe91230SJoel HuttonThe same issue exists for the equivalent AArch32 register, ``PMCR``, except that
484fe91230SJoel Huttonhere ``PMCR_EL0.DP`` architecturally resets to zero.
494fe91230SJoel Hutton
50*c605ecd1SAlexei FedorovNOTE: The original pull request referenced above only fixed the issue for S-EL1
51*c605ecd1SAlexei Fedorovwhereas the EL3 was fixed in the later commits.
52*c605ecd1SAlexei Fedorov
5312fc6ba7SPaul Beesley.. _CVE-2017-15031: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-15031
544fe91230SJoel Hutton.. _Pull Request #1127: https://github.com/ARM-software/arm-trusted-firmware/pull/1127
55*c605ecd1SAlexei Fedorov.. _Commit e290a8fcbc: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=e290a8fcbc
56*c605ecd1SAlexei Fedorov.. _Commit c3e8b0be9b: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=c3e8b0be9b
57*c605ecd1SAlexei Fedorov
58