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Searched refs:cfg (Results 1 – 25 of 74) sorted by relevance

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/rk3399_ARM-atf/plat/brcm/board/stingray/include/
H A Dscp_utils.h20 #define SCP_READ_CFG(cfg) mmio_read_32(CRMU_CFG_BASE + \ argument
21 offsetof(M0CFG, cfg))
22 #define SCP_WRITE_CFG(cfg, value) mmio_write_32(CRMU_CFG_BASE + \ argument
23 offsetof(M0CFG, cfg), value)
25 #define SCP_READ_CFG16(cfg) mmio_read_16(CRMU_CFG_BASE + \ argument
26 offsetof(M0CFG, cfg))
27 #define SCP_WRITE_CFG16(cfg, value) mmio_write_16(CRMU_CFG_BASE + \ argument
28 offsetof(M0CFG, cfg), value)
30 #define SCP_READ_CFG8(cfg) mmio_read_8(CRMU_CFG_BASE + \ argument
31 offsetof(M0CFG, cfg))
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/devapc/
H A Dapusys_dapc_v1.c17 uint32_t size, dapc_cfg_func cfg) in set_apusys_dapc_v1() argument
22 if ((dapc == NULL) || (cfg == NULL)) { in set_apusys_dapc_v1()
27 ret += cfg(i, DOMAIN_0, dapc[i].d0_permission); in set_apusys_dapc_v1()
28 ret += cfg(i, DOMAIN_1, dapc[i].d1_permission); in set_apusys_dapc_v1()
29 ret += cfg(i, DOMAIN_2, dapc[i].d2_permission); in set_apusys_dapc_v1()
30 ret += cfg(i, DOMAIN_3, dapc[i].d3_permission); in set_apusys_dapc_v1()
31 ret += cfg(i, DOMAIN_4, dapc[i].d4_permission); in set_apusys_dapc_v1()
32 ret += cfg(i, DOMAIN_5, dapc[i].d5_permission); in set_apusys_dapc_v1()
33 ret += cfg(i, DOMAIN_6, dapc[i].d6_permission); in set_apusys_dapc_v1()
34 ret += cfg(i, DOMAIN_7, dapc[i].d7_permission); in set_apusys_dapc_v1()
[all …]
/rk3399_ARM-atf/drivers/nxp/trdc/
H A Dimx_trdc.c295 void trdc_setup(struct trdc_config_info *cfg) in trdc_setup() argument
301 if (trdc_mrc_enabled(cfg->trdc_base)) { in trdc_setup()
303 for (i = 0U; i < cfg->num_mrc_glbac; i++) { in trdc_setup()
304 trdc_mrc_set_control(cfg->trdc_base, in trdc_setup()
305 cfg->mrc_glbac[i].mbc_mrc_id, in trdc_setup()
306 cfg->mrc_glbac[i].glbac_id, in trdc_setup()
307 cfg->mrc_glbac[i].glbac_val); in trdc_setup()
311 for (i = 0U; i < cfg->num_mrc_cfg; i++) { in trdc_setup()
312 trdc_mrc_rgn_config(cfg->trdc_base, cfg->mrc_cfg[i].mrc_id, in trdc_setup()
313 cfg->mrc_cfg[i].dom_id, in trdc_setup()
[all …]
/rk3399_ARM-atf/drivers/amlogic/crypto/
H A Dsha_dma.c20 uint32_t cfg; member
31 (ASD_DESC_GET((d)->cfg, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF))
33 (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF))
38 (ASD_DESC_GET((d)->cfg, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF))
40 (ASD_DESC_SET((d)->cfg, v, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF))
45 (ASD_DESC_GET((d)->cfg, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF))
47 (ASD_DESC_SET((d)->cfg, v, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF))
52 (ASD_DESC_GET((d)->cfg, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF))
54 (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF))
59 (ASD_DESC_GET((d)->cfg, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF))
[all …]
/rk3399_ARM-atf/plat/imx/imx8ulp/upower/
H A Dupower_soc_defs.h846 get_apd_swt_cfg(volatile struct ps_apd_pwr_mode_cfg_t *cfg) in get_apd_swt_cfg() argument
850 ptr = (char *)cfg; in get_apd_swt_cfg()
851 ptr += (uint64_t)cfg->swt_board_offs; in get_apd_swt_cfg()
857 get_apd_mem_cfg(volatile struct ps_apd_pwr_mode_cfg_t *cfg) in get_apd_mem_cfg() argument
861 ptr = (char *)cfg; in get_apd_mem_cfg()
862 ptr += (uint64_t)cfg->swt_mem_offs; in get_apd_mem_cfg()
970 uint32_t *cfg; in set_mon_cfg() local
973 cfg = (uint32_t *)&((struct ps_rtd_pwr_mode_cfg_t *)mode_cfg)->mon_cfg.mon_hvd_en; in set_mon_cfg()
975 cfg = (uint32_t *)&((struct ps_apd_pwr_mode_cfg_t *)mode_cfg)->pad_cfg.pad_tqsleep; in set_mon_cfg()
978 *cfg = mon_cfg.R; in set_mon_cfg()
[all …]
/rk3399_ARM-atf/drivers/qti/accesscontrol/vmidmt/
H A Dvmidmt.c97 struct hal_vmidmt_port_map *cfg; in map_vmid_internal() local
100 cfg = get_info_cfg(master); in map_vmid_internal()
101 if (!cfg) in map_vmid_internal()
115 rc = vmidmt_hal_config_ctx_ext(&cfg->vmidmt_info, index, list, len, in map_vmid_internal()
120 vmidmt_hal_enable_client(&cfg->vmidmt_info, true); in map_vmid_internal()
121 vmidmt_hal_enable_client(&cfg->vmidmt_info, false); in map_vmid_internal()
164 struct hal_vmidmt_port_map *cfg; in config_options_per_master() local
167 cfg = get_info_cfg(VMIDMT_INSTANCE(g_vmidmt_cfg[index])); in config_options_per_master()
168 if (!cfg) in config_options_per_master()
179 rc = vmidmt_hal_init(&cfg->vmidmt_info, &secure_cfg, NULL, NULL); in config_options_per_master()
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H A Dvmidmt_hal.c59 get_permissions(const struct hal_vmidmt_access_config *cfg, uint32_t vmid) in get_permissions() argument
64 uint32_t perm = cfg->au_vmid_perm[word]; in get_permissions()
69 static inline bool mask_bit_set(const struct hal_vmidmt_access_config *cfg, in mask_bit_set() argument
77 return (cfg->au_vmid[word] & mask) != 0U; in mask_bit_set()
81 configure_acr(uint64_t addr, struct hal_vmidmt_access_config *cfg) in configure_acr() argument
88 if (!mask_bit_set(cfg, vmid)) in configure_acr()
92 perm = get_permissions(cfg, vmid); in configure_acr()
97 VMIDMT_OUTM(addr, VMIDMTACR, cfg->au_vmid[0], acr); in configure_acr()
98 acr_val = VMIDMT_INM(addr, VMIDMTACR, cfg->au_vmid[0]); in configure_acr()
155 const struct hal_vmidmt_default_vmid_config *cfg, bool sec) in set_default_config() argument
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/rk3399_ARM-atf/fdts/
H A Dstm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi60 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
61 cfg = <30 1 1 1>;
69 pll2_cfg_600Mhz: pll2-cfg-600Mhz {
70 cfg = <30 1 1 2>;
78 pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
79 cfg = <30 1 1 1>;
87 pll5_cfg_532Mhz: pll5-cfg-532Mhz {
88 cfg = <133 5 1 2>;
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi63 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
64 cfg = <30 1 1 1>;
72 pll2_cfg_600Mhz: pll2-cfg-600Mhz {
73 cfg = <30 1 1 2>;
81 pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
82 cfg = <30 1 1 1>;
90 pll5_cfg_532Mhz: pll5-cfg-532Mhz {
91 cfg = <133 5 1 2>;
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi65 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
66 cfg = <30 1 1 1>;
74 pll2_cfg_600Mhz: pll2-cfg-600Mhz {
75 cfg = <30 1 1 2>;
83 pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
84 cfg = <30 1 1 1>;
92 pll5_cfg_532Mhz: pll5-cfg-532Mhz {
93 cfg = <133 5 1 2>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi65 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
66 cfg = <30 1 1 1>;
74 pll2_cfg_600Mhz: pll2-cfg-600Mhz {
75 cfg = <30 1 1 2>;
83 pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
84 cfg = <30 1 1 1>;
92 pll5_cfg_532Mhz: pll5-cfg-532Mhz {
93 cfg = <133 5 1 2>;
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi65 pll1_cfg_1200MHz: pll1-cfg-1200MHz {
66 cfg = <30 1 1 1>;
74 pll2_cfg_400MHz: pll2-cfg-400MHz {
75 cfg = <20 1 1 2>;
83 pll4_cfg_1200MHz: pll4-cfg-1200MHz {
84 cfg = <30 1 1 1>;
/rk3399_ARM-atf/drivers/brcm/emmc/
H A Demmc_pboot_hal_memory_drv.c134 p_sdhandle->device->cfg.blockSize)) { in bcm_emmc_init()
330 const size_t blockSize = p_sdhandle->device->cfg.blockSize; in sdio_read()
481 (uint32_t)(mem_addr / p_sdhandle->device->cfg.blockSize); in sdio_write()
484 blockAddr * p_sdhandle->device->cfg.blockSize); in sdio_write()
487 ((uint32_t)mem_addr / p_sdhandle->device->cfg.blockSize) * in sdio_write()
488 p_sdhandle->device->cfg.blockSize; in sdio_write()
499 blockAddr, p_sdhandle->device->cfg.blockSize)) { in sdio_write()
502 (p_sdhandle->device->cfg.blockSize - offset)) { in sdio_write()
506 p_sdhandle->device->cfg.blockSize - offset; in sdio_write()
519 p_sdhandle->device->cfg.blockSize)) { in sdio_write()
[all …]
H A Demmc_chal_sd.c275 handle->cfg.voltage = 0; in chal_sd_init()
279 handle->cfg.voltage |= SD_VDD_WINDOW_3_3_TO_3_4; in chal_sd_init()
282 handle->cfg.voltage |= SD_VDD_WINDOW_3_0_TO_3_1; in chal_sd_init()
285 handle->cfg.voltage |= SD_VDD_WINDOW_1_8_TO_1_9; in chal_sd_init()
368 handle->cfg.mode = SD_PIO_MODE; /* set to PIO mode first for init */ in chal_sd_start()
369 handle->cfg.dma = SD_DMA_OFF; in chal_sd_start()
381 handle->cfg.mode = mode; in chal_sd_start()
481 handle->cfg.dma = mode; in chal_sd_set_dma()
485 val |= handle->cfg.dma - 1; in chal_sd_set_dma()
491 handle->cfg.dma = 0; in chal_sd_set_dma()
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/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm_cpc.c52 struct mtk_plat_dev_config *cfg = NULL; in mtk_cpc_auto_dormant_en() local
59 mt_plat_cpu_pm_dev_config(&cfg); in mtk_cpc_auto_dormant_en()
61 if (cfg) { in mtk_cpc_auto_dormant_en()
62 cfg->auto_off = !!en; in mtk_cpc_auto_dormant_en()
63 mt_plat_cpu_pm_dev_update(cfg); in mtk_cpc_auto_dormant_en()
69 struct mtk_plat_dev_config *cfg = NULL; in mtk_cpc_auto_dormant_tick() local
73 mt_plat_cpu_pm_dev_config(&cfg); in mtk_cpc_auto_dormant_tick()
75 if (cfg) { in mtk_cpc_auto_dormant_tick()
76 cfg->auto_thres_us = us; in mtk_cpc_auto_dormant_tick()
77 mt_plat_cpu_pm_dev_update(cfg); in mtk_cpc_auto_dormant_tick()
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/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Ddram.c158 struct dram_cfg_param *cfg = timing->ddrphy_cfg; in dram_phy_init() local
162 cfg = timing->ddrphy_cfg; in dram_phy_init()
164 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); in dram_phy_init()
165 cfg++; in dram_phy_init()
169 cfg = timing->ddrphy_trained_csr; in dram_phy_init()
171 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); in dram_phy_init()
172 cfg++; in dram_phy_init()
176 cfg = timing->ddrphy_pie; in dram_phy_init()
178 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); in dram_phy_init()
179 cfg++; in dram_phy_init()
/rk3399_ARM-atf/plat/marvell/armada/a8k/a80x0/board/
H A Dmarvell_plat_config.c168 .cfg.gpio.pin_count = 1,
169 .cfg.gpio.info = {{0, 35} },
170 .cfg.gpio.step_count = 7,
171 .cfg.gpio.seq = {1, 0, 1, 0, 1, 0, 1},
172 .cfg.gpio.delay_ms = 10,
/rk3399_ARM-atf/plat/marvell/armada/a8k/a80x0_nbx/board/
H A Dmarvell_plat_config.c173 .cfg.gpio.pin_count = 1,
174 .cfg.gpio.info = {{0, 35} },
175 .cfg.gpio.step_count = 7,
176 .cfg.gpio.seq = {1, 0, 1, 0, 1, 0, 1},
177 .cfg.gpio.delay_ms = 10,
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Diommu.c284 struct arm_smmu_cfg cfg[NUM_OF_SMRS]; member
308 uint32_t idx = smmu->cfg[index].cbndx; in arm_smmu_smr_cfg()
321 uint32_t idx = smmu->cfg[index].cbndx; in arm_smmu_s2cr_cfg()
446 smmu->cfg[idx].cbndx = context_bank_index; in arm_smmu_create_identity_map()
447 smmu->cfg[idx].cbar = STG1_WITH_STG2_BYPASS << CBAR_TYPE_SHIFT; in arm_smmu_create_identity_map()
458 ARM_SMMU_GR1_CBA2R(smmu->cfg[idx].cbndx)), in arm_smmu_create_identity_map()
461 reg = smmu->cfg[idx].cbar; in arm_smmu_create_identity_map()
466 ARM_SMMU_GR1_CBAR(smmu->cfg[idx].cbndx)), in arm_smmu_create_identity_map()
485 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) + in arm_smmu_create_identity_map()
489 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) + in arm_smmu_create_identity_map()
[all …]
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.c72 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_enable() local
74 mmio_setbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx)); in clk_gate_enable()
77 (void)mmio_read_32(priv->base + cfg->offset); in clk_gate_enable()
85 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_disable() local
89 mmio_clrbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx)); in clk_gate_disable()
92 (void)mmio_read_32(priv->base + cfg->offset); in clk_gate_disable()
98 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_is_enabled() local
100 return ((mmio_read_32(priv->base + cfg->offset) & BIT(cfg->bit_idx)) != 0U); in clk_gate_is_enabled()
755 struct clk_stm32_gate_cfg *cfg = clk->clock_cfg; in clk_stm32_gate_enable() local
756 const struct gate_cfg *gate = &priv->gates[cfg->id]; in clk_stm32_gate_enable()
[all …]
/rk3399_ARM-atf/plat/qti/msm8916/
H A Dmsm8916_config.c54 uintptr_t cfg = APCS_CFG(cluster); in msm8916_configure_apcs_cluster() local
58 mmio_write_32(cfg, 0); in msm8916_configure_apcs_cluster()
87 mmio_write_32(cfg + APCS_BOOT_START_ADDR_SEC, BL31_BASE | REMAP_EN); in msm8916_configure_apcs_cluster()
88 mmio_write_32(cfg + APCS_AA64NAA32_REG, 1); in msm8916_configure_apcs_cluster()
92 mmio_write_32(cfg + APCS_BOOT_START_ADDR_SEC, BL32_BASE | REMAP_EN); in msm8916_configure_apcs_cluster()
/rk3399_ARM-atf/drivers/nxp/ddr/s32cc/
H A Dddr_init.c223 uint32_t load_register_cfg_16(size_t size, const struct regconf_16 cfg[]) in load_register_cfg_16() argument
228 mmio_write_16((uintptr_t)cfg[i].addr, cfg[i].data); in load_register_cfg_16()
235 uint32_t load_register_cfg(size_t size, const struct regconf cfg[]) in load_register_cfg() argument
240 mmio_write_32((uintptr_t)cfg[i].addr, cfg[i].data); in load_register_cfg()
247 uint32_t load_dq_cfg(size_t size, const struct dqconf cfg[]) in load_dq_cfg() argument
252 mmio_write_32((uintptr_t)cfg[i].addr, cfg[i].data); in load_dq_cfg()
/rk3399_ARM-atf/include/common/
H A Dinterrupt_props.h13 #define INTR_PROP_DESC(num, pri, grp, cfg) \ argument
18 .intr_cfg = (cfg), \
/rk3399_ARM-atf/include/drivers/marvell/
H A Dthermal.h22 int (*ptr_tsen_probe)(struct tsen_config *cfg);
23 int (*ptr_tsen_read)(struct tsen_config *cfg, int *temp);
/rk3399_ARM-atf/plat/marvell/armada/a8k/common/
H A Dplat_pm.c510 assert((pm_cfg->cfg.gpio.pin_count < PMIC_GPIO_MAX_NUMBER) && in plat_marvell_power_off_gpio()
511 (pm_cfg->cfg.gpio.step_count < PMIC_GPIO_MAX_TOGGLE_STEP)); in plat_marvell_power_off_gpio()
514 for (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) { in plat_marvell_power_off_gpio()
515 info = &pm_cfg->cfg.gpio.info[gpio]; in plat_marvell_power_off_gpio()
532 mdelay(pm_cfg->cfg.gpio.delay_ms); in plat_marvell_power_off_gpio()
537 for (idx = 0; idx < pm_cfg->cfg.gpio.step_count; idx++) { in plat_marvell_power_off_gpio()
538 tog_bits = pm_cfg->cfg.gpio.seq[idx]; in plat_marvell_power_off_gpio()
543 info = &pm_cfg->cfg.gpio.info[0]; in plat_marvell_power_off_gpio()
548 for (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) { in plat_marvell_power_off_gpio()
549 shift = pm_cfg->cfg.gpio.info[gpio].gpio_index % 32; in plat_marvell_power_off_gpio()
[all …]

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