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Searched refs:PLAT_MAX_PWR_LVL (Results 1 – 25 of 148) sorted by relevance

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/rk3399_ARM-atf/lib/psci/
H A Dpsci_common.c51 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
81 CASSERT((PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL) &&
82 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),
308 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_set_req_local_pwr_state()
323 for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) { in psci_init_req_local_pwr_states()
344 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_get_req_local_pwr_states()
367 unsigned int max_pwrlvl = PLAT_MAX_PWR_LVL; in psci_update_req_local_pwr_states()
396 unsigned int max_pwrlvl = PLAT_MAX_PWR_LVL; in psci_restore_req_local_pwr_states()
472 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in psci_get_target_local_pwr_states()
582 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); in psci_do_state_coordination()
[all …]
H A Dpsci_setup.c73 svc_cpu_data->target_pwrlvl = PLAT_MAX_PWR_LVL; in psci_init_pwr_domain_node()
101 unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; in psci_update_pwrlvl_limits()
102 unsigned int temp_index[PLAT_MAX_PWR_LVL] = {0}; in psci_update_pwrlvl_limits()
106 PLAT_MAX_PWR_LVL, in psci_update_pwrlvl_limits()
108 for (j = (int)PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { in psci_update_pwrlvl_limits()
138 int level = (int)PLAT_MAX_PWR_LVL; in populate_power_domain_tree()
244 psci_set_pwr_domains_to_run(cpu_idx, PLAT_MAX_PWR_LVL); in psci_setup()
H A Dpsci_suspend.c39 psci_set_suspend_pwrlvl(PLAT_MAX_PWR_LVL); in psci_cpu_suspend_to_standby_finish()
58 end_pwrlvl = PLAT_MAX_PWR_LVL; in psci_suspend_to_pwrdown_start()
122 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; in psci_cpu_suspend_start()
341 psci_set_suspend_pwrlvl(PLAT_MAX_PWR_LVL); in psci_cpu_suspend_to_powerdown_finish()
H A Dpsci_off.c28 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in psci_set_power_off_state()
51 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; in psci_do_cpu_off()
H A Dpsci_main.c200 if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL) { in psci_system_suspend()
207 state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0); in psci_system_suspend()
215 PLAT_MAX_PWR_LVL, in psci_system_suspend()
225 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; in psci_cpu_off()
353 if (power_level > PLAT_MAX_PWR_LVL) { in psci_node_hw_state()
/rk3399_ARM-atf/plat/arm/css/common/
H A Dcss_pm.c43 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
56 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
63 CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL,
260 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL); in css_get_sys_suspend_power_state()
262 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) in css_get_sys_suspend_power_state()
291 #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) in css_validate_power_state()
359 psci_pwrdown_cpu_start(PLAT_MAX_PWR_LVL); in css_reboot_interrupt_handler()
/rk3399_ARM-atf/plat/imx/common/
H A Dimx8_psci.c39 if (pwr_lvl > PLAT_MAX_PWR_LVL) in imx_validate_power_state()
58 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in imx_get_sys_suspend_power_state()
60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/rockchip/common/
H A Dplat_pm.c26 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
139 if (pwr_lvl > PLAT_MAX_PWR_LVL) in rockchip_validate_power_state()
158 for (i = (pwr_lvl + 1); i <= PLAT_MAX_PWR_LVL; i++) in rockchip_validate_power_state()
174 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rockchip_get_sys_suspend_power_state()
229 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_off()
265 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend()
286 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_on_finish()
330 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend_finish()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_pm.c33 if (pwr_lvl > PLAT_MAX_PWR_LVL) in arm_validate_power_state()
99 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) { in arm_validate_power_state()
149 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); in arm_system_pwr_domain_save()
178 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); in arm_system_pwr_domain_resume()
/rk3399_ARM-atf/plat/mediatek/topology/group_4_3_1/
H A Dtopology_conf.mk7 PLAT_MAX_PWR_LVL := 2
8 $(eval $(call add_defined_option,PLAT_MAX_PWR_LVL))
/rk3399_ARM-atf/plat/mediatek/include/armv9/
H A Darch_def.h13 #ifndef PLAT_MAX_PWR_LVL
14 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 macro
/rk3399_ARM-atf/plat/mediatek/mt8173/
H A Dplat_pm.c39 #define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ?\
59 #if PLAT_MAX_PWR_LVL > MTK_PWR_LVL1
378 if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) && in plat_power_domain_on_finish()
387 if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) && in plat_power_domain_on_finish()
436 assert(PLAT_MAX_PWR_LVL >= 2); in plat_get_sys_suspend_power_state()
438 for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in plat_get_sys_suspend_power_state()
478 if (pwr_lvl > PLAT_MAX_PWR_LVL) in plat_validate_power_state()
548 assert(PLAT_MAX_PWR_LVL >= MTK_PWR_LVL2); in mtk_system_pwr_domain_resume()
/rk3399_ARM-atf/plat/nuvoton/npcm845x/
H A Dnpcm845x_psci.c168 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_suspend()
188 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_on_finish()
210 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_suspend_finish()
306 for (i = ARM_PWR_LVL0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_get_sys_suspend_power_state()
367 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_off()
/rk3399_ARM-atf/services/spd/tlkd/
H A Dtlkd_pm.c50 if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) in cpu_suspend_handler()
86 if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) in cpu_resume_handler()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/
H A Dimx8mq_psci.c28 if (pwr_lvl > PLAT_MAX_PWR_LVL) in imx_validate_power_state()
125 for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++) in imx_get_sys_suspend_power_state()
128 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/xilinx/zynqmp/
H A Dplat_psci.c80 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_off()
110 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_suspend()
131 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_on_finish()
148 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_suspend_finish()
/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_psci.c104 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_off()
127 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_suspend()
144 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_on_finish()
175 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_suspend_finish()
/rk3399_ARM-atf/plat/renesas/rcar_gen4/
H A Dplat_pm.c25 #define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
188 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = in rcar_get_sys_suspend_power_state()
191 for (i = MPIDR_AFFLVL0; i < (uint64_t)PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
194 for (i = MPIDR_AFFLVL0; i <= (uint64_t)PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/nvidia/tegra/common/
H A Dtegra_pm.c40 for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in tegra_get_sys_suspend_power_state()
148 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == in tegra_pwr_domain_power_down_wfi()
171 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == in tegra_pwr_domain_on_finish()
/rk3399_ARM-atf/plat/xilinx/versal_net/
H A Dplat_psci_pm.c75 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_off()
221 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_suspend()
263 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_suspend_finish()
343 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/allwinner/common/
H A Dsunxi_scpi_pm.c156 if (power_level > PLAT_MAX_PWR_LVL) { in sunxi_validate_power_state()
173 for (; i <= PLAT_MAX_PWR_LVL; ++i) { in sunxi_validate_power_state()
184 for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i) { in sunxi_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/amd/versal2/
H A Dplat_psci_pm.c77 for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal2_pwr_domain_off()
168 for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal2_pwr_domain_suspend()
250 for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal2_pwr_domain_suspend_finish()
348 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in versal2_get_sys_suspend_power_state()
/rk3399_ARM-atf/plat/renesas/common/
H A Dplat_pm.c38 #define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
286 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
292 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN; in rcar_get_sys_suspend_power_state()
293 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
/rk3399_ARM-atf/drivers/arm/css/scp/
H A Dcss_pm_scmi.c162 for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in css_scp_suspend()
208 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in css_scp_off()
241 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) in css_scp_on()
272 if ((power_level > PLAT_MAX_PWR_LVL) || in css_scp_get_power_state()
360 psci_pwrdown_cpu_start(PLAT_MAX_PWR_LVL); in css_scp_system_off()
/rk3399_ARM-atf/plat/mediatek/include/armv8_2/
H A Darch_def.h11 #define PLAT_MAX_PWR_LVL (2) macro

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