Merge "fix(smccc): resolve caller world confusion" into integration

fix(smccc): resolve caller world confusion

TF-A checks the SMC caller world using is_caller_secure,
is_caller_non_secure and is_caller_realm macros. Until
realm world was introduced it was fine to u

fix(smccc): resolve caller world confusion

TF-A checks the SMC caller world using is_caller_secure,
is_caller_non_secure and is_caller_realm macros. Until
realm world was introduced it was fine to use a pattern like

if (is_caller_non_secure(flags))
return DENY;

// Handle secure call
secure_operation();

is_caller_non_secure would be false for a realm caller, so this pattern
treats this like a secure world caller. This patch fixes
improper use of is_caller_non_secure and is_caller_secure
to handle realm world caller properly.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I60b125853183ac2ac15277f06d2efb7f3a9d3977

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Merge "fix(psci): add missing curly braces" into integration

Merge "fix(psci): initialise variable to default zero" into integration

fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body w

fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: Ida2460b7fe6f27b23382a1259a5ac93fe36bd48d
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(psci): initialise variable to default zero

This corrects the MISRA violation C2012-9.1:

The value of an object with automatic storage duration shall
not be read before it has been set.Initializ

fix(psci): initialise variable to default zero

This corrects the MISRA violation C2012-9.1:

The value of an object with automatic storage duration shall
not be read before it has been set.Initialized the variable
to default value zero.

Change-Id: Ib3a2a853b82ce3c3ba1f518705d7ac2e01130e37
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge changes from topic "xlnx_fix_gen_unused_var" into integration

* changes:
fix(console): create unique variable name
fix(bl31): declare function as static
fix(psci): initialise variable to

Merge changes from topic "xlnx_fix_gen_unused_var" into integration

* changes:
fix(console): create unique variable name
fix(bl31): declare function as static
fix(psci): initialise variable to default zero
fix(services): declare unused parameters as void
fix(lib): declare unused parameters as void
fix(platforms): declare unused parameters as void

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fix(psci): initialise variable to default zero

This corrects the MISRA violation C2012-9.1:
The value of an object with automatic storage duration shall not
be read before it has been set.
Initializ

fix(psci): initialise variable to default zero

This corrects the MISRA violation C2012-9.1:
The value of an object with automatic storage duration shall not
be read before it has been set.
Initialized the variable to default value zero.

Change-Id: I225ae4487b05fc47728222765029d6e1fe292ac1
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(lib): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I

fix(lib): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I979ba118fd209be5d4f0bff3978479c22428d79b
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge "fix(psci): add missing curly braces" into integration

fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:

The body of an iteration-statement or a selection-statement
shall be a compound-statement.Enclosed statement body w

fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:

The body of an iteration-statement or a selection-statement
shall be a compound-statement.Enclosed statement body within
the curly braces.

Change-Id: Ibd402a52e44e59d1c37613d8925aac8e115aa31c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge "fix(psci): do not modify higher levels for standby in OSI mode" into integration

fix(psci): do not modify higher levels for standby in OSI mode

The OSI mode for the CPU standby fast path updates the requested power
states incorrectly. psci_update_req_local_pwr_states() will not

fix(psci): do not modify higher levels for standby in OSI mode

The OSI mode for the CPU standby fast path updates the requested power
states incorrectly. psci_update_req_local_pwr_states() will not bother
saving level 0. It will also clamp the level it accesses to the
end_pwrlvl argument. Well, in the fast path, this argument is always 0
(as a condition of entering the fast path). The result is that it reads
the level 0 power state (retention) and writes it to the level 1 power
state, even though by definition, the fast path will not update higher
power levels.

The fix is to pass PLAT_MAX_PWR_LVL instead of target_pwrlvl to
psci_update_req_local_pwr_states(). However, doing that makes it
apparent that this call will not change anything and therefore there is
nothing to save - the level 0 power state is written by
psci_set_cpu_local_state(). So the save + restore are redundant. Remove
them to save on a bunch of work.

Another thing that is not considered is locking. No locks are held in
the fast path, so these updates are not safe.

Change-Id: Icc785df87b294b938b59705116369abd80ccf4da
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "xlnx_fix_gen_op_datatype" into integration

* changes:
fix(services): typecast operands to match data type
fix(psci): typecast operands to match data type
fix(common):

Merge changes from topic "xlnx_fix_gen_op_datatype" into integration

* changes:
fix(services): typecast operands to match data type
fix(psci): typecast operands to match data type
fix(common): typecast operands to match data type
fix(arm-drivers): typecast operands to match data type
fix(bl31): typecast operands to match data type

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fix(psci): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a dif

fix(psci): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Ic4a109cb55fdf9b60c8d26df68f61811b59a1a9f
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge "feat(psci): remove cpu context init by index" into integration

feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of in

feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of initialising the context for the waking core (the warmboot
entrypoint for both). This is convenient because the calling core can
write the context while in coherency and the waking core will only need
the context after its entered coherency. This avoids any cache
maintenance and makes communication simple.

However, this has 3 main problems:
a) asymmetric feature support is problematic - the calling core has no
way of knowing the feature set of the waking core. If the two
diverge, the architectural feature discovery via ID registers breaks
down. We've thus far "fixed" this on a case by case basis which
doesn't scale and introduces redundancy.

b) powerdown abandon (pabandon) introduces a contradiction - the calling
core has to initialise the context for when the core wakes up, but
should the core not powerdown it needs its old context intact. The only
way to work around this is by keeping two copies of context which
incurs a runtime and memory overhead.

c) cm_prepare_el3_exit[_ns]() doesn't have access to the entrypoint but needs
it to make initialisation decisions. We can infer some of this from
registers that have already been written but this is awkwardly
limiting for what we can do. This also necessitates the split from
the context initialisation.

We can solve all three by a making a core be in full ownership of its
own context. The calling core then only writes entrypoint information
and nothing else. The waking core then initialises its own context as it
sees fit with full knowledge of the whole picture.

The only tricky bit is cache coherency - the waking core has to be able
to coherently observe its new entrypoint. Calling cores will write to
the shared region with coherent caches on. If we make sure to read the
context only after the waking core has entered coherency, then we can
avoid cache operations and let hardware handle everything.

We can skip the spsr check for FEAT_TCR2 as it doesn't make a
difference. We can also skip enabling it twice from generic code.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I86e7fe8b698191fc3b469e5ced1fd010f8754b0e

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Merge changes Ibe021336,Ic1f05e77 into integration

* changes:
fix(rdv3): correctly define plat_mboot_measure_key()
fix(psci): initialise variables

fix(psci): initialise variables

When building with LTO, GCC is uncomfortable that these variables are
uninitialised and complains that they may be used before they are
initialised. Set them to 0 as

fix(psci): initialise variables

When building with LTO, GCC is uncomfortable that these variables are
uninitialised and complains that they may be used before they are
initialised. Set them to 0 as there are plenty of asserts to make sure
these branches cannot be taken.

Change-Id: Ic1f05e77252e93bdafab033dcb24ad42856ebf9a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "xlnx_fix_gen_missing_brace" into integration

* changes:
fix(platforms): modify function to have single return
fix(el3-runtime): add missing curly braces
fix(locks): a

Merge changes from topic "xlnx_fix_gen_missing_brace" into integration

* changes:
fix(platforms): modify function to have single return
fix(el3-runtime): add missing curly braces
fix(locks): add missing curly braces
fix(psci): add missing curly braces
fix(bl31): add missing curly braces
fix(console): add missing curly braces
fix(arm-drivers): add missing curly braces
fix(common): add missing curly braces
fix(platforms): add missing curly braces

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fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body w

fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I8b656f59b445e914dd3f47e3dde83735481a3640
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_

Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`
chore(psci): drop skip_wfi variable
feat(arm): convert arm platforms to expect a wakeup
fix(cpus): avoid SME related loss of context on powerdown
feat(psci): allow cores to wake up from powerdown
refactor: panic after calling psci_power_down_wfi()
refactor(cpus): undo errata mitigations
feat(cpus): add sysreg_bit_toggle

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fix(cpus): avoid SME related loss of context on powerdown

Travis' and Gelas' TRMs tell us to disable SME (set PSTATE.{ZA, SM} to
0) when we're attempting to power down. What they don't tell us is th

fix(cpus): avoid SME related loss of context on powerdown

Travis' and Gelas' TRMs tell us to disable SME (set PSTATE.{ZA, SM} to
0) when we're attempting to power down. What they don't tell us is that
if this isn't done, the powerdown request will be rejected. On the
CPU_OFF path that's not a problem - we can force SVCR to 0 and be
certain the core will power off.

On the suspend to powerdown path, however, we cannot do this. The TRM
also tells us that the sequence could also be aborted on eg. GIC
interrupts. If this were to happen when we have overwritten SVCR to 0,
upon a return to the caller they would experience a loss of context. We
know that at least Linux may call into PSCI with SVCR != 0. One option
is to save the entire SME context which would be quite expensive just to
work around. Another option is to downgrade the request to a normal
suspend when SME was left on. This option is better as this is expected
to happen rarely enough to ignore the wasted power and we don't want to
burden the generic (correct) path with needless context management.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I698fa8490ebf51461f6aa8bba84f9827c5c46ad4

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Merge changes I137f69be,Ia2e7168f,I0e569d12,I614272ec,Ib68293f2 into integration

* changes:
perf(psci): pass my_core_pos around instead of calling it repeatedly
refactor(psci): move timestamp co

Merge changes I137f69be,Ia2e7168f,I0e569d12,I614272ec,Ib68293f2 into integration

* changes:
perf(psci): pass my_core_pos around instead of calling it repeatedly
refactor(psci): move timestamp collection to psci_pwrdown_cpu
refactor(psci): factor common code out of the standby finisher
refactor(psci): don't use PSCI_INVALID_PWR_LVL to signal OFF state
docs(psci): drop outdated cache maintenance comment

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perf(psci): pass my_core_pos around instead of calling it repeatedly

On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inli

perf(psci): pass my_core_pos around instead of calling it repeatedly

On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inline. In the PSCI
library, at least, we have no need to keep repeatedly calling it and we
can instead pass it around as an argument. This saves on a lot of
redundant calls, speeding the library up a bit.

Change-Id: I137f69bea80d7cac90d7a20ffe98e1ba8d77246f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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