| /rk3399_ARM-atf/plat/mediatek/drivers/gicv3/ |
| H A D | mt_gic_v3.c | 56 val = mmio_read_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_get_pending()
70 mmio_write_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_set_pending()
|
| /rk3399_ARM-atf/plat/amlogic/common/include/ |
| H A D | plat_macros.S | 48 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/nvidia/tegra/include/ |
| H A D | plat_macros.S | 45 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/renesas/common/include/ |
| H A D | plat_macros_gic.S | 44 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/include/drivers/arm/ |
| H A D | gic_common.h | 51 #define GICD_ISPENDR U(0x200) macro
|
| /rk3399_ARM-atf/plat/hisilicon/hikey960/include/ |
| H A D | plat_macros.S | 49 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/hisilicon/hikey/include/ |
| H A D | plat_macros.S | 49 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/mediatek/mt8183/include/ |
| H A D | plat_macros.S | 47 add x7, x26, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/mediatek/mt8173/include/ |
| H A D | plat_macros.S | 47 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/xilinx/versal_net/include/ |
| H A D | plat_macros.S | 77 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/amd/versal2/include/ |
| H A D | plat_macros.S | 77 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/qti/common/inc/aarch64/ |
| H A D | plat_macros.S | 84 add x7, x26, #GICD_ISPENDR
|
| /rk3399_ARM-atf/include/plat/arm/common/aarch64/ |
| H A D | arm_macros.S | 81 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/xilinx/versal/include/ |
| H A D | plat_macros.S | 76 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/mediatek/drivers/cirq/ |
| H A D | mt_cirq.c | 399 LSB_vec = mmio_read_32(base + GICD_ISPENDR + in mt_irq_get_pending_vec()
401 MSB_vec = mmio_read_32(base + GICD_ISPENDR + in mt_irq_get_pending_vec()
405 pending_vec = mmio_read_32(base + GICD_ISPENDR + reg * 4); in mt_irq_get_pending_vec()
|
| /rk3399_ARM-atf/plat/mediatek/drivers/gic600/ |
| H A D | mt_gic_v3.c | 226 val = mmio_read_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_get_pending()
237 mmio_write_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_set_pending()
|
| /rk3399_ARM-atf/drivers/arm/gic/common/ |
| H A D | gic_common.c | 60 return mmio_read_32(base + GICD_ISPENDR + (n << 2)); in gicd_read_ispendr()
173 mmio_write_32(base + GICD_ISPENDR + (n << 2), val); in gicd_write_ispendr()
|
| /rk3399_ARM-atf/include/plat/marvell/armada/common/aarch64/ |
| H A D | marvell_macros.S | 84 add x7, x16, #GICD_ISPENDR
|
| /rk3399_ARM-atf/plat/rockchip/common/include/ |
| H A D | plat_macros.S | 83 add x7, x26, #GICD_ISPENDR
|
| /rk3399_ARM-atf/drivers/arm/gic/v2/ |
| H A D | gicdv2_helpers.c | 59 return mmio_read_32(base + GICD_ISPENDR + (n << 2)); in gicd_read_ispendr()
172 mmio_write_32(base + GICD_ISPENDR + (n << 2), val); in gicd_write_ispendr()
|