1*5bd9c17dSSaurabh Gorecha/* 2*5bd9c17dSSaurabh Gorecha * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*5bd9c17dSSaurabh Gorecha * Copyright (c) 2018,2020, The Linux Foundation. All rights reserved. 4*5bd9c17dSSaurabh Gorecha * 5*5bd9c17dSSaurabh Gorecha * SPDX-License-Identifier: BSD-3-Clause 6*5bd9c17dSSaurabh Gorecha */ 7*5bd9c17dSSaurabh Gorecha 8*5bd9c17dSSaurabh Gorecha#ifndef __PLAT_MACROS_S__ 9*5bd9c17dSSaurabh Gorecha#define __PLAT_MACROS_S__ 10*5bd9c17dSSaurabh Gorecha 11*5bd9c17dSSaurabh Gorecha#include <drivers/arm/gic_common.h> 12*5bd9c17dSSaurabh Gorecha#include <drivers/arm/gicv2.h> 13*5bd9c17dSSaurabh Gorecha#include <drivers/arm/gicv3.h> 14*5bd9c17dSSaurabh Gorecha 15*5bd9c17dSSaurabh Gorecha#include <platform_def.h> 16*5bd9c17dSSaurabh Gorecha 17*5bd9c17dSSaurabh Gorecha.section .rodata.gic_reg_name, "aS" 18*5bd9c17dSSaurabh Gorecha/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 19*5bd9c17dSSaurabh Gorechagicc_regs: 20*5bd9c17dSSaurabh Gorecha .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 21*5bd9c17dSSaurabh Gorecha 22*5bd9c17dSSaurabh Gorecha/* Applicable only to GICv3 with SRE enabled */ 23*5bd9c17dSSaurabh Gorechaicc_regs: 24*5bd9c17dSSaurabh Gorecha .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 25*5bd9c17dSSaurabh Gorecha 26*5bd9c17dSSaurabh Gorecha/* Registers common to both GICv2 and GICv3 */ 27*5bd9c17dSSaurabh Gorechagicd_pend_reg: 28*5bd9c17dSSaurabh Gorecha .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 29*5bd9c17dSSaurabh Gorecha " Offset:\t\t\tvalue\n" 30*5bd9c17dSSaurabh Gorechanewline: 31*5bd9c17dSSaurabh Gorecha .asciz "\n" 32*5bd9c17dSSaurabh Gorechaspacer: 33*5bd9c17dSSaurabh Gorecha .asciz ":\t\t0x" 34*5bd9c17dSSaurabh Gorecha 35*5bd9c17dSSaurabh Gorecha/** Macro : plat_crash_print_regs 36*5bd9c17dSSaurabh Gorecha * This macro allows the crash reporting routine to print GIC registers 37*5bd9c17dSSaurabh Gorecha * in case of an unhandled exception in BL31. This aids in debugging and 38*5bd9c17dSSaurabh Gorecha * this macro can be defined to be empty in case GIC register reporting is 39*5bd9c17dSSaurabh Gorecha * not desired. 40*5bd9c17dSSaurabh Gorecha * The below required platform porting macro 41*5bd9c17dSSaurabh Gorecha * prints out relevant GIC registers whenever an 42*5bd9c17dSSaurabh Gorecha * unhandled exception is taken in BL31. 43*5bd9c17dSSaurabh Gorecha * Clobbers: x0 - x10, x26, x27, sp 44*5bd9c17dSSaurabh Gorecha * --------------------------------------------- 45*5bd9c17dSSaurabh Gorecha */ 46*5bd9c17dSSaurabh Gorecha .macro plat_crash_print_regs 47*5bd9c17dSSaurabh Gorechaprint_gic_regs: 48*5bd9c17dSSaurabh Gorecha ldr x26, =QTI_GICD_BASE 49*5bd9c17dSSaurabh Gorecha ldr x27, =QTI_GICC_BASE 50*5bd9c17dSSaurabh Gorecha 51*5bd9c17dSSaurabh Gorecha /* Check for GICv3 system register access */ 52*5bd9c17dSSaurabh Gorecha mrs x7, id_aa64pfr0_el1 53*5bd9c17dSSaurabh Gorecha ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 54*5bd9c17dSSaurabh Gorecha cmp x7, #1 55*5bd9c17dSSaurabh Gorecha b.ne print_gicv2 56*5bd9c17dSSaurabh Gorecha 57*5bd9c17dSSaurabh Gorecha /* Check for SRE enable */ 58*5bd9c17dSSaurabh Gorecha mrs x8, ICC_SRE_EL3 59*5bd9c17dSSaurabh Gorecha tst x8, #ICC_SRE_SRE_BIT 60*5bd9c17dSSaurabh Gorecha b.eq print_gicv2 61*5bd9c17dSSaurabh Gorecha 62*5bd9c17dSSaurabh Gorecha /* Load the icc reg list to x6 */ 63*5bd9c17dSSaurabh Gorecha adr x6, icc_regs 64*5bd9c17dSSaurabh Gorecha /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 65*5bd9c17dSSaurabh Gorecha mrs x8, ICC_HPPIR0_EL1 66*5bd9c17dSSaurabh Gorecha mrs x9, ICC_HPPIR1_EL1 67*5bd9c17dSSaurabh Gorecha mrs x10, ICC_CTLR_EL3 68*5bd9c17dSSaurabh Gorecha /* Store to the crash buf and print to console */ 69*5bd9c17dSSaurabh Gorecha bl str_in_crash_buf_print 70*5bd9c17dSSaurabh Gorecha b print_gic_common 71*5bd9c17dSSaurabh Gorecha 72*5bd9c17dSSaurabh Gorechaprint_gicv2: 73*5bd9c17dSSaurabh Gorecha /* Load the gicc reg list to x6 */ 74*5bd9c17dSSaurabh Gorecha adr x6, gicc_regs 75*5bd9c17dSSaurabh Gorecha /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 76*5bd9c17dSSaurabh Gorecha ldr w8, [x27, #GICC_HPPIR] 77*5bd9c17dSSaurabh Gorecha ldr w9, [x27, #GICC_AHPPIR] 78*5bd9c17dSSaurabh Gorecha ldr w10, [x27, #GICC_CTLR] 79*5bd9c17dSSaurabh Gorecha /* Store to the crash buf and print to console */ 80*5bd9c17dSSaurabh Gorecha bl str_in_crash_buf_print 81*5bd9c17dSSaurabh Gorecha 82*5bd9c17dSSaurabh Gorechaprint_gic_common: 83*5bd9c17dSSaurabh Gorecha /* Print the GICD_ISPENDR regs */ 84*5bd9c17dSSaurabh Gorecha add x7, x26, #GICD_ISPENDR 85*5bd9c17dSSaurabh Gorecha adr x4, gicd_pend_reg 86*5bd9c17dSSaurabh Gorecha bl asm_print_str 87*5bd9c17dSSaurabh Gorechagicd_ispendr_loop: 88*5bd9c17dSSaurabh Gorecha sub x4, x7, x26 89*5bd9c17dSSaurabh Gorecha cmp x4, #0x280 90*5bd9c17dSSaurabh Gorecha b.eq exit_print_gic_regs 91*5bd9c17dSSaurabh Gorecha bl asm_print_hex 92*5bd9c17dSSaurabh Gorecha 93*5bd9c17dSSaurabh Gorecha adr x4, spacer 94*5bd9c17dSSaurabh Gorecha bl asm_print_str 95*5bd9c17dSSaurabh Gorecha 96*5bd9c17dSSaurabh Gorecha ldr x4, [x7], #8 97*5bd9c17dSSaurabh Gorecha bl asm_print_hex 98*5bd9c17dSSaurabh Gorecha 99*5bd9c17dSSaurabh Gorecha adr x4, newline 100*5bd9c17dSSaurabh Gorecha bl asm_print_str 101*5bd9c17dSSaurabh Gorecha b gicd_ispendr_loop 102*5bd9c17dSSaurabh Gorechaexit_print_gic_regs: 103*5bd9c17dSSaurabh Gorecha 104*5bd9c17dSSaurabh Gorecha .endm 105*5bd9c17dSSaurabh Gorecha 106*5bd9c17dSSaurabh Gorecha#endif /* __PLAT_MACROS_S__ */ 107