108438e24SVarun Wadekar/* 28510376cSVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*7cd336abSVarun Wadekar * Copyright (c) 2015-2020, NVIDIA Corporation. All rights reserved. 408438e24SVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 608438e24SVarun Wadekar */ 708438e24SVarun Wadekar 8c3cf06f1SAntonio Nino Diaz#ifndef PLAT_MACROS_S 9c3cf06f1SAntonio Nino Diaz#define PLAT_MACROS_S 1008438e24SVarun Wadekar 116e756f6dSAmbroise Vincent#include <drivers/arm/gicv2.h> 1208438e24SVarun Wadekar#include <tegra_def.h> 1308438e24SVarun Wadekar 1408438e24SVarun Wadekar.section .rodata.gic_reg_name, "aS" 1508438e24SVarun Wadekargicc_regs: 1608438e24SVarun Wadekar .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 1708438e24SVarun Wadekargicd_pend_reg: 1808438e24SVarun Wadekar .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 1908438e24SVarun Wadekarnewline: 2008438e24SVarun Wadekar .asciz "\n" 2108438e24SVarun Wadekarspacer: 2208438e24SVarun Wadekar .asciz ":\t\t0x" 2308438e24SVarun Wadekar 2408438e24SVarun Wadekar/* --------------------------------------------- 2508438e24SVarun Wadekar * The below macro prints out relevant GIC 2608438e24SVarun Wadekar * registers whenever an unhandled exception is 2708438e24SVarun Wadekar * taken in BL31. 2808438e24SVarun Wadekar * --------------------------------------------- 2908438e24SVarun Wadekar */ 309ff67fa6SGerald Lejeune.macro plat_crash_print_regs 31*7cd336abSVarun Wadekar#ifdef TEGRA_GICC_BASE 3208438e24SVarun Wadekar mov_imm x16, TEGRA_GICC_BASE 3323cd470fSVarun Wadekar 3408438e24SVarun Wadekar /* gicc base address is now in x16 */ 3508438e24SVarun Wadekar adr x6, gicc_regs /* Load the gicc reg list to x6 */ 3608438e24SVarun Wadekar /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 3708438e24SVarun Wadekar ldr w8, [x16, #GICC_HPPIR] 3808438e24SVarun Wadekar ldr w9, [x16, #GICC_AHPPIR] 3908438e24SVarun Wadekar ldr w10, [x16, #GICC_CTLR] 4008438e24SVarun Wadekar /* Store to the crash buf and print to cosole */ 4108438e24SVarun Wadekar bl str_in_crash_buf_print 42*7cd336abSVarun Wadekar#endif 4308438e24SVarun Wadekar /* Print the GICD_ISPENDR regs */ 4423cd470fSVarun Wadekar mov_imm x16, TEGRA_GICD_BASE 4508438e24SVarun Wadekar add x7, x16, #GICD_ISPENDR 4608438e24SVarun Wadekar adr x4, gicd_pend_reg 4708438e24SVarun Wadekar bl asm_print_str 4808438e24SVarun Wadekar2: 4908438e24SVarun Wadekar sub x4, x7, x16 5008438e24SVarun Wadekar cmp x4, #0x280 5108438e24SVarun Wadekar b.eq 1f 5208438e24SVarun Wadekar bl asm_print_hex 5308438e24SVarun Wadekar adr x4, spacer 5408438e24SVarun Wadekar bl asm_print_str 558510376cSVarun Wadekar ldr w4, [x7], #4 5608438e24SVarun Wadekar bl asm_print_hex 5708438e24SVarun Wadekar adr x4, newline 5808438e24SVarun Wadekar bl asm_print_str 5908438e24SVarun Wadekar b 2b 6008438e24SVarun Wadekar1: 6108438e24SVarun Wadekar.endm 6208438e24SVarun Wadekar 63c3cf06f1SAntonio Nino Diaz#endif /* PLAT_MACROS_S */ 64