1*c97857dbSAmit Nagal/* 2*c97857dbSAmit Nagal * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. 3*c97857dbSAmit Nagal * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4*c97857dbSAmit Nagal * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5*c97857dbSAmit Nagal * 6*c97857dbSAmit Nagal * SPDX-License-Identifier: BSD-3-Clause 7*c97857dbSAmit Nagal */ 8*c97857dbSAmit Nagal 9*c97857dbSAmit Nagal#ifndef PLAT_MACROS_S 10*c97857dbSAmit Nagal#define PLAT_MACROS_S 11*c97857dbSAmit Nagal 12*c97857dbSAmit Nagal#include <drivers/arm/gic_common.h> 13*c97857dbSAmit Nagal#include <drivers/arm/gicv2.h> 14*c97857dbSAmit Nagal#include <drivers/arm/gicv3.h> 15*c97857dbSAmit Nagal 16*c97857dbSAmit Nagal#include "../include/platform_def.h" 17*c97857dbSAmit Nagal 18*c97857dbSAmit Nagal.section .rodata.gic_reg_name, "aS" 19*c97857dbSAmit Nagal/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 20*c97857dbSAmit Nagalgicc_regs: 21*c97857dbSAmit Nagal .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 22*c97857dbSAmit Nagal 23*c97857dbSAmit Nagal/* Applicable only to GICv3 with SRE enabled */ 24*c97857dbSAmit Nagalicc_regs: 25*c97857dbSAmit Nagal .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 26*c97857dbSAmit Nagal 27*c97857dbSAmit Nagal/* Registers common to both GICv2 and GICv3 */ 28*c97857dbSAmit Nagalgicd_pend_reg: 29*c97857dbSAmit Nagal .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 30*c97857dbSAmit Nagalnewline: 31*c97857dbSAmit Nagal .asciz "\n" 32*c97857dbSAmit Nagalspacer: 33*c97857dbSAmit Nagal .asciz ":\t\t0x" 34*c97857dbSAmit Nagal 35*c97857dbSAmit Nagal /* --------------------------------------------- 36*c97857dbSAmit Nagal * The below utility macro prints out relevant GIC 37*c97857dbSAmit Nagal * registers whenever an unhandled exception is 38*c97857dbSAmit Nagal * taken in BL31 on platform. 39*c97857dbSAmit Nagal * Expects: GICD base in x16, GICC base in x17 40*c97857dbSAmit Nagal * Clobbers: x0 - x10, sp 41*c97857dbSAmit Nagal * --------------------------------------------- 42*c97857dbSAmit Nagal */ 43*c97857dbSAmit Nagal .macro _print_gic_regs 44*c97857dbSAmit Nagal /* Check for GICv3 system register access */ 45*c97857dbSAmit Nagal mrs x7, id_aa64pfr0_el1 46*c97857dbSAmit Nagal ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 47*c97857dbSAmit Nagal cmp x7, #1 48*c97857dbSAmit Nagal b.ne print_gicv2 49*c97857dbSAmit Nagal 50*c97857dbSAmit Nagal /* Check for SRE enable */ 51*c97857dbSAmit Nagal mrs x8, ICC_SRE_EL3 52*c97857dbSAmit Nagal tst x8, #ICC_SRE_SRE_BIT 53*c97857dbSAmit Nagal b.eq print_gicv2 54*c97857dbSAmit Nagal 55*c97857dbSAmit Nagal /* Load the icc reg list to x6 */ 56*c97857dbSAmit Nagal adr x6, icc_regs 57*c97857dbSAmit Nagal /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 58*c97857dbSAmit Nagal mrs x8, ICC_HPPIR0_EL1 59*c97857dbSAmit Nagal mrs x9, ICC_HPPIR1_EL1 60*c97857dbSAmit Nagal mrs x10, ICC_CTLR_EL3 61*c97857dbSAmit Nagal /* Store to the crash buf and print to console */ 62*c97857dbSAmit Nagal bl str_in_crash_buf_print 63*c97857dbSAmit Nagal b print_gic_common 64*c97857dbSAmit Nagal 65*c97857dbSAmit Nagalprint_gicv2: 66*c97857dbSAmit Nagal /* Load the gicc reg list to x6 */ 67*c97857dbSAmit Nagal adr x6, gicc_regs 68*c97857dbSAmit Nagal /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 69*c97857dbSAmit Nagal ldr w8, [x17, #GICC_HPPIR] 70*c97857dbSAmit Nagal ldr w9, [x17, #GICC_AHPPIR] 71*c97857dbSAmit Nagal ldr w10, [x17, #GICC_CTLR] 72*c97857dbSAmit Nagal /* Store to the crash buf and print to console */ 73*c97857dbSAmit Nagal bl str_in_crash_buf_print 74*c97857dbSAmit Nagal 75*c97857dbSAmit Nagalprint_gic_common: 76*c97857dbSAmit Nagal /* Print the GICD_ISPENDR regs */ 77*c97857dbSAmit Nagal add x7, x16, #GICD_ISPENDR 78*c97857dbSAmit Nagal adr x4, gicd_pend_reg 79*c97857dbSAmit Nagal bl asm_print_str 80*c97857dbSAmit Nagalgicd_ispendr_loop: 81*c97857dbSAmit Nagal sub x4, x7, x16 82*c97857dbSAmit Nagal cmp x4, #0x280 83*c97857dbSAmit Nagal b.eq exit_print_gic_regs 84*c97857dbSAmit Nagal bl asm_print_hex 85*c97857dbSAmit Nagal 86*c97857dbSAmit Nagal adr x4, spacer 87*c97857dbSAmit Nagal bl asm_print_str 88*c97857dbSAmit Nagal 89*c97857dbSAmit Nagal ldr x4, [x7], #8 90*c97857dbSAmit Nagal bl asm_print_hex 91*c97857dbSAmit Nagal 92*c97857dbSAmit Nagal adr x4, newline 93*c97857dbSAmit Nagal bl asm_print_str 94*c97857dbSAmit Nagal b gicd_ispendr_loop 95*c97857dbSAmit Nagalexit_print_gic_regs: 96*c97857dbSAmit Nagal .endm 97*c97857dbSAmit Nagal 98*c97857dbSAmit Nagal /* --------------------------------------------- 99*c97857dbSAmit Nagal * The below required platform porting macro 100*c97857dbSAmit Nagal * prints out relevant GIC and CCI registers 101*c97857dbSAmit Nagal * whenever an unhandled exception is taken in 102*c97857dbSAmit Nagal * BL31. 103*c97857dbSAmit Nagal * Clobbers: x0 - x10, x16, x17, sp 104*c97857dbSAmit Nagal * --------------------------------------------- 105*c97857dbSAmit Nagal */ 106*c97857dbSAmit Nagal .macro plat_crash_print_regs 107*c97857dbSAmit Nagal /* 108*c97857dbSAmit Nagal * Empty for now to handle more platforms variant. 109*c97857dbSAmit Nagal * Uncomment it when versions are stable 110*c97857dbSAmit Nagal */ 111*c97857dbSAmit Nagal /* 112*c97857dbSAmit Nagal mov_imm x17, PLAT_GICD_BASE_VALUE 113*c97857dbSAmit Nagal mov_imm x16, PLAT_GICR_BASE_VALUE 114*c97857dbSAmit Nagal _print_gic_regs 115*c97857dbSAmit Nagal */ 116*c97857dbSAmit Nagal .endm 117*c97857dbSAmit Nagal 118*c97857dbSAmit Nagal#endif /* PLAT_MACROS_S */ 119