11d333e69SMichal Simek/* 2619bc13eSMichal Simek * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. 31d333e69SMichal Simek * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 431b68489SJay Buddhabhatti * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 51d333e69SMichal Simek * 61d333e69SMichal Simek * SPDX-License-Identifier: BSD-3-Clause 71d333e69SMichal Simek */ 81d333e69SMichal Simek 91d333e69SMichal Simek#ifndef PLAT_MACROS_S 101d333e69SMichal Simek#define PLAT_MACROS_S 111d333e69SMichal Simek 121d333e69SMichal Simek#include <drivers/arm/gic_common.h> 131d333e69SMichal Simek#include <drivers/arm/gicv2.h> 141d333e69SMichal Simek#include <drivers/arm/gicv3.h> 151d333e69SMichal Simek 161d333e69SMichal Simek#include "../include/platform_def.h" 171d333e69SMichal Simek 181d333e69SMichal Simek.section .rodata.gic_reg_name, "aS" 191d333e69SMichal Simek/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 201d333e69SMichal Simekgicc_regs: 211d333e69SMichal Simek .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 221d333e69SMichal Simek 231d333e69SMichal Simek/* Applicable only to GICv3 with SRE enabled */ 241d333e69SMichal Simekicc_regs: 251d333e69SMichal Simek .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 261d333e69SMichal Simek 271d333e69SMichal Simek/* Registers common to both GICv2 and GICv3 */ 281d333e69SMichal Simekgicd_pend_reg: 291d333e69SMichal Simek .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 301d333e69SMichal Simeknewline: 311d333e69SMichal Simek .asciz "\n" 321d333e69SMichal Simekspacer: 331d333e69SMichal Simek .asciz ":\t\t0x" 341d333e69SMichal Simek 351d333e69SMichal Simek /* --------------------------------------------- 361d333e69SMichal Simek * The below utility macro prints out relevant GIC 371d333e69SMichal Simek * registers whenever an unhandled exception is 381d333e69SMichal Simek * taken in BL31 on Versal NET platform. 391d333e69SMichal Simek * Expects: GICD base in x16, GICC base in x17 401d333e69SMichal Simek * Clobbers: x0 - x10, sp 411d333e69SMichal Simek * --------------------------------------------- 421d333e69SMichal Simek */ 431d333e69SMichal Simek .macro versal_net_print_gic_regs 441d333e69SMichal Simek /* Check for GICv3 system register access */ 451d333e69SMichal Simek mrs x7, id_aa64pfr0_el1 461d333e69SMichal Simek ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 471d333e69SMichal Simek cmp x7, #1 481d333e69SMichal Simek b.ne print_gicv2 491d333e69SMichal Simek 501d333e69SMichal Simek /* Check for SRE enable */ 511d333e69SMichal Simek mrs x8, ICC_SRE_EL3 521d333e69SMichal Simek tst x8, #ICC_SRE_SRE_BIT 531d333e69SMichal Simek b.eq print_gicv2 541d333e69SMichal Simek 551d333e69SMichal Simek /* Load the icc reg list to x6 */ 561d333e69SMichal Simek adr x6, icc_regs 571d333e69SMichal Simek /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 581d333e69SMichal Simek mrs x8, ICC_HPPIR0_EL1 591d333e69SMichal Simek mrs x9, ICC_HPPIR1_EL1 601d333e69SMichal Simek mrs x10, ICC_CTLR_EL3 611d333e69SMichal Simek /* Store to the crash buf and print to console */ 621d333e69SMichal Simek bl str_in_crash_buf_print 631d333e69SMichal Simek b print_gic_common 641d333e69SMichal Simek 651d333e69SMichal Simekprint_gicv2: 661d333e69SMichal Simek /* Load the gicc reg list to x6 */ 671d333e69SMichal Simek adr x6, gicc_regs 681d333e69SMichal Simek /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 691d333e69SMichal Simek ldr w8, [x17, #GICC_HPPIR] 701d333e69SMichal Simek ldr w9, [x17, #GICC_AHPPIR] 711d333e69SMichal Simek ldr w10, [x17, #GICC_CTLR] 721d333e69SMichal Simek /* Store to the crash buf and print to console */ 731d333e69SMichal Simek bl str_in_crash_buf_print 741d333e69SMichal Simek 751d333e69SMichal Simekprint_gic_common: 761d333e69SMichal Simek /* Print the GICD_ISPENDR regs */ 771d333e69SMichal Simek add x7, x16, #GICD_ISPENDR 781d333e69SMichal Simek adr x4, gicd_pend_reg 791d333e69SMichal Simek bl asm_print_str 801d333e69SMichal Simekgicd_ispendr_loop: 811d333e69SMichal Simek sub x4, x7, x16 821d333e69SMichal Simek cmp x4, #0x280 831d333e69SMichal Simek b.eq exit_print_gic_regs 841d333e69SMichal Simek bl asm_print_hex 851d333e69SMichal Simek 861d333e69SMichal Simek adr x4, spacer 871d333e69SMichal Simek bl asm_print_str 881d333e69SMichal Simek 891d333e69SMichal Simek ldr x4, [x7], #8 901d333e69SMichal Simek bl asm_print_hex 911d333e69SMichal Simek 921d333e69SMichal Simek adr x4, newline 931d333e69SMichal Simek bl asm_print_str 941d333e69SMichal Simek b gicd_ispendr_loop 951d333e69SMichal Simekexit_print_gic_regs: 961d333e69SMichal Simek .endm 971d333e69SMichal Simek 981d333e69SMichal Simek /* --------------------------------------------- 991d333e69SMichal Simek * The below required platform porting macro 1001d333e69SMichal Simek * prints out relevant GIC and CCI registers 1011d333e69SMichal Simek * whenever an unhandled exception is taken in 1021d333e69SMichal Simek * BL31. 1031d333e69SMichal Simek * Clobbers: x0 - x10, x16, x17, sp 1041d333e69SMichal Simek * --------------------------------------------- 1051d333e69SMichal Simek */ 1061d333e69SMichal Simek .macro plat_crash_print_regs 1071d333e69SMichal Simek /* 1081d333e69SMichal Simek * Empty for now to handle more platforms variant. 1091d333e69SMichal Simek * Uncomment it when versions are stable 1101d333e69SMichal Simek */ 1111d333e69SMichal Simek /* 112*79953190SJay Buddhabhatti mov_imm x17, PLAT_ARM_GICD_BASE 113*79953190SJay Buddhabhatti mov_imm x16, PLAT_ARM_GICR_BASE 1141d333e69SMichal Simek versal_net_print_gic_regs 1151d333e69SMichal Simek */ 1161d333e69SMichal Simek .endm 1171d333e69SMichal Simek 1181d333e69SMichal Simek#endif /* PLAT_MACROS_S */ 119