1b4315306SDan Handley/* 26c6a470fSAlexei Fedorov * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5b4315306SDan Handley */ 6c3cf06f1SAntonio Nino Diaz#ifndef ARM_MACROS_S 7c3cf06f1SAntonio Nino Diaz#define ARM_MACROS_S 8b4315306SDan Handley 909d40e0eSAntonio Nino Diaz#include <drivers/arm/gic_common.h> 1009d40e0eSAntonio Nino Diaz#include <drivers/arm/gicv2.h> 1109d40e0eSAntonio Nino Diaz#include <drivers/arm/gicv3.h> 12b4315306SDan Handley#include <platform_def.h> 13b4315306SDan Handley 14b4315306SDan Handley.section .rodata.gic_reg_name, "aS" 15f14d1886SSoby Mathew/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 16b4315306SDan Handleygicc_regs: 17b4315306SDan Handley .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 18f14d1886SSoby Mathew 19f14d1886SSoby Mathew/* Applicable only to GICv3 with SRE enabled */ 20f14d1886SSoby Mathewicc_regs: 21f14d1886SSoby Mathew .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 22f14d1886SSoby Mathew 23f14d1886SSoby Mathew/* Registers common to both GICv2 and GICv3 */ 24b4315306SDan Handleygicd_pend_reg: 256c6a470fSAlexei Fedorov .asciz "gicd_ispendr regs (Offsets 0x200-0x278)\nOffset\t\t\tValue\n" 26b4315306SDan Handleynewline: 27b4315306SDan Handley .asciz "\n" 28b4315306SDan Handleyspacer: 29b4315306SDan Handley .asciz ":\t\t 0x" 306c6a470fSAlexei Fedorovprefix: 316c6a470fSAlexei Fedorov .asciz "0x" 32b4315306SDan Handley 33b4315306SDan Handley /* --------------------------------------------- 34b4315306SDan Handley * The below utility macro prints out relevant GIC 35b4315306SDan Handley * registers whenever an unhandled exception is 36d178637dSJuan Castillo * taken in BL31 on ARM standard platforms. 37b4315306SDan Handley * Expects: GICD base in x16, GICC base in x17 38b4315306SDan Handley * Clobbers: x0 - x10, sp 39b4315306SDan Handley * --------------------------------------------- 40b4315306SDan Handley */ 41b4315306SDan Handley .macro arm_print_gic_regs 42*f1df8f10SMoritz Fischer /* Check for GICv3/v4 system register access. 43*f1df8f10SMoritz Fischer * ID_AA64PFR0_GIC indicates presence of the CPU 44*f1df8f10SMoritz Fischer * system registers by either 0b0011 or 0xb0001. 45*f1df8f10SMoritz Fischer * A value of 0b000 means CPU system registers aren't 46*f1df8f10SMoritz Fischer * available and the code needs to use the memory 47*f1df8f10SMoritz Fischer * mapped registers like in GICv2. 48*f1df8f10SMoritz Fischer */ 49f14d1886SSoby Mathew mrs x7, id_aa64pfr0_el1 50f14d1886SSoby Mathew ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 51*f1df8f10SMoritz Fischer cmp x7, #0 52*f1df8f10SMoritz Fischer b.eq print_gicv2 53f14d1886SSoby Mathew 54f14d1886SSoby Mathew /* Check for SRE enable */ 55f14d1886SSoby Mathew mrs x8, ICC_SRE_EL3 56f14d1886SSoby Mathew tst x8, #ICC_SRE_SRE_BIT 57f14d1886SSoby Mathew b.eq print_gicv2 58f14d1886SSoby Mathew 59f14d1886SSoby Mathew /* Load the icc reg list to x6 */ 60f14d1886SSoby Mathew adr x6, icc_regs 61f14d1886SSoby Mathew /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 62f14d1886SSoby Mathew mrs x8, ICC_HPPIR0_EL1 63f14d1886SSoby Mathew mrs x9, ICC_HPPIR1_EL1 64f14d1886SSoby Mathew mrs x10, ICC_CTLR_EL3 65f14d1886SSoby Mathew /* Store to the crash buf and print to console */ 66f14d1886SSoby Mathew bl str_in_crash_buf_print 67f14d1886SSoby Mathew b print_gic_common 68f14d1886SSoby Mathew 69f14d1886SSoby Mathewprint_gicv2: 70b4315306SDan Handley /* Load the gicc reg list to x6 */ 71b4315306SDan Handley adr x6, gicc_regs 72b4315306SDan Handley /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 73b4315306SDan Handley ldr w8, [x17, #GICC_HPPIR] 74b4315306SDan Handley ldr w9, [x17, #GICC_AHPPIR] 75b4315306SDan Handley ldr w10, [x17, #GICC_CTLR] 76b4315306SDan Handley /* Store to the crash buf and print to console */ 77b4315306SDan Handley bl str_in_crash_buf_print 78b4315306SDan Handley 79f14d1886SSoby Mathewprint_gic_common: 80b4315306SDan Handley /* Print the GICD_ISPENDR regs */ 81b4315306SDan Handley add x7, x16, #GICD_ISPENDR 82b4315306SDan Handley adr x4, gicd_pend_reg 83b4315306SDan Handley bl asm_print_str 84b4315306SDan Handleygicd_ispendr_loop: 85b4315306SDan Handley sub x4, x7, x16 86b4315306SDan Handley cmp x4, #0x280 87b4315306SDan Handley b.eq exit_print_gic_regs 886c6a470fSAlexei Fedorov 896c6a470fSAlexei Fedorov /* Print "0x" */ 906c6a470fSAlexei Fedorov adr x4, prefix 916c6a470fSAlexei Fedorov bl asm_print_str 926c6a470fSAlexei Fedorov 936c6a470fSAlexei Fedorov /* Print offset */ 946c6a470fSAlexei Fedorov sub x4, x7, x16 956c6a470fSAlexei Fedorov mov x5, #12 966c6a470fSAlexei Fedorov bl asm_print_hex_bits 97b4315306SDan Handley 98b4315306SDan Handley adr x4, spacer 99b4315306SDan Handley bl asm_print_str 100b4315306SDan Handley 101b4315306SDan Handley ldr x4, [x7], #8 102b4315306SDan Handley bl asm_print_hex 103b4315306SDan Handley 104b4315306SDan Handley adr x4, newline 105b4315306SDan Handley bl asm_print_str 106b4315306SDan Handley b gicd_ispendr_loop 107b4315306SDan Handleyexit_print_gic_regs: 108b4315306SDan Handley .endm 109b4315306SDan Handley 110c3cf06f1SAntonio Nino Diaz#endif /* ARM_MACROS_S */ 111