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Searched refs:reg (Results 1 – 25 of 9128) sorted by relevance

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/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c71 u32 reg; in wait_refresh_op_complete() local
75 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
77 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
117 u32 reg, freq_par, tmp; in ddr3_dfs_high_2_low() local
133 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
135 reg |= (1 << REG_DFS_DLLNEXTSTATE_OFFS); in ddr3_dfs_high_2_low()
136 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
142 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
144 reg &= ~(1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_high_2_low()
146 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
[all …]
H A Dddr3_write_leveling.c67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
76 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_write_leveling_hw()
77 if (reg & (1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)) { in ddr3_write_leveling_hw()
80 reg & ~(1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)); in ddr3_write_leveling_hw()
84 reg = 1 << REG_DRAM_TRAINING_WL_OFFS; in ddr3_write_leveling_hw()
86 reg |= (COUNT_HW_WL << REG_DRAM_TRAINING_RETEST_OFFS); in ddr3_write_leveling_hw()
87 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
88 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
90 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_write_leveling_hw()
92 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_write_leveling_hw()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/
H A Dasm-eva.h19 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" argument
20 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" argument
21 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" argument
22 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" argument
23 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" argument
24 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" argument
25 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" argument
26 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" argument
27 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" argument
28 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" argument
[all …]
/OK3568_Linux_fs/kernel/arch/parisc/include/asm/
H A Dasmregs.h11 rp: .reg %r2
12 arg3: .reg %r23
13 arg2: .reg %r24
14 arg1: .reg %r25
15 arg0: .reg %r26
16 dp: .reg %r27
17 ret0: .reg %r28
18 ret1: .reg %r29
19 sl: .reg %r29
20 sp: .reg %r30
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Danalogix_dp_reg.c37 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) in analogix_dp_write() argument
40 writel(val, dp->reg_base + reg); in analogix_dp_write()
41 writel(val, dp->reg_base + reg); in analogix_dp_write()
44 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) in analogix_dp_read() argument
46 readl(dp->reg_base + reg); in analogix_dp_read()
48 return readl(dp->reg_base + reg); in analogix_dp_read()
53 u32 reg; in analogix_dp_enable_video_mute() local
56 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
57 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
58 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); in analogix_dp_enable_video_mute()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.c25 unsigned int reg; in exynos_dp_enable_video_input() local
27 reg = readl(&dp_regs->video_ctl1); in exynos_dp_enable_video_input()
28 reg &= ~VIDEO_EN_MASK; in exynos_dp_enable_video_input()
32 reg |= VIDEO_EN_MASK; in exynos_dp_enable_video_input()
34 writel(reg, &dp_regs->video_ctl1); in exynos_dp_enable_video_input()
42 unsigned int reg; in exynos_dp_enable_video_bist() local
44 reg = readl(&dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
45 reg &= ~VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
49 reg |= VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
51 writel(reg, &dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
[all …]
H A Dexynos_mipi_dsi_lowlevel.c21 unsigned int reg; in exynos_mipi_dsi_func_reset() local
26 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
28 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
30 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
35 unsigned int reg = 0; in exynos_mipi_dsi_sw_reset() local
40 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
42 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
43 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_sw_reset()
45 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
52 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release() local
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.c22 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) in analogix_dp_write() argument
26 writel(val, dp->reg_base + reg); in analogix_dp_write()
29 writel(val, dp->reg_base + reg); in analogix_dp_write()
32 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) in analogix_dp_read() argument
35 readl(dp->reg_base + reg); in analogix_dp_read()
37 return readl(dp->reg_base + reg); in analogix_dp_read()
42 u32 reg; in analogix_dp_enable_video_mute() local
45 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
46 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
47 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); in analogix_dp_enable_video_mute()
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/qla2xxx/
H A Dqla_dbg.c108 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla27xx_dump_mpi_ram() local
121 wrt_reg_word(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM); in qla27xx_dump_mpi_ram()
122 wrt_reg_word(&reg->mailbox1, LSW(addr)); in qla27xx_dump_mpi_ram()
123 wrt_reg_word(&reg->mailbox8, MSW(addr)); in qla27xx_dump_mpi_ram()
125 wrt_reg_word(&reg->mailbox2, MSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
126 wrt_reg_word(&reg->mailbox3, LSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
127 wrt_reg_word(&reg->mailbox6, MSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
128 wrt_reg_word(&reg->mailbox7, LSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
130 wrt_reg_word(&reg->mailbox4, MSW(dwords)); in qla27xx_dump_mpi_ram()
131 wrt_reg_word(&reg->mailbox5, LSW(dwords)); in qla27xx_dump_mpi_ram()
[all …]
/OK3568_Linux_fs/kernel/tools/testing/selftests/powerpc/include/
H A Dvmx_asm.h9 #define PUSH_VMX(pos,reg) \ argument
10 li reg,pos; \
11 stvx v20,reg,%r1; \
12 addi reg,reg,16; \
13 stvx v21,reg,%r1; \
14 addi reg,reg,16; \
15 stvx v22,reg,%r1; \
16 addi reg,reg,16; \
17 stvx v23,reg,%r1; \
18 addi reg,reg,16; \
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/s5p-jpeg/
H A Djpeg-hw-s5p.c19 unsigned long reg; in s5p_jpeg_reset() local
22 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
24 while (reg != 0) { in s5p_jpeg_reset()
26 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
37 unsigned long reg, m; in s5p_jpeg_input_raw_mode() local
45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
46 reg &= ~S5P_MOD_SEL_MASK; in s5p_jpeg_input_raw_mode()
47 reg |= m; in s5p_jpeg_input_raw_mode()
48 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
53 unsigned long reg, m; in s5p_jpeg_proc_mode() local
[all …]
H A Djpeg-hw-exynos4.c18 unsigned int reg; in exynos4_jpeg_sw_reset() local
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
21 writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE), in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
34 unsigned int reg; in exynos4_jpeg_set_enc_dec_mode() local
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
39 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
43 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
[all …]
H A Djpeg-hw-exynos3250.c20 u32 reg = 1; in exynos3250_jpeg_reset() local
25 while (reg != 0 && --count > 0) { in exynos3250_jpeg_reset()
28 reg = readl(regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
31 reg = 0; in exynos3250_jpeg_reset()
34 while (reg != 1 && --count > 0) { in exynos3250_jpeg_reset()
38 reg = readl(regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
62 u32 reg; in exynos3250_jpeg_clk_set() local
64 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; in exynos3250_jpeg_clk_set()
66 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set()
71 u32 reg; in exynos3250_jpeg_input_raw_fmt() local
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/
H A Darm32_macros.S8 .macro read_midr reg argument
9 mrc p15, 0, \reg, c0, c0, 0
12 .macro read_ctr reg argument
13 mrc p15, 0, \reg, c0, c0, 1
16 .macro read_mpidr reg argument
17 mrc p15, 0, \reg, c0, c0, 5
20 .macro read_sctlr reg argument
21 mrc p15, 0, \reg, c1, c0, 0
24 .macro write_sctlr reg argument
25 mcr p15, 0, \reg, c1, c0, 0
[all …]
/OK3568_Linux_fs/kernel/drivers/media/cec/platform/s5p/
H A Dexynos_hdmi_cecctrl.c26 unsigned int reg; in s5p_cec_set_divider() local
30 if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, &reg)) { in s5p_cec_set_divider()
35 reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16); in s5p_cec_set_divider()
37 if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) { in s5p_cec_set_divider()
44 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3); in s5p_cec_set_divider()
45 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2); in s5p_cec_set_divider()
46 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1); in s5p_cec_set_divider()
47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider()
52 u8 reg; in s5p_cec_enable_rx() local
54 reg = readb(cec->reg + S5P_CEC_RX_CTRL); in s5p_cec_enable_rx()
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/tegra/
H A Dtegra210.c20 .reg = 0x228,
24 .reg = 0x2e8,
34 .reg = 0x228,
38 .reg = 0x2f4,
48 .reg = 0x228,
52 .reg = 0x2e8,
62 .reg = 0x228,
66 .reg = 0x2f4,
76 .reg = 0x228,
80 .reg = 0x2ec,
[all …]
H A Dtegra30.c44 .reg = 0x228,
48 .reg = 0x2e8,
58 .reg = 0x228,
62 .reg = 0x2f4,
72 .reg = 0x228,
76 .reg = 0x2e8,
86 .reg = 0x228,
90 .reg = 0x2f4,
100 .reg = 0x228,
104 .reg = 0x2ec,
[all …]
H A Dtegra114.c23 .reg = 0x228,
27 .reg = 0x2e8,
37 .reg = 0x228,
41 .reg = 0x2f4,
51 .reg = 0x228,
55 .reg = 0x2e8,
65 .reg = 0x228,
69 .reg = 0x2f4,
79 .reg = 0x228,
83 .reg = 0x2ec,
[all …]
H A Dtegra124.c23 .reg = 0x228,
27 .reg = 0x2e8,
37 .reg = 0x228,
41 .reg = 0x2f4,
51 .reg = 0x228,
55 .reg = 0x2e8,
65 .reg = 0x228,
69 .reg = 0x2f4,
79 .reg = 0x228,
83 .reg = 0x2ec,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Darmada-38x-controlcenterdc.dts60 reg = <0x00000000 0x10000000>; /* 256 MB */
80 reg = <0>;
97 reg = <0>; /* Chip select 0 */
104 reg = <1>; /* Chip select 1 */
116 reg = <0x21>;
123 reg = <0x22>;
129 reg = <0x23>;
135 reg = <0x24>;
141 reg = <0x25>;
147 reg = <0x26>;
[all …]
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/jpegd/
H A Dhal_jpegd_vdpu2.c36 static MPP_RET jpegd_regs_init(JpegRegSet *reg) in jpegd_regs_init() argument
39 memset(reg, 0, sizeof(JpegRegSet)); in jpegd_regs_init()
40 reg->reg50_dec_ctrl.sw_dec_out_tiled_e = 0; in jpegd_regs_init()
41 reg->reg50_dec_ctrl.sw_dec_scmd_dis = DEC_SCMD_DISABLE; in jpegd_regs_init()
42 reg->reg50_dec_ctrl.sw_dec_latency = DEC_LATENCY_COMPENSATION; in jpegd_regs_init()
44 reg->reg54_endian.sw_dec_in_endian = DEC_BIG_ENDIAN; in jpegd_regs_init()
45 reg->reg54_endian.sw_dec_out_endian = DEC_LITTLE_ENDIAN; in jpegd_regs_init()
46 reg->reg54_endian.sw_dec_strendian_e = DEC_LITTLE_ENDIAN; in jpegd_regs_init()
47 reg->reg54_endian.sw_dec_outswap32_e = DEC_LITTLE_ENDIAN; in jpegd_regs_init()
48 reg->reg54_endian.sw_dec_inswap32_e = 1; in jpegd_regs_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/riva/
H A Dnvreg.h44 #define DEVICE_ACCESS(device,reg) \ argument
45 nvCONTROL[(NV_##device##_##reg)/4]
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) argument
49 #define DEVICE_PRINT(device,reg) \ argument
50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) argument
58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) argument
63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument
68 REG_SET_N(reg, 2, init_value, \
69 FN(reg, f1), v1,\
70 FN(reg, f2), v2)
72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
73 REG_SET_N(reg, 3, init_value, \
74 FN(reg, f1), v1,\
75 FN(reg, f2), v2,\
76 FN(reg, f3), v3)
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c30 u32 reg; in enable_ocotp_clk() local
32 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
34 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
36 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
37 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
84 u32 reg; in enable_usboh3_clk() local
86 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
88 reg |= MXC_CCM_CCGR6_USBOH3_MASK; in enable_usboh3_clk()
90 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); in enable_usboh3_clk()
91 __raw_writel(reg, &imx_ccm->CCGR6); in enable_usboh3_clk()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/microchip/
H A Dencx24j600-regmap.c60 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, in regmap_encx24j600_sfr_read() argument
64 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read()
65 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_read()
71 if (reg < 0x80) { in regmap_encx24j600_sfr_read()
81 switch (reg) { in regmap_encx24j600_sfr_read()
104 tx_buf[i++] = reg; in regmap_encx24j600_sfr_read()
112 u8 reg, u8 *val, size_t len, in regmap_encx24j600_sfr_update() argument
115 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update()
116 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_update()
120 { .tx_buf = &reg, .len = sizeof(reg), }, in regmap_encx24j600_sfr_update()
[all …]

12345678910>>...366