Lines Matching refs:reg
30 u32 reg; in enable_ocotp_clk() local
32 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
34 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
36 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
37 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
84 u32 reg; in enable_usboh3_clk() local
86 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
88 reg |= MXC_CCM_CCGR6_USBOH3_MASK; in enable_usboh3_clk()
90 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); in enable_usboh3_clk()
91 __raw_writel(reg, &imx_ccm->CCGR6); in enable_usboh3_clk()
157 u32 reg; in enable_i2c_clk() local
167 reg = __raw_readl(&imx_ccm->CCGR2); in enable_i2c_clk()
169 reg |= mask; in enable_i2c_clk()
171 reg &= ~mask; in enable_i2c_clk()
172 __raw_writel(reg, &imx_ccm->CCGR2); in enable_i2c_clk()
183 reg = __raw_readl(addr); in enable_i2c_clk()
185 reg |= mask; in enable_i2c_clk()
187 reg &= ~mask; in enable_i2c_clk()
188 __raw_writel(reg, addr); in enable_i2c_clk()
197 u32 reg; in enable_spi_clk() local
204 reg = __raw_readl(&imx_ccm->CCGR1); in enable_spi_clk()
206 reg |= mask; in enable_spi_clk()
208 reg &= ~mask; in enable_spi_clk()
209 __raw_writel(reg, &imx_ccm->CCGR1); in enable_spi_clk()
311 u32 reg, freq; in get_mcu_main_clk() local
313 reg = __raw_readl(&imx_ccm->cacrr); in get_mcu_main_clk()
314 reg &= MXC_CCM_CACRR_ARM_PODF_MASK; in get_mcu_main_clk()
315 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET; in get_mcu_main_clk()
318 return freq / (reg + 1); in get_mcu_main_clk()
323 u32 reg, div = 0, freq = 0; in get_periph_clk() local
325 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
326 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { in get_periph_clk()
327 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> in get_periph_clk()
329 reg = __raw_readl(&imx_ccm->cbcmr); in get_periph_clk()
330 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK; in get_periph_clk()
331 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET; in get_periph_clk()
333 switch (reg) { in get_periph_clk()
345 reg = __raw_readl(&imx_ccm->cbcmr); in get_periph_clk()
346 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK; in get_periph_clk()
347 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; in get_periph_clk()
349 switch (reg) { in get_periph_clk()
373 u32 reg, ipg_podf; in get_ipg_clk() local
375 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
376 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK; in get_ipg_clk()
377 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET; in get_ipg_clk()
384 u32 reg, perclk_podf; in get_ipg_per_clk() local
386 reg = __raw_readl(&imx_ccm->cscmr1); in get_ipg_per_clk()
389 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) in get_ipg_per_clk()
393 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; in get_ipg_per_clk()
400 u32 reg, uart_podf; in get_uart_clk() local
402 reg = __raw_readl(&imx_ccm->cscdr1); in get_uart_clk()
406 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) in get_uart_clk()
410 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; in get_uart_clk()
411 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; in get_uart_clk()
418 u32 reg, cspi_podf; in get_cspi_clk() local
420 reg = __raw_readl(&imx_ccm->cscdr2); in get_cspi_clk()
421 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> in get_cspi_clk()
426 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) in get_cspi_clk()
555 u32 reg = 0; in enable_pll_video() local
599 reg = readl(&imx_ccm->analog_pll_video); in enable_pll_video()
600 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) { in enable_pll_video()
620 u32 reg = 0; in mxs_set_lcdclk() local
639 reg = readl(&imx_ccm->cscdr2); in mxs_set_lcdclk()
641 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0) in mxs_set_lcdclk()
647 reg = readl(&imx_ccm->cscdr2); in mxs_set_lcdclk()
649 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0) in mxs_set_lcdclk()
772 u32 reg = 0; in enable_lcdif_clock() local
804 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
805 reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK | in enable_lcdif_clock()
807 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
810 reg = readl(&imx_ccm->cscdr3); in enable_lcdif_clock()
811 reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK; in enable_lcdif_clock()
812 reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET; in enable_lcdif_clock()
813 writel(reg, &imx_ccm->cscdr3); in enable_lcdif_clock()
815 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
816 reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK | in enable_lcdif_clock()
818 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
827 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
828 reg &= ~lcdif_ccgr3_mask; in enable_lcdif_clock()
829 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
831 reg = readl(&imx_ccm->CCGR2); in enable_lcdif_clock()
832 reg &= ~MXC_CCM_CCGR2_LCD_MASK; in enable_lcdif_clock()
833 writel(reg, &imx_ccm->CCGR2); in enable_lcdif_clock()
837 reg = readl(&imx_ccm->cscdr2); in enable_lcdif_clock()
838 reg &= ~lcdif_clk_sel_mask; in enable_lcdif_clock()
839 writel(reg, &imx_ccm->cscdr2); in enable_lcdif_clock()
842 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
843 reg |= lcdif_ccgr3_mask; in enable_lcdif_clock()
844 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
846 reg = readl(&imx_ccm->CCGR2); in enable_lcdif_clock()
847 reg |= MXC_CCM_CCGR2_LCD_MASK; in enable_lcdif_clock()
848 writel(reg, &imx_ccm->CCGR2); in enable_lcdif_clock()
859 u32 reg = 0; in enable_qspi_clk() local
867 reg = readl(&imx_ccm->cscmr1); in enable_qspi_clk()
868 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | in enable_qspi_clk()
870 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | in enable_qspi_clk()
872 writel(reg, &imx_ccm->cscmr1); in enable_qspi_clk()
887 reg = readl(&imx_ccm->cs2cdr); in enable_qspi_clk()
888 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | in enable_qspi_clk()
891 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | in enable_qspi_clk()
893 writel(reg, &imx_ccm->cs2cdr); in enable_qspi_clk()
908 u32 reg = 0; in enable_fec_anatop_clock() local
917 reg = readl(&anatop->pll_enet); in enable_fec_anatop_clock()
920 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; in enable_fec_anatop_clock()
921 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); in enable_fec_anatop_clock()
926 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; in enable_fec_anatop_clock()
927 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); in enable_fec_anatop_clock()
932 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || in enable_fec_anatop_clock()
933 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { in enable_fec_anatop_clock()
934 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; in enable_fec_anatop_clock()
935 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
946 reg |= BM_ANADIG_PLL_ENET_ENABLE; in enable_fec_anatop_clock()
948 reg |= BM_ANADIG_PLL_ENET2_ENABLE; in enable_fec_anatop_clock()
949 reg &= ~BM_ANADIG_PLL_ENET_BYPASS; in enable_fec_anatop_clock()
950 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
954 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
955 reg &= ~MXC_CCM_CCGR3_ENET_MASK; in enable_fec_anatop_clock()
956 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
962 reg = readl(&imx_ccm->chsccdr); in enable_fec_anatop_clock()
963 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK in enable_fec_anatop_clock()
967 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET); in enable_fec_anatop_clock()
969 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET); in enable_fec_anatop_clock()
970 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET); in enable_fec_anatop_clock()
971 writel(reg, &imx_ccm->chsccdr); in enable_fec_anatop_clock()
974 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
975 reg |= MXC_CCM_CCGR3_ENET_MASK; in enable_fec_anatop_clock()
976 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
1051 u32 reg = 0; in enable_enet_pll() local
1054 reg = readl(&imx_ccm->analog_pll_enet); in enable_enet_pll()
1055 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; in enable_enet_pll()
1056 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1057 reg |= BM_ANADIG_PLL_SYS_ENABLE; in enable_enet_pll()
1064 reg &= ~BM_ANADIG_PLL_SYS_BYPASS; in enable_enet_pll()
1065 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1066 reg |= en; in enable_enet_pll()
1067 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1159 u32 reg; in hab_caam_clock_enable() local
1163 reg = __raw_readl(&imx_ccm->CCGR0); in hab_caam_clock_enable()
1165 reg |= MXC_CCM_CCGR0_DCP_CLK_MASK; in hab_caam_clock_enable()
1167 reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK; in hab_caam_clock_enable()
1168 __raw_writel(reg, &imx_ccm->CCGR0); in hab_caam_clock_enable()
1171 reg = __raw_readl(&imx_ccm->CCGR0); in hab_caam_clock_enable()
1173 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | in hab_caam_clock_enable()
1177 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | in hab_caam_clock_enable()
1180 __raw_writel(reg, &imx_ccm->CCGR0); in hab_caam_clock_enable()
1184 reg = __raw_readl(&imx_ccm->CCGR6); in hab_caam_clock_enable()
1186 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; in hab_caam_clock_enable()
1188 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK; in hab_caam_clock_enable()
1189 __raw_writel(reg, &imx_ccm->CCGR6); in hab_caam_clock_enable()
1304 int reg; in enable_ipu_clock() local
1305 reg = readl(&mxc_ccm->CCGR3); in enable_ipu_clock()
1306 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; in enable_ipu_clock()
1307 writel(reg, &mxc_ccm->CCGR3); in enable_ipu_clock()
1321 int reg; in disable_ldb_di_clock_sources() local
1324 reg = readl(&mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
1327 reg |= 0x80008080; in disable_ldb_di_clock_sources()
1329 reg |= 0x80808080; in disable_ldb_di_clock_sources()
1330 writel(reg, &mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
1333 reg = readl(&mxc_ccm->analog_pfd_480); in disable_ldb_di_clock_sources()
1334 reg |= 0x80808080; in disable_ldb_di_clock_sources()
1335 writel(reg, &mxc_ccm->analog_pfd_480); in disable_ldb_di_clock_sources()
1338 reg = readl(&mxc_ccm->analog_pll_video); in disable_ldb_di_clock_sources()
1339 reg &= ~(1 << 13); in disable_ldb_di_clock_sources()
1340 writel(reg, &mxc_ccm->analog_pll_video); in disable_ldb_di_clock_sources()
1346 int reg; in enable_ldb_di_clock_sources() local
1348 reg = readl(&mxc_ccm->analog_pfd_528); in enable_ldb_di_clock_sources()
1350 reg &= ~(0x80008080); in enable_ldb_di_clock_sources()
1352 reg &= ~(0x80808080); in enable_ldb_di_clock_sources()
1353 writel(reg, &mxc_ccm->analog_pfd_528); in enable_ldb_di_clock_sources()
1355 reg = readl(&mxc_ccm->analog_pfd_480); in enable_ldb_di_clock_sources()
1356 reg &= ~(0x80808080); in enable_ldb_di_clock_sources()
1357 writel(reg, &mxc_ccm->analog_pfd_480); in enable_ldb_di_clock_sources()
1367 int reg; in select_ldb_di_clock_source() local
1394 reg = readl(&mxc_ccm->ccdr); in select_ldb_di_clock_source()
1395 reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK; in select_ldb_di_clock_source()
1396 writel(reg, &mxc_ccm->ccdr); in select_ldb_di_clock_source()
1399 reg = readl(&mxc_ccm->cbcmr); in select_ldb_di_clock_source()
1400 reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL; in select_ldb_di_clock_source()
1401 writel(reg, &mxc_ccm->cbcmr); in select_ldb_di_clock_source()
1407 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1408 reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL; in select_ldb_di_clock_source()
1409 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1415 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1416 reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL; in select_ldb_di_clock_source()
1417 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1420 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1421 reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) in select_ldb_di_clock_source()
1423 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1426 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1427 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK in select_ldb_di_clock_source()
1429 reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) in select_ldb_di_clock_source()
1431 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1434 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1435 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK in select_ldb_di_clock_source()
1437 reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) in select_ldb_di_clock_source()
1439 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1442 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1443 reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL; in select_ldb_di_clock_source()
1444 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1450 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1451 reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL; in select_ldb_di_clock_source()
1452 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1458 reg = readl(&mxc_ccm->ccdr); in select_ldb_di_clock_source()
1459 reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK; in select_ldb_di_clock_source()
1460 writel(reg, &mxc_ccm->ccdr); in select_ldb_di_clock_source()
1469 u32 reg; in enable_eim_clk() local
1471 reg = __raw_readl(&imx_ccm->CCGR6); in enable_eim_clk()
1473 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; in enable_eim_clk()
1475 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK; in enable_eim_clk()
1476 __raw_writel(reg, &imx_ccm->CCGR6); in enable_eim_clk()