xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/armada-38x-controlcenterdc.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Device Tree file for the Guntermann & Drunck ControlCenter-Compact board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * based on the Device Tree file for Marvell Armada 388 evaluation board
7*4882a593Smuzhiyun * (DB-88F6820), which is
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (C) 2014 Marvell
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * SPDX-License-Identifier:     GPL-2.0+
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun/dts-v1/;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun#include "armada-388.dtsi"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun&gpio0 {
21*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
22*4882a593Smuzhiyun};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun&gpio1 {
25*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
26*4882a593Smuzhiyun};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun&uart0 {
29*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
30*4882a593Smuzhiyun};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun&uart1 {
33*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
34*4882a593Smuzhiyun};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun/ {
37*4882a593Smuzhiyun	model = "Controlcenter Digital Compact";
38*4882a593Smuzhiyun	compatible = "marvell,a385-db", "marvell,armada388",
39*4882a593Smuzhiyun		"marvell,armada385", "marvell,armada380";
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	chosen {
42*4882a593Smuzhiyun		bootargs = "console=ttyS1,115200 earlyprintk";
43*4882a593Smuzhiyun		stdout-path = "/soc/internal-regs/serial@12100";
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	aliases {
47*4882a593Smuzhiyun		ethernet0 = &eth0;
48*4882a593Smuzhiyun		ethernet2 = &eth2;
49*4882a593Smuzhiyun		mdio-gpio0 = &MDIO0;
50*4882a593Smuzhiyun		mdio-gpio1 = &MDIO1;
51*4882a593Smuzhiyun		mdio-gpio2 = &MDIO2;
52*4882a593Smuzhiyun		spi0 = &spi0;
53*4882a593Smuzhiyun		spi1 = &spi1;
54*4882a593Smuzhiyun		i2c0 = &I2C0;
55*4882a593Smuzhiyun		i2c1 = &I2C1;
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	memory {
59*4882a593Smuzhiyun		device_type = "memory";
60*4882a593Smuzhiyun		reg = <0x00000000 0x10000000>; /* 256 MB */
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	clocks {
64*4882a593Smuzhiyun		sc16isclk: sc16isclk {
65*4882a593Smuzhiyun			compatible = "fixed-clock";
66*4882a593Smuzhiyun			#clock-cells = <0>;
67*4882a593Smuzhiyun			clock-frequency = <11059200>;
68*4882a593Smuzhiyun		};
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	soc {
72*4882a593Smuzhiyun		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
73*4882a593Smuzhiyun			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun		internal-regs {
76*4882a593Smuzhiyun			spi0: spi@10600 {
77*4882a593Smuzhiyun				status = "okay";
78*4882a593Smuzhiyun				sc16is741: sc16is741@0 {
79*4882a593Smuzhiyun					compatible = "nxp,sc16is741";
80*4882a593Smuzhiyun					reg = <0>;
81*4882a593Smuzhiyun					clocks = <&sc16isclk>;
82*4882a593Smuzhiyun					spi-max-frequency = <4000000>;
83*4882a593Smuzhiyun					interrupt-parent = <&gpio0>;
84*4882a593Smuzhiyun					interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
85*4882a593Smuzhiyun					gpio-controller;
86*4882a593Smuzhiyun					#gpio-cells = <2>;
87*4882a593Smuzhiyun				};
88*4882a593Smuzhiyun			};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun			spi1: spi@10680 {
91*4882a593Smuzhiyun				status = "okay";
92*4882a593Smuzhiyun				u-boot,dm-pre-reloc;
93*4882a593Smuzhiyun				spi-flash@0 {
94*4882a593Smuzhiyun					#address-cells = <1>;
95*4882a593Smuzhiyun					#size-cells = <1>;
96*4882a593Smuzhiyun					compatible = "n25q016a";
97*4882a593Smuzhiyun					reg = <0>; /* Chip select 0 */
98*4882a593Smuzhiyun					spi-max-frequency = <108000000>;
99*4882a593Smuzhiyun				};
100*4882a593Smuzhiyun				spi-flash@1 {
101*4882a593Smuzhiyun					#address-cells = <1>;
102*4882a593Smuzhiyun					#size-cells = <1>;
103*4882a593Smuzhiyun					compatible = "n25q128a11";
104*4882a593Smuzhiyun					reg = <1>; /* Chip select 1 */
105*4882a593Smuzhiyun					spi-max-frequency = <108000000>;
106*4882a593Smuzhiyun					u-boot,dm-pre-reloc;
107*4882a593Smuzhiyun				};
108*4882a593Smuzhiyun			};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun			I2C0: i2c@11000 {
111*4882a593Smuzhiyun				status = "okay";
112*4882a593Smuzhiyun				clock-frequency = <1000000>;
113*4882a593Smuzhiyun				u-boot,dm-pre-reloc;
114*4882a593Smuzhiyun				PCA21: pca9698@21 {
115*4882a593Smuzhiyun					compatible = "nxp,pca9698";
116*4882a593Smuzhiyun					reg = <0x21>;
117*4882a593Smuzhiyun					#gpio-cells = <2>;
118*4882a593Smuzhiyun					gpio-controller;
119*4882a593Smuzhiyun				};
120*4882a593Smuzhiyun				PCA22: pca9698@22 {
121*4882a593Smuzhiyun					compatible = "nxp,pca9698";
122*4882a593Smuzhiyun					u-boot,dm-pre-reloc;
123*4882a593Smuzhiyun					reg = <0x22>;
124*4882a593Smuzhiyun					#gpio-cells = <2>;
125*4882a593Smuzhiyun					gpio-controller;
126*4882a593Smuzhiyun				};
127*4882a593Smuzhiyun				PCA23: pca9698@23 {
128*4882a593Smuzhiyun					compatible = "nxp,pca9698";
129*4882a593Smuzhiyun					reg = <0x23>;
130*4882a593Smuzhiyun					#gpio-cells = <2>;
131*4882a593Smuzhiyun					gpio-controller;
132*4882a593Smuzhiyun				};
133*4882a593Smuzhiyun				PCA24: pca9698@24 {
134*4882a593Smuzhiyun					compatible = "nxp,pca9698";
135*4882a593Smuzhiyun					reg = <0x24>;
136*4882a593Smuzhiyun					#gpio-cells = <2>;
137*4882a593Smuzhiyun					gpio-controller;
138*4882a593Smuzhiyun				};
139*4882a593Smuzhiyun				PCA25: pca9698@25 {
140*4882a593Smuzhiyun					compatible = "nxp,pca9698";
141*4882a593Smuzhiyun					reg = <0x25>;
142*4882a593Smuzhiyun					#gpio-cells = <2>;
143*4882a593Smuzhiyun					gpio-controller;
144*4882a593Smuzhiyun				};
145*4882a593Smuzhiyun				PCA26: pca9698@26 {
146*4882a593Smuzhiyun					compatible = "nxp,pca9698";
147*4882a593Smuzhiyun					reg = <0x26>;
148*4882a593Smuzhiyun					#gpio-cells = <2>;
149*4882a593Smuzhiyun					gpio-controller;
150*4882a593Smuzhiyun				};
151*4882a593Smuzhiyun			};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun			I2C1: i2c@11100 {
154*4882a593Smuzhiyun				status = "okay";
155*4882a593Smuzhiyun				clock-frequency = <400000>;
156*4882a593Smuzhiyun				at97sc3205t@29 {
157*4882a593Smuzhiyun					compatible = "atmel,at97sc3204t";
158*4882a593Smuzhiyun					reg = <0x29>;
159*4882a593Smuzhiyun					u-boot,i2c-offset-len = <0>;
160*4882a593Smuzhiyun				};
161*4882a593Smuzhiyun				emc2305@2d {
162*4882a593Smuzhiyun					compatible = "smsc,emc2305";
163*4882a593Smuzhiyun					#address-cells = <1>;
164*4882a593Smuzhiyun					#size-cells = <0>;
165*4882a593Smuzhiyun					reg = <0x2d>;
166*4882a593Smuzhiyun					fan@0 {
167*4882a593Smuzhiyun						reg = <0>;
168*4882a593Smuzhiyun					};
169*4882a593Smuzhiyun					fan@1 {
170*4882a593Smuzhiyun						reg = <1>;
171*4882a593Smuzhiyun					};
172*4882a593Smuzhiyun					fan@2 {
173*4882a593Smuzhiyun						reg = <2>;
174*4882a593Smuzhiyun					};
175*4882a593Smuzhiyun					fan@3 {
176*4882a593Smuzhiyun						reg = <3>;
177*4882a593Smuzhiyun					};
178*4882a593Smuzhiyun					fan@4 {
179*4882a593Smuzhiyun						reg = <4>;
180*4882a593Smuzhiyun					};
181*4882a593Smuzhiyun				};
182*4882a593Smuzhiyun				lm77@48 {
183*4882a593Smuzhiyun					compatible = "national,lm77";
184*4882a593Smuzhiyun					reg = <0x48>;
185*4882a593Smuzhiyun				};
186*4882a593Smuzhiyun				ads1015@49 {
187*4882a593Smuzhiyun					compatible = "ti,ads1015";
188*4882a593Smuzhiyun					reg = <0x49>;
189*4882a593Smuzhiyun				};
190*4882a593Smuzhiyun				lm77@4a {
191*4882a593Smuzhiyun					compatible = "national,lm77";
192*4882a593Smuzhiyun					reg = <0x4a>;
193*4882a593Smuzhiyun				};
194*4882a593Smuzhiyun				ads1015@4b {
195*4882a593Smuzhiyun					compatible = "ti,ads1015";
196*4882a593Smuzhiyun					reg = <0x4b>;
197*4882a593Smuzhiyun				};
198*4882a593Smuzhiyun				emc2305@4c {
199*4882a593Smuzhiyun					compatible = "smsc,emc2305";
200*4882a593Smuzhiyun					#address-cells = <1>;
201*4882a593Smuzhiyun					#size-cells = <0>;
202*4882a593Smuzhiyun					reg = <0x4c>;
203*4882a593Smuzhiyun					fan@0 {
204*4882a593Smuzhiyun						reg = <0>;
205*4882a593Smuzhiyun					};
206*4882a593Smuzhiyun					fan@1 {
207*4882a593Smuzhiyun						reg = <1>;
208*4882a593Smuzhiyun					};
209*4882a593Smuzhiyun					fan@2 {
210*4882a593Smuzhiyun						reg = <2>;
211*4882a593Smuzhiyun					};
212*4882a593Smuzhiyun					fan@3 {
213*4882a593Smuzhiyun						reg = <3>;
214*4882a593Smuzhiyun					};
215*4882a593Smuzhiyun					fan@4 {
216*4882a593Smuzhiyun						reg = <4>;
217*4882a593Smuzhiyun					};
218*4882a593Smuzhiyun				};
219*4882a593Smuzhiyun				at24c512@54 {
220*4882a593Smuzhiyun					compatible = "atmel,24c512";
221*4882a593Smuzhiyun					reg = <0x54>;
222*4882a593Smuzhiyun					u-boot,i2c-offset-len = <2>;
223*4882a593Smuzhiyun				};
224*4882a593Smuzhiyun				ds1339@68 {
225*4882a593Smuzhiyun					compatible = "dallas,ds1339";
226*4882a593Smuzhiyun					reg = <0x68>;
227*4882a593Smuzhiyun				};
228*4882a593Smuzhiyun			};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun			serial@12000 {
231*4882a593Smuzhiyun				status = "okay";
232*4882a593Smuzhiyun			};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun			serial@12100 {
235*4882a593Smuzhiyun				status = "okay";
236*4882a593Smuzhiyun			};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun			ethernet@34000 {
239*4882a593Smuzhiyun				status = "okay";
240*4882a593Smuzhiyun				phy = <&phy1>;
241*4882a593Smuzhiyun				phy-mode = "sgmii";
242*4882a593Smuzhiyun			};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun			usb@58000 {
245*4882a593Smuzhiyun				status = "ok";
246*4882a593Smuzhiyun			};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun			ethernet@70000 {
249*4882a593Smuzhiyun				status = "okay";
250*4882a593Smuzhiyun				phy = <&phy0>;
251*4882a593Smuzhiyun				phy-mode = "sgmii";
252*4882a593Smuzhiyun			};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun			mdio@72004 {
255*4882a593Smuzhiyun				phy0: ethernet-phy@0 {
256*4882a593Smuzhiyun					reg = <1>;
257*4882a593Smuzhiyun				};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun				phy1: ethernet-phy@1 {
260*4882a593Smuzhiyun					reg = <0>;
261*4882a593Smuzhiyun				};
262*4882a593Smuzhiyun			};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun			sata@a8000 {
265*4882a593Smuzhiyun				status = "okay";
266*4882a593Smuzhiyun			};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun			sdhci@d8000 {
269*4882a593Smuzhiyun				broken-cd;
270*4882a593Smuzhiyun				wp-inverted;
271*4882a593Smuzhiyun				bus-width = <4>;
272*4882a593Smuzhiyun				status = "okay";
273*4882a593Smuzhiyun				no-1-8-v;
274*4882a593Smuzhiyun			};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun			usb3@f0000 {
277*4882a593Smuzhiyun				status = "okay";
278*4882a593Smuzhiyun			};
279*4882a593Smuzhiyun		};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun		pcie-controller {
282*4882a593Smuzhiyun			status = "okay";
283*4882a593Smuzhiyun			/*
284*4882a593Smuzhiyun			 * The two PCIe units are accessible through
285*4882a593Smuzhiyun			 * standard PCIe slots on the board.
286*4882a593Smuzhiyun			 */
287*4882a593Smuzhiyun			pcie@3,0 {
288*4882a593Smuzhiyun				/* Port 0, Lane 0 */
289*4882a593Smuzhiyun				status = "okay";
290*4882a593Smuzhiyun			};
291*4882a593Smuzhiyun		};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun		MDIO0: mdio0 {
294*4882a593Smuzhiyun			compatible = "virtual,mdio-gpio";
295*4882a593Smuzhiyun			#address-cells = <1>;
296*4882a593Smuzhiyun			#size-cells = <0>;
297*4882a593Smuzhiyun			gpios = < /*MDC*/ &gpio0 13 0
298*4882a593Smuzhiyun				  /*MDIO*/ &gpio0 14 0>;
299*4882a593Smuzhiyun			mv88e1240@0 {
300*4882a593Smuzhiyun				reg = <0x0>;
301*4882a593Smuzhiyun			};
302*4882a593Smuzhiyun			mv88e1240@1 {
303*4882a593Smuzhiyun				reg = <0x1>;
304*4882a593Smuzhiyun			};
305*4882a593Smuzhiyun			mv88e1240@2 {
306*4882a593Smuzhiyun				reg = <0x2>;
307*4882a593Smuzhiyun			};
308*4882a593Smuzhiyun			mv88e1240@3 {
309*4882a593Smuzhiyun				reg = <0x3>;
310*4882a593Smuzhiyun			};
311*4882a593Smuzhiyun			mv88e1240@4 {
312*4882a593Smuzhiyun				reg = <0x4>;
313*4882a593Smuzhiyun			};
314*4882a593Smuzhiyun			mv88e1240@5 {
315*4882a593Smuzhiyun				reg = <0x5>;
316*4882a593Smuzhiyun			};
317*4882a593Smuzhiyun			mv88e1240@6 {
318*4882a593Smuzhiyun				reg = <0x6>;
319*4882a593Smuzhiyun			};
320*4882a593Smuzhiyun			mv88e1240@7 {
321*4882a593Smuzhiyun				reg = <0x7>;
322*4882a593Smuzhiyun			};
323*4882a593Smuzhiyun			mv88e1240@8 {
324*4882a593Smuzhiyun				reg = <0x8>;
325*4882a593Smuzhiyun			};
326*4882a593Smuzhiyun			mv88e1240@9 {
327*4882a593Smuzhiyun				reg = <0x9>;
328*4882a593Smuzhiyun			};
329*4882a593Smuzhiyun			mv88e1240@a {
330*4882a593Smuzhiyun				reg = <0xa>;
331*4882a593Smuzhiyun			};
332*4882a593Smuzhiyun			mv88e1240@b {
333*4882a593Smuzhiyun				reg = <0xb>;
334*4882a593Smuzhiyun			};
335*4882a593Smuzhiyun			mv88e1240@c {
336*4882a593Smuzhiyun				reg = <0xc>;
337*4882a593Smuzhiyun			};
338*4882a593Smuzhiyun			mv88e1240@d {
339*4882a593Smuzhiyun				reg = <0xd>;
340*4882a593Smuzhiyun			};
341*4882a593Smuzhiyun			mv88e1240@e {
342*4882a593Smuzhiyun				reg = <0xe>;
343*4882a593Smuzhiyun			};
344*4882a593Smuzhiyun			mv88e1240@f {
345*4882a593Smuzhiyun				reg = <0xf>;
346*4882a593Smuzhiyun			};
347*4882a593Smuzhiyun			mv88e1240@10 {
348*4882a593Smuzhiyun				reg = <0x10>;
349*4882a593Smuzhiyun			};
350*4882a593Smuzhiyun			mv88e1240@11 {
351*4882a593Smuzhiyun				reg = <0x11>;
352*4882a593Smuzhiyun			};
353*4882a593Smuzhiyun			mv88e1240@12 {
354*4882a593Smuzhiyun				reg = <0x12>;
355*4882a593Smuzhiyun			};
356*4882a593Smuzhiyun			mv88e1240@13 {
357*4882a593Smuzhiyun				reg = <0x13>;
358*4882a593Smuzhiyun			};
359*4882a593Smuzhiyun			mv88e1240@14 {
360*4882a593Smuzhiyun				reg = <0x14>;
361*4882a593Smuzhiyun			};
362*4882a593Smuzhiyun			mv88e1240@15 {
363*4882a593Smuzhiyun				reg = <0x15>;
364*4882a593Smuzhiyun			};
365*4882a593Smuzhiyun			mv88e1240@16 {
366*4882a593Smuzhiyun				reg = <0x16>;
367*4882a593Smuzhiyun			};
368*4882a593Smuzhiyun			mv88e1240@17 {
369*4882a593Smuzhiyun				reg = <0x17>;
370*4882a593Smuzhiyun			};
371*4882a593Smuzhiyun			mv88e1240@18 {
372*4882a593Smuzhiyun				reg = <0x18>;
373*4882a593Smuzhiyun			};
374*4882a593Smuzhiyun			mv88e1240@19 {
375*4882a593Smuzhiyun				reg = <0x19>;
376*4882a593Smuzhiyun			};
377*4882a593Smuzhiyun			mv88e1240@1a {
378*4882a593Smuzhiyun				reg = <0x1a>;
379*4882a593Smuzhiyun			};
380*4882a593Smuzhiyun			mv88e1240@1b {
381*4882a593Smuzhiyun				reg = <0x1b>;
382*4882a593Smuzhiyun			};
383*4882a593Smuzhiyun			mv88e1240@1c {
384*4882a593Smuzhiyun				reg = <0x1c>;
385*4882a593Smuzhiyun			};
386*4882a593Smuzhiyun			mv88e1240@1d {
387*4882a593Smuzhiyun				reg = <0x1d>;
388*4882a593Smuzhiyun			};
389*4882a593Smuzhiyun			mv88e1240@1e {
390*4882a593Smuzhiyun				reg = <0x1e>;
391*4882a593Smuzhiyun			};
392*4882a593Smuzhiyun			mv88e1240@1f {
393*4882a593Smuzhiyun				reg = <0x1f>;
394*4882a593Smuzhiyun			};
395*4882a593Smuzhiyun		};
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun		MDIO1: mdio1 {
398*4882a593Smuzhiyun			compatible = "virtual,mdio-gpio";
399*4882a593Smuzhiyun			#address-cells = <1>;
400*4882a593Smuzhiyun			#size-cells = <0>;
401*4882a593Smuzhiyun			gpios = < /*MDC*/ &gpio0 25 0
402*4882a593Smuzhiyun				  /*MDIO*/ &gpio1 13 0>;
403*4882a593Smuzhiyun			mv88e1240@0 {
404*4882a593Smuzhiyun				reg = <0x0>;
405*4882a593Smuzhiyun			};
406*4882a593Smuzhiyun			mv88e1240@1 {
407*4882a593Smuzhiyun				reg = <0x1>;
408*4882a593Smuzhiyun			};
409*4882a593Smuzhiyun			mv88e1240@2 {
410*4882a593Smuzhiyun				reg = <0x2>;
411*4882a593Smuzhiyun			};
412*4882a593Smuzhiyun			mv88e1240@3 {
413*4882a593Smuzhiyun				reg = <0x3>;
414*4882a593Smuzhiyun			};
415*4882a593Smuzhiyun			mv88e1240@4 {
416*4882a593Smuzhiyun				reg = <0x4>;
417*4882a593Smuzhiyun			};
418*4882a593Smuzhiyun			mv88e1240@5 {
419*4882a593Smuzhiyun				reg = <0x5>;
420*4882a593Smuzhiyun			};
421*4882a593Smuzhiyun			mv88e1240@6 {
422*4882a593Smuzhiyun				reg = <0x6>;
423*4882a593Smuzhiyun			};
424*4882a593Smuzhiyun			mv88e1240@7 {
425*4882a593Smuzhiyun				reg = <0x7>;
426*4882a593Smuzhiyun			};
427*4882a593Smuzhiyun			mv88e1240@8 {
428*4882a593Smuzhiyun				reg = <0x8>;
429*4882a593Smuzhiyun			};
430*4882a593Smuzhiyun			mv88e1240@9 {
431*4882a593Smuzhiyun				reg = <0x9>;
432*4882a593Smuzhiyun			};
433*4882a593Smuzhiyun			mv88e1240@a {
434*4882a593Smuzhiyun				reg = <0xa>;
435*4882a593Smuzhiyun			};
436*4882a593Smuzhiyun			mv88e1240@b {
437*4882a593Smuzhiyun				reg = <0xb>;
438*4882a593Smuzhiyun			};
439*4882a593Smuzhiyun			mv88e1240@c {
440*4882a593Smuzhiyun				reg = <0xc>;
441*4882a593Smuzhiyun			};
442*4882a593Smuzhiyun			mv88e1240@d {
443*4882a593Smuzhiyun				reg = <0xd>;
444*4882a593Smuzhiyun			};
445*4882a593Smuzhiyun			mv88e1240@e {
446*4882a593Smuzhiyun				reg = <0xe>;
447*4882a593Smuzhiyun			};
448*4882a593Smuzhiyun			mv88e1240@f {
449*4882a593Smuzhiyun				reg = <0xf>;
450*4882a593Smuzhiyun			};
451*4882a593Smuzhiyun			mv88e1240@10 {
452*4882a593Smuzhiyun				reg = <0x10>;
453*4882a593Smuzhiyun			};
454*4882a593Smuzhiyun			mv88e1240@11 {
455*4882a593Smuzhiyun				reg = <0x11>;
456*4882a593Smuzhiyun			};
457*4882a593Smuzhiyun			mv88e1240@12 {
458*4882a593Smuzhiyun				reg = <0x12>;
459*4882a593Smuzhiyun			};
460*4882a593Smuzhiyun			mv88e1240@13 {
461*4882a593Smuzhiyun				reg = <0x13>;
462*4882a593Smuzhiyun			};
463*4882a593Smuzhiyun			mv88e1240@14 {
464*4882a593Smuzhiyun				reg = <0x14>;
465*4882a593Smuzhiyun			};
466*4882a593Smuzhiyun			mv88e1240@15 {
467*4882a593Smuzhiyun				reg = <0x15>;
468*4882a593Smuzhiyun			};
469*4882a593Smuzhiyun			mv88e1240@16 {
470*4882a593Smuzhiyun				reg = <0x16>;
471*4882a593Smuzhiyun			};
472*4882a593Smuzhiyun			mv88e1240@17 {
473*4882a593Smuzhiyun				reg = <0x17>;
474*4882a593Smuzhiyun			};
475*4882a593Smuzhiyun			mv88e1240@18 {
476*4882a593Smuzhiyun				reg = <0x18>;
477*4882a593Smuzhiyun			};
478*4882a593Smuzhiyun			mv88e1240@19 {
479*4882a593Smuzhiyun				reg = <0x19>;
480*4882a593Smuzhiyun			};
481*4882a593Smuzhiyun			mv88e1240@1a {
482*4882a593Smuzhiyun				reg = <0x1a>;
483*4882a593Smuzhiyun			};
484*4882a593Smuzhiyun			mv88e1240@1b {
485*4882a593Smuzhiyun				reg = <0x1b>;
486*4882a593Smuzhiyun			};
487*4882a593Smuzhiyun			mv88e1240@1c {
488*4882a593Smuzhiyun				reg = <0x1c>;
489*4882a593Smuzhiyun			};
490*4882a593Smuzhiyun			mv88e1240@1d {
491*4882a593Smuzhiyun				reg = <0x1d>;
492*4882a593Smuzhiyun			};
493*4882a593Smuzhiyun			mv88e1240@1e {
494*4882a593Smuzhiyun				reg = <0x1e>;
495*4882a593Smuzhiyun			};
496*4882a593Smuzhiyun			mv88e1240@1f {
497*4882a593Smuzhiyun				reg = <0x1f>;
498*4882a593Smuzhiyun			};
499*4882a593Smuzhiyun		};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun		MDIO2: mdio2 {
502*4882a593Smuzhiyun			compatible = "virtual,mdio-gpio";
503*4882a593Smuzhiyun			#address-cells = <1>;
504*4882a593Smuzhiyun			#size-cells = <0>;
505*4882a593Smuzhiyun			gpios = < /*MDC*/ &gpio1 14 0
506*4882a593Smuzhiyun				  /*MDIO*/ &gpio0 24 0>;
507*4882a593Smuzhiyun			mv88e1240@0 {
508*4882a593Smuzhiyun				reg = <0x0>;
509*4882a593Smuzhiyun			};
510*4882a593Smuzhiyun			mv88e1240@1 {
511*4882a593Smuzhiyun				reg = <0x1>;
512*4882a593Smuzhiyun			};
513*4882a593Smuzhiyun			mv88e1240@2 {
514*4882a593Smuzhiyun				reg = <0x2>;
515*4882a593Smuzhiyun			};
516*4882a593Smuzhiyun			mv88e1240@3 {
517*4882a593Smuzhiyun				reg = <0x3>;
518*4882a593Smuzhiyun			};
519*4882a593Smuzhiyun			mv88e1240@4 {
520*4882a593Smuzhiyun				reg = <0x4>;
521*4882a593Smuzhiyun			};
522*4882a593Smuzhiyun			mv88e1240@5 {
523*4882a593Smuzhiyun				reg = <0x5>;
524*4882a593Smuzhiyun			};
525*4882a593Smuzhiyun			mv88e1240@6 {
526*4882a593Smuzhiyun				reg = <0x6>;
527*4882a593Smuzhiyun			};
528*4882a593Smuzhiyun			mv88e1240@7 {
529*4882a593Smuzhiyun				reg = <0x7>;
530*4882a593Smuzhiyun			};
531*4882a593Smuzhiyun			mv88e1240@8 {
532*4882a593Smuzhiyun				reg = <0x8>;
533*4882a593Smuzhiyun			};
534*4882a593Smuzhiyun			mv88e1240@9 {
535*4882a593Smuzhiyun				reg = <0x9>;
536*4882a593Smuzhiyun			};
537*4882a593Smuzhiyun			mv88e1240@a {
538*4882a593Smuzhiyun				reg = <0xa>;
539*4882a593Smuzhiyun			};
540*4882a593Smuzhiyun			mv88e1240@b {
541*4882a593Smuzhiyun				reg = <0xb>;
542*4882a593Smuzhiyun			};
543*4882a593Smuzhiyun			mv88e1240@c {
544*4882a593Smuzhiyun				reg = <0xc>;
545*4882a593Smuzhiyun			};
546*4882a593Smuzhiyun			mv88e1240@d {
547*4882a593Smuzhiyun				reg = <0xd>;
548*4882a593Smuzhiyun			};
549*4882a593Smuzhiyun			mv88e1240@e {
550*4882a593Smuzhiyun				reg = <0xe>;
551*4882a593Smuzhiyun			};
552*4882a593Smuzhiyun			mv88e1240@f {
553*4882a593Smuzhiyun				reg = <0xf>;
554*4882a593Smuzhiyun			};
555*4882a593Smuzhiyun			mv88e1240@10 {
556*4882a593Smuzhiyun				reg = <0x10>;
557*4882a593Smuzhiyun			};
558*4882a593Smuzhiyun			mv88e1240@11 {
559*4882a593Smuzhiyun				reg = <0x11>;
560*4882a593Smuzhiyun			};
561*4882a593Smuzhiyun			mv88e1240@12 {
562*4882a593Smuzhiyun				reg = <0x12>;
563*4882a593Smuzhiyun			};
564*4882a593Smuzhiyun			mv88e1240@13 {
565*4882a593Smuzhiyun				reg = <0x13>;
566*4882a593Smuzhiyun			};
567*4882a593Smuzhiyun			mv88e1240@14 {
568*4882a593Smuzhiyun				reg = <0x14>;
569*4882a593Smuzhiyun			};
570*4882a593Smuzhiyun			mv88e1240@15 {
571*4882a593Smuzhiyun				reg = <0x15>;
572*4882a593Smuzhiyun			};
573*4882a593Smuzhiyun		};
574*4882a593Smuzhiyun	};
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun	leds {
577*4882a593Smuzhiyun		compatible = "gpio-leds";
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun		finder_led {
580*4882a593Smuzhiyun			label = "finder-led";
581*4882a593Smuzhiyun			gpios = <&PCA22 25 0>;
582*4882a593Smuzhiyun		};
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun		status_led {
585*4882a593Smuzhiyun			label = "status-led";
586*4882a593Smuzhiyun			gpios = <&gpio0 29 0>;
587*4882a593Smuzhiyun		};
588*4882a593Smuzhiyun	};
589*4882a593Smuzhiyun};
590