1*4882a593Smuzhiyun /* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 1996-1997 David J. McKay 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 6*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 7*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 8*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 10*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 13*4882a593Smuzhiyun * all copies or substantial portions of the Software. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*4882a593Smuzhiyun * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 19*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 20*4882a593Smuzhiyun * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21*4882a593Smuzhiyun * SOFTWARE. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifndef __NVREG_H_ 27*4882a593Smuzhiyun #define __NVREG_H_ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Little macro to construct bitmask for contiguous ranges of bits */ 30*4882a593Smuzhiyun #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b)) 31*4882a593Smuzhiyun #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Macro to set specific bitfields (mask has to be a macro x:y) ! */ 34*4882a593Smuzhiyun #define SetBF(mask,value) ((value) << (0?mask)) 35*4882a593Smuzhiyun #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ 38*4882a593Smuzhiyun | SetBF(mask,value))) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define DEVICE_BASE(device) (0?NV##_##device) 41*4882a593Smuzhiyun #define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* This is where we will have to have conditional compilation */ 44*4882a593Smuzhiyun #define DEVICE_ACCESS(device,reg) \ 45*4882a593Smuzhiyun nvCONTROL[(NV_##device##_##reg)/4] 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) 48*4882a593Smuzhiyun #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) 49*4882a593Smuzhiyun #define DEVICE_PRINT(device,reg) \ 50*4882a593Smuzhiyun ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) 51*4882a593Smuzhiyun #define DEVICE_DEF(device,mask,value) \ 52*4882a593Smuzhiyun SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value) 53*4882a593Smuzhiyun #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) 54*4882a593Smuzhiyun #define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) 57*4882a593Smuzhiyun #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) 58*4882a593Smuzhiyun #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) 59*4882a593Smuzhiyun #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) 60*4882a593Smuzhiyun #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) 61*4882a593Smuzhiyun #define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) 64*4882a593Smuzhiyun #define PFB_Read(reg) DEVICE_READ(PFB,reg) 65*4882a593Smuzhiyun #define PFB_Print(reg) DEVICE_PRINT(PFB,reg) 66*4882a593Smuzhiyun #define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value) 67*4882a593Smuzhiyun #define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value) 68*4882a593Smuzhiyun #define PFB_Mask(mask) DEVICE_MASK(PFB,mask) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value) 71*4882a593Smuzhiyun #define PRM_Read(reg) DEVICE_READ(PRM,reg) 72*4882a593Smuzhiyun #define PRM_Print(reg) DEVICE_PRINT(PRM,reg) 73*4882a593Smuzhiyun #define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value) 74*4882a593Smuzhiyun #define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value) 75*4882a593Smuzhiyun #define PRM_Mask(mask) DEVICE_MASK(PRM,mask) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value) 78*4882a593Smuzhiyun #define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg) 79*4882a593Smuzhiyun #define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg) 80*4882a593Smuzhiyun #define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value) 81*4882a593Smuzhiyun #define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value) 82*4882a593Smuzhiyun #define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value) 85*4882a593Smuzhiyun #define PDMA_Read(reg) DEVICE_READ(PDMA,reg) 86*4882a593Smuzhiyun #define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg) 87*4882a593Smuzhiyun #define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value) 88*4882a593Smuzhiyun #define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value) 89*4882a593Smuzhiyun #define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value) 92*4882a593Smuzhiyun #define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg) 93*4882a593Smuzhiyun #define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg) 94*4882a593Smuzhiyun #define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value) 95*4882a593Smuzhiyun #define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value) 96*4882a593Smuzhiyun #define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value) 99*4882a593Smuzhiyun #define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg) 100*4882a593Smuzhiyun #define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg) 101*4882a593Smuzhiyun #define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value) 102*4882a593Smuzhiyun #define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value) 103*4882a593Smuzhiyun #define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value) 106*4882a593Smuzhiyun #define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg) 107*4882a593Smuzhiyun #define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg) 108*4882a593Smuzhiyun #define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value) 109*4882a593Smuzhiyun #define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value) 110*4882a593Smuzhiyun #define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value) 113*4882a593Smuzhiyun #define PRAM_Read(reg) DEVICE_READ(PRAM,reg) 114*4882a593Smuzhiyun #define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg) 115*4882a593Smuzhiyun #define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value) 116*4882a593Smuzhiyun #define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value) 117*4882a593Smuzhiyun #define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value) 120*4882a593Smuzhiyun #define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg) 121*4882a593Smuzhiyun #define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg) 122*4882a593Smuzhiyun #define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value) 123*4882a593Smuzhiyun #define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value) 124*4882a593Smuzhiyun #define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) 127*4882a593Smuzhiyun #define PMC_Read(reg) DEVICE_READ(PMC,reg) 128*4882a593Smuzhiyun #define PMC_Print(reg) DEVICE_PRINT(PMC,reg) 129*4882a593Smuzhiyun #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) 130*4882a593Smuzhiyun #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) 131*4882a593Smuzhiyun #define PMC_Mask(mask) DEVICE_MASK(PMC,mask) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) 134*4882a593Smuzhiyun #define PMC_Read(reg) DEVICE_READ(PMC,reg) 135*4882a593Smuzhiyun #define PMC_Print(reg) DEVICE_PRINT(PMC,reg) 136*4882a593Smuzhiyun #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) 137*4882a593Smuzhiyun #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) 138*4882a593Smuzhiyun #define PMC_Mask(mask) DEVICE_MASK(PMC,mask) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value) 142*4882a593Smuzhiyun #define PBUS_Read(reg) DEVICE_READ(PBUS,reg) 143*4882a593Smuzhiyun #define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg) 144*4882a593Smuzhiyun #define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value) 145*4882a593Smuzhiyun #define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value) 146*4882a593Smuzhiyun #define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value) 150*4882a593Smuzhiyun #define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg) 151*4882a593Smuzhiyun #define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg) 152*4882a593Smuzhiyun #define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value) 153*4882a593Smuzhiyun #define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value) 154*4882a593Smuzhiyun #define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define PDAC_ReadExt(reg) \ 158*4882a593Smuzhiyun ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ 159*4882a593Smuzhiyun (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ 160*4882a593Smuzhiyun (PDAC_Read(INDEX_DATA))) 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define PDAC_WriteExt(reg,value)\ 163*4882a593Smuzhiyun ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ 164*4882a593Smuzhiyun (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ 165*4882a593Smuzhiyun (PDAC_Write(INDEX_DATA,(value)))) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5) 168*4882a593Smuzhiyun #define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5)) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value) 171*4882a593Smuzhiyun #define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index) 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value) 174*4882a593Smuzhiyun #define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value) 175*4882a593Smuzhiyun #define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask) 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value) 178*4882a593Smuzhiyun #define SR_Read(index) (outb(0x3c4,index),inb(0x3c5)) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun extern volatile unsigned *nvCONTROL; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun NVChipType GetChipType(void); 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #endif 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun 189