1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* Please keep them sorted based on the CRn register */ 8 .macro read_midr reg 9 mrc p15, 0, \reg, c0, c0, 0 10 .endm 11 12 .macro read_ctr reg 13 mrc p15, 0, \reg, c0, c0, 1 14 .endm 15 16 .macro read_mpidr reg 17 mrc p15, 0, \reg, c0, c0, 5 18 .endm 19 20 .macro read_sctlr reg 21 mrc p15, 0, \reg, c1, c0, 0 22 .endm 23 24 .macro write_sctlr reg 25 mcr p15, 0, \reg, c1, c0, 0 26 .endm 27 28 .macro write_actlr reg 29 mcr p15, 0, \reg, c1, c0, 1 30 .endm 31 32 .macro read_actlr reg 33 mrc p15, 0, \reg, c1, c0, 1 34 .endm 35 36 .macro write_cpacr reg 37 mcr p15, 0, \reg, c1, c0, 2 38 .endm 39 40 .macro read_cpacr reg 41 mrc p15, 0, \reg, c1, c0, 2 42 .endm 43 44 .macro read_scr reg 45 mrc p15, 0, \reg, c1, c1, 0 46 .endm 47 48 .macro write_scr reg 49 mcr p15, 0, \reg, c1, c1, 0 50 .endm 51 52 .macro write_nsacr reg 53 mcr p15, 0, \reg, c1, c1, 2 54 .endm 55 56 .macro read_nsacr reg 57 mrc p15, 0, \reg, c1, c1, 2 58 .endm 59 60 .macro write_ttbr0 reg 61 mcr p15, 0, \reg, c2, c0, 0 62 .endm 63 64 .macro read_ttbr0 reg 65 mrc p15, 0, \reg, c2, c0, 0 66 .endm 67 68 .macro write_ttbr1 reg 69 mcr p15, 0, \reg, c2, c0, 1 70 .endm 71 72 .macro read_ttbr1 reg 73 mrc p15, 0, \reg, c2, c0, 1 74 .endm 75 76 .macro write_ttbcr reg 77 mcr p15, 0, \reg, c2, c0, 2 78 .endm 79 80 .macro read_ttbcr reg 81 mrc p15, 0, \reg, c2, c0, 2 82 .endm 83 84 85 .macro write_dacr reg 86 mcr p15, 0, \reg, c3, c0, 0 87 .endm 88 89 .macro read_dacr reg 90 mrc p15, 0, \reg, c3, c0, 0 91 .endm 92 93 .macro read_dfsr reg 94 mrc p15, 0, \reg, c5, c0, 0 95 .endm 96 97 .macro write_icialluis 98 /* 99 * Invalidate all instruction caches to PoU, Inner Shareable 100 * (register ignored) 101 */ 102 mcr p15, 0, r0, c7, c1, 0 103 .endm 104 105 .macro write_bpiallis 106 /* 107 * Invalidate entire branch predictor array, Inner Shareable 108 * (register ignored) 109 */ 110 mcr p15, 0, r0, c7, c1, 6 111 .endm 112 113 .macro write_iciallu 114 /* Invalidate all instruction caches to PoU (register ignored) */ 115 mcr p15, 0, r0, c7, c5, 0 116 .endm 117 118 .macro write_icimvau reg 119 /* Instruction cache invalidate by MVA */ 120 mcr p15, 0, \reg, c7, c5, 1 121 .endm 122 123 .macro write_bpiall 124 /* Invalidate entire branch predictor array (register ignored) */ 125 mcr p15, 0, r0, c7, c5, 6 126 .endm 127 128 .macro write_dcimvac reg 129 /* Data cache invalidate by MVA */ 130 mcr p15, 0, \reg, c7, c6, 1 131 .endm 132 133 .macro write_dcisw reg 134 /* Data cache invalidate by set/way */ 135 mcr p15, 0, \reg, c7, c6, 2 136 .endm 137 138 .macro write_dccmvac reg 139 /* Data cache clean by MVA */ 140 mcr p15, 0, \reg, c7, c10, 1 141 .endm 142 143 .macro write_dccsw reg 144 /* Data cache clean by set/way */ 145 mcr p15, 0, \reg, c7, c10, 2 146 .endm 147 148 .macro write_dccimvac reg 149 /* Data cache invalidate by MVA */ 150 mcr p15, 0, \reg, c7, c14, 1 151 .endm 152 153 .macro write_dccisw reg 154 /* Data cache clean and invalidate by set/way */ 155 mcr p15, 0, \reg, c7, c14, 2 156 .endm 157 158 .macro write_tlbiall 159 /* Invalidate entire unified TLB (register ignored) */ 160 mcr p15, 0, r0, c8, c7, 0 161 .endm 162 163 .macro write_tlbiallis 164 /* Invalidate entire unified TLB Inner Sharable (register ignored) */ 165 mcr p15, 0, r0, c8, c3, 0 166 .endm 167 168 .macro write_tlbiasidis reg 169 /* Invalidate unified TLB by ASID Inner Sharable */ 170 mcr p15, 0, \reg, c8, c3, 2 171 .endm 172 173 .macro write_tlbimvaais reg 174 /* Invalidate unified TLB by MVA all ASID Inner Sharable */ 175 mcr p15, 0, \reg, c8, c3, 3 176 .endm 177 178 .macro write_prrr reg 179 mcr p15, 0, \reg, c10, c2, 0 180 .endm 181 182 .macro read_prrr reg 183 mrc p15, 0, \reg, c10, c2, 0 184 .endm 185 186 .macro write_nmrr reg 187 mcr p15, 0, \reg, c10, c2, 1 188 .endm 189 190 .macro read_nmrr reg 191 mrc p15, 0, \reg, c10, c2, 1 192 .endm 193 194 .macro read_vbar reg 195 mrc p15, 0, \reg, c12, c0, 0 196 .endm 197 198 .macro write_vbar reg 199 mcr p15, 0, \reg, c12, c0, 0 200 .endm 201 202 .macro write_mvbar reg 203 mcr p15, 0, \reg, c12, c0, 1 204 .endm 205 206 .macro read_mvbar reg 207 mrc p15, 0, \reg, c12, c0, 1 208 .endm 209 210 .macro write_fcseidr reg 211 mcr p15, 0, \reg, c13, c0, 0 212 .endm 213 214 .macro read_fcseidr reg 215 mrc p15, 0, \reg, c13, c0, 0 216 .endm 217 218 .macro write_contextidr reg 219 mcr p15, 0, \reg, c13, c0, 1 220 .endm 221 222 .macro read_contextidr reg 223 mrc p15, 0, \reg, c13, c0, 1 224 .endm 225 226 .macro write_tpidruro reg 227 mcr p15, 0, \reg, c13, c0, 3 228 .endm 229 230 .macro read_tpidruro reg 231 mrc p15, 0, \reg, c13, c0, 3 232 .endm 233 234 .macro read_clidr reg 235 /* Cache Level ID Register */ 236 mrc p15, 1, \reg, c0, c0, 1 237 .endm 238 239 .macro read_ccsidr reg 240 /* Cache Size ID Registers */ 241 mrc p15, 1, \reg, c0, c0, 0 242 .endm 243 244 .macro write_csselr reg 245 /* Cache Size Selection Register */ 246 mcr p15, 2, \reg, c0, c0, 0 247 .endm 248 249 /* Cortex A9: pcr, diag registers */ 250 .macro write_pcr reg 251 mcr p15, 0, \reg, c15, c0, 0 252 .endm 253 254 .macro read_pcr reg 255 mrc p15, 0, \reg, c15, c0, 0 256 .endm 257 258 .macro write_diag reg 259 mcr p15, 0, \reg, c15, c0, 1 260 .endm 261 262 .macro read_diag reg 263 mrc p15, 0, \reg, c15, c0, 1 264 .endm 265