| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/mediatek/ |
| H A D | mediatek,infracfg.txt | 1 Mediatek infracfg controller
4 The Mediatek infracfg controller provides various clocks and reset
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6765-infracfg", "syscon"
14 - "mediatek,mt6797-infracfg", "syscon"
15 - "mediatek,mt7622-infracfg", "syscon"
16 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
17 - "mediatek,mt7629-infracfg", "syscon"
18 - "mediatek,mt8135-infracfg", "syscon"
[all …]
|
| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8183.dtsi | 282 infracfg: syscon@10001000 { label
283 compatible = "mediatek,mt8183-infracfg", "syscon";
337 <&infracfg CLK_INFRA_PMIC_AP>;
347 clocks = <&infracfg CLK_INFRA_SCPSYS>;
367 clocks = <&infracfg CLK_INFRA_GCE>;
375 clocks = <&infracfg CLK_INFRA_AUXADC>;
386 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
396 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
406 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
416 clocks = <&infracfg CLK_INFRA_I2C6>,
[all …]
|
| H A D | mt8516.dtsi | 57 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
70 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
83 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
96 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
188 infracfg: infracfg@10001000 { label
189 compatible = "mediatek,mt8516-infracfg", "syscon";
312 <&infracfg CLK_IFR_I2C0_SEL>,
331 <&infracfg CLK_IFR_I2C1_SEL>,
350 <&infracfg CLK_IFR_I2C2_SEL>,
|
| H A D | mt7622.dtsi | 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
89 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
205 infracfg: infracfg@10000000 { label
206 compatible = "mediatek,mt7622-infracfg",
217 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
219 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
242 infracfg = <&infracfg>;
251 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
296 clocks = <&infracfg CLK_INFRA_TRNG>;
604 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
[all …]
|
| H A D | mt8173.dtsi | 166 clocks = <&infracfg CLK_INFRA_CA53SEL>,
181 clocks = <&infracfg CLK_INFRA_CA53SEL>,
196 clocks = <&infracfg CLK_INFRA_CA72SEL>,
211 clocks = <&infracfg CLK_INFRA_CA72SEL>,
362 infracfg: power-controller@10001000 { label
363 compatible = "mediatek,mt8173-infracfg", "syscon";
462 infracfg = <&infracfg>;
476 clocks = <&infracfg CLK_INFRA_CLK_13M>,
485 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
487 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
[all …]
|
| H A D | mt2712e.dtsi | 252 infracfg: syscon@10001000 { label
253 compatible = "mediatek,mt2712-infracfg", "syscon";
293 infracfg = <&infracfg>;
319 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
330 clocks = <&infracfg CLK_INFRA_M4U>;
347 clocks = <&infracfg CLK_INFRA_M4U>;
661 <&infracfg CLK_INFRA_AO_SPI0>;
|
| /OK3568_Linux_fs/kernel/drivers/soc/mediatek/ |
| H A D | mtk-infracfg.c | 32 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
39 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
42 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
44 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
63 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
70 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
72 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
74 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_clear_bus_protection()
|
| H A D | mtk-scpsys.c | 153 struct regmap *infracfg; member
286 return mtk_infracfg_set_bus_protection(scp->infracfg, in scpsys_bus_protect_enable()
298 return mtk_infracfg_clear_bus_protection(scp->infracfg, in scpsys_bus_protect_disable()
461 scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in init_scp()
463 if (IS_ERR(scp->infracfg)) { in init_scp()
465 PTR_ERR(scp->infracfg)); in init_scp()
466 return ERR_CAST(scp->infracfg); in init_scp()
|
| H A D | Makefile | 3 obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7615/ |
| H A D | soc.c | 23 dev->infracfg = syscon_regmap_lookup_by_phandle(np, "mediatek,infracfg"); in mt7622_wmac_init()
24 if (IS_ERR(dev->infracfg)) { in mt7622_wmac_init()
26 return PTR_ERR(dev->infracfg); in mt7622_wmac_init()
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpufreq/ |
| H A D | cpufreq-mediatek.txt | 63 clocks = <&infracfg CLK_INFRA_CPUSEL>,
185 clocks = <&infracfg CLK_INFRA_CA53SEL>,
197 clocks = <&infracfg CLK_INFRA_CA53SEL>,
209 clocks = <&infracfg CLK_INFRA_CA57SEL>,
221 clocks = <&infracfg CLK_INFRA_CA57SEL>,
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/mediatek/ |
| H A D | scpsys.txt | 32 - infracfg: must contain a phandle to the infracfg controller
65 infracfg = <&infracfg>;
|
| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | mt7623.dtsi | 80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
234 infracfg: syscon@10001000 { label
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
277 infracfg = <&infracfg>;
305 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
307 clocks = <&infracfg CLK_INFRA_PMICSPI>,
[all …]
|
| H A D | mt7629.dtsi | 81 infracfg: syscon@10000000 { label
82 compatible = "mediatek,mt7629-infracfg", "syscon";
102 infracfg = <&infracfg>;
134 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
475 mediatek,infracfg = <&infracfg>;
|
| H A D | mt8135.dtsi | 133 infracfg: infracfg@10001000 { label
136 compatible = "mediatek,mt8135-infracfg", "syscon";
185 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
|
| H A D | mt2701.dtsi | 132 infracfg: syscon@10001000 { label
133 compatible = "mediatek,mt2701-infracfg", "syscon";
155 infracfg = <&infracfg>;
193 clocks = <&infracfg CLK_INFRA_SMI>,
195 <&infracfg CLK_INFRA_SMI>;
223 clocks = <&infracfg CLK_INFRA_M4U>;
435 clocks = <&infracfg CLK_INFRA_AUDIO>,
|
| H A D | mt7623n.dtsi | 108 clocks = <&infracfg CLK_INFRA_M4U>;
133 clocks = <&infracfg CLK_INFRA_SMI>,
135 <&infracfg CLK_INFRA_SMI>;
264 clocks = <&infracfg CLK_INFRA_CEC>;
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/ |
| H A D | mtk-btcvsd-snd.txt | 7 - mediatek,infracfg: the phandles of INFRASYS
22 mediatek,infracfg = <&infrasys>;
|
| H A D | mtk-afe-pcm.txt | 25 clocks = <&infracfg INFRA_AUDIO>,
|
| /OK3568_Linux_fs/kernel/include/linux/soc/mediatek/ |
| H A D | infracfg.h | 38 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
40 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/wireless/ |
| H A D | mediatek,mt76.txt | 20 - mediatek,infracfg: phandle to the infrastructure bus fabric syscon node
75 mediatek,infracfg = <&infracfg>;
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/ |
| H A D | spi-slave-mt27xx.txt | 9 It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>.
28 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rng/ |
| H A D | mtk-rng.txt | 20 clocks = <&infracfg CLK_INFRA_TRNG>;
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/ |
| H A D | mtk-cir.txt | 25 clocks = <&infracfg CLK_INFRA_IRRX>;
|
| /OK3568_Linux_fs/kernel/drivers/iommu/ |
| H A D | mtk_iommu.c | 789 struct regmap *infracfg; in mtk_iommu_probe() local
819 infracfg = syscon_regmap_lookup_by_compatible(p); in mtk_iommu_probe()
821 if (IS_ERR(infracfg)) in mtk_iommu_probe()
822 return PTR_ERR(infracfg); in mtk_iommu_probe()
824 ret = regmap_read(infracfg, REG_INFRA_MISC, &val); in mtk_iommu_probe()
|