1*4882a593SmuzhiyunBinding for MTK SPI Slave controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: should be one of the following. 5*4882a593Smuzhiyun - mediatek,mt2712-spi-slave: for mt2712 platforms 6*4882a593Smuzhiyun- reg: Address and length of the register set for the device. 7*4882a593Smuzhiyun- interrupts: Should contain spi interrupt. 8*4882a593Smuzhiyun- clocks: phandles to input clocks. 9*4882a593Smuzhiyun It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>. 10*4882a593Smuzhiyun- clock-names: should be "spi" for the clock gate. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties: 13*4882a593Smuzhiyun- assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>. 14*4882a593Smuzhiyun- assigned-clock-parents: parent of mux clock. 15*4882a593Smuzhiyun It's PLL, and should be one of the following. 16*4882a593Smuzhiyun - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ. 17*4882a593Smuzhiyun It's the default one. 18*4882a593Smuzhiyun - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ. 19*4882a593Smuzhiyun - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ. 20*4882a593Smuzhiyun - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun- SoC Specific Portion: 24*4882a593Smuzhiyunspis1: spi@10013000 { 25*4882a593Smuzhiyun compatible = "mediatek,mt2712-spi-slave"; 26*4882a593Smuzhiyun reg = <0 0x10013000 0 0x100>; 27*4882a593Smuzhiyun interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; 28*4882a593Smuzhiyun clocks = <&infracfg CLK_INFRA_AO_SPI1>; 29*4882a593Smuzhiyun clock-names = "spi"; 30*4882a593Smuzhiyun assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; 31*4882a593Smuzhiyun assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 32*4882a593Smuzhiyun}; 33