1*4882a593SmuzhiyunMediatek AFE PCM controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible = "mediatek,mt8173-afe-pcm"; 5*4882a593Smuzhiyun- reg: register location and size 6*4882a593Smuzhiyun- interrupts: Should contain AFE interrupt 7*4882a593Smuzhiyun- clock-names: should have these clock names: 8*4882a593Smuzhiyun "infra_sys_audio_clk", 9*4882a593Smuzhiyun "top_pdn_audio", 10*4882a593Smuzhiyun "top_pdn_aud_intbus", 11*4882a593Smuzhiyun "bck0", 12*4882a593Smuzhiyun "bck1", 13*4882a593Smuzhiyun "i2s0_m", 14*4882a593Smuzhiyun "i2s1_m", 15*4882a593Smuzhiyun "i2s2_m", 16*4882a593Smuzhiyun "i2s3_m", 17*4882a593Smuzhiyun "i2s3_b"; 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun afe: mt8173-afe-pcm@11220000 { 22*4882a593Smuzhiyun compatible = "mediatek,mt8173-afe-pcm"; 23*4882a593Smuzhiyun reg = <0 0x11220000 0 0x1000>; 24*4882a593Smuzhiyun interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 25*4882a593Smuzhiyun clocks = <&infracfg INFRA_AUDIO>, 26*4882a593Smuzhiyun <&topckgen TOP_AUDIO_SEL>, 27*4882a593Smuzhiyun <&topckgen TOP_AUD_INTBUS_SEL>, 28*4882a593Smuzhiyun <&topckgen TOP_APLL1_DIV0>, 29*4882a593Smuzhiyun <&topckgen TOP_APLL2_DIV0>, 30*4882a593Smuzhiyun <&topckgen TOP_I2S0_M_CK_SEL>, 31*4882a593Smuzhiyun <&topckgen TOP_I2S1_M_CK_SEL>, 32*4882a593Smuzhiyun <&topckgen TOP_I2S2_M_CK_SEL>, 33*4882a593Smuzhiyun <&topckgen TOP_I2S3_M_CK_SEL>, 34*4882a593Smuzhiyun <&topckgen TOP_I2S3_B_CK_SEL>; 35*4882a593Smuzhiyun clock-names = "infra_sys_audio_clk", 36*4882a593Smuzhiyun "top_pdn_audio", 37*4882a593Smuzhiyun "top_pdn_aud_intbus", 38*4882a593Smuzhiyun "bck0", 39*4882a593Smuzhiyun "bck1", 40*4882a593Smuzhiyun "i2s0_m", 41*4882a593Smuzhiyun "i2s1_m", 42*4882a593Smuzhiyun "i2s2_m", 43*4882a593Smuzhiyun "i2s3_m", 44*4882a593Smuzhiyun "i2s3_b"; 45*4882a593Smuzhiyun }; 46