Lines Matching refs:infracfg
282 infracfg: syscon@10001000 { label
283 compatible = "mediatek,mt8183-infracfg", "syscon";
337 <&infracfg CLK_INFRA_PMIC_AP>;
347 clocks = <&infracfg CLK_INFRA_SCPSYS>;
367 clocks = <&infracfg CLK_INFRA_GCE>;
375 clocks = <&infracfg CLK_INFRA_AUXADC>;
386 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
396 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
406 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
416 clocks = <&infracfg CLK_INFRA_I2C6>,
417 <&infracfg CLK_INFRA_AP_DMA>;
430 clocks = <&infracfg CLK_INFRA_I2C0>,
431 <&infracfg CLK_INFRA_AP_DMA>;
444 clocks = <&infracfg CLK_INFRA_I2C1>,
445 <&infracfg CLK_INFRA_AP_DMA>,
446 <&infracfg CLK_INFRA_I2C1_ARBITER>;
459 clocks = <&infracfg CLK_INFRA_I2C2>,
460 <&infracfg CLK_INFRA_AP_DMA>,
461 <&infracfg CLK_INFRA_I2C2_ARBITER>;
477 <&infracfg CLK_INFRA_SPI0>;
487 clocks = <&infracfg CLK_INFRA_I2C3>,
488 <&infracfg CLK_INFRA_AP_DMA>;
504 <&infracfg CLK_INFRA_SPI1>;
514 clocks = <&infracfg CLK_INFRA_I2C4>,
515 <&infracfg CLK_INFRA_AP_DMA>;
531 <&infracfg CLK_INFRA_SPI2>;
544 <&infracfg CLK_INFRA_SPI3>;
554 clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
555 <&infracfg CLK_INFRA_AP_DMA>,
556 <&infracfg CLK_INFRA_I2C1_ARBITER>;
569 clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
570 <&infracfg CLK_INFRA_AP_DMA>,
571 <&infracfg CLK_INFRA_I2C2_ARBITER>;
584 clocks = <&infracfg CLK_INFRA_I2C5>,
585 <&infracfg CLK_INFRA_AP_DMA>,
586 <&infracfg CLK_INFRA_I2C5_ARBITER>;
599 clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
600 <&infracfg CLK_INFRA_AP_DMA>,
601 <&infracfg CLK_INFRA_I2C5_ARBITER>;
617 <&infracfg CLK_INFRA_SPI4>;
630 <&infracfg CLK_INFRA_SPI5>;
640 clocks = <&infracfg CLK_INFRA_I2C7>,
641 <&infracfg CLK_INFRA_AP_DMA>;
654 clocks = <&infracfg CLK_INFRA_I2C8>,
655 <&infracfg CLK_INFRA_AP_DMA>;
671 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
672 <&infracfg CLK_INFRA_USB>;
686 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
687 <&infracfg CLK_INFRA_USB>;
705 <&infracfg CLK_INFRA_MSDC0>,
706 <&infracfg CLK_INFRA_MSDC0_SCK>;
717 <&infracfg CLK_INFRA_MSDC1>,
718 <&infracfg CLK_INFRA_MSDC1_SCK>;