1*4882a593SmuzhiyunMediatek ALSA BT SCO CVSD/MSBC Driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible = "mediatek,mtk-btcvsd-snd"; 5*4882a593Smuzhiyun- reg: register location and size of PKV and SRAM_BANK2 6*4882a593Smuzhiyun- interrupts: should contain BTSCO interrupt 7*4882a593Smuzhiyun- mediatek,infracfg: the phandles of INFRASYS 8*4882a593Smuzhiyun- mediatek,offset: Array contains of register offset and mask 9*4882a593Smuzhiyun infra_misc_offset, 10*4882a593Smuzhiyun infra_conn_bt_cvsd_mask, 11*4882a593Smuzhiyun cvsd_mcu_read_offset, 12*4882a593Smuzhiyun cvsd_mcu_write_offset, 13*4882a593Smuzhiyun cvsd_packet_indicator_offset 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun mtk-btcvsd-snd@18000000 { 18*4882a593Smuzhiyun compatible = "mediatek,mtk-btcvsd-snd"; 19*4882a593Smuzhiyun reg=<0 0x18000000 0 0x1000>, 20*4882a593Smuzhiyun <0 0x18080000 0 0x8000>; 21*4882a593Smuzhiyun interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; 22*4882a593Smuzhiyun mediatek,infracfg = <&infrasys>; 23*4882a593Smuzhiyun mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>; 24*4882a593Smuzhiyun }; 25