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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-vop-clk-set.dtsi16 assigned-clocks = <&cru SCLK_EMMC>;
17 assigned-clock-parents = <&cru PLL_GPLL>;
18 assigned-clock-rates = <200000000>;
22 assigned-clocks = <&cru SCLK_UART0_SRC>;
23 assigned-clock-parents = <&cru PLL_GPLL>;
27 assigned-clocks = <&cru SCLK_UART_SRC>;
28 assigned-clock-parents = <&cru PLL_GPLL>;
32 assigned-clocks = <&cru SCLK_UART_SRC>;
33 assigned-clock-parents = <&cru PLL_GPLL>;
37 assigned-clocks = <&cru SCLK_UART_SRC>;
[all …]
H A Dpx30-ad-r35-mb-rk618-hdmi.dts24 assigned-clocks = <&cru SCLK_I2S1_OUT>;
25 assigned-clock-rates = <11289600>;
33 assigned-clocks = <&clock SCALER_PLLIN_CLK>,
39 assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
53 assigned-clocks = <&clock HDMI_CLK>;
54 assigned-clock-parents = <&clock VIF0_CLK>;
76 assigned-clocks = <&cru PLL_NPLL>;
77 assigned-clock-rates = <1188000000>;
H A Drk3568-nvr-demo-v10.dtsi118 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
119 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
120 assigned-clock-rates = <0>, <125000000>;
145 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
146 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
147 assigned-clock-rates = <0>, <125000000>;
192 assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
193 assigned-clock-rates = <12288000>;
194 assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
206 assigned-clocks =<&cru I2S3_MCLKOUT>, <&cru I2S3_MCLK_IOE>;
[all …]
H A Dpx30-ad-r35-mb-rk618-hdmi-lvds.dts67 assigned-clocks = <&cru SCLK_I2S1_OUT>;
68 assigned-clock-rates = <11289600>;
76 assigned-clocks = <&clock SCALER_PLLIN_CLK>,
82 assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
96 assigned-clocks = <&clock HDMI_CLK>;
97 assigned-clock-parents = <&clock VIF0_CLK>;
212 assigned-clocks = <&cru PLL_NPLL>;
213 assigned-clock-rates = <1188000000>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx7ulp.dtsi210 assigned-clock-rates = <48000000>;
211 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
212 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
221 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
222 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
223 assigned-clock-rates = <48000000>;
233 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
234 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
235 assigned-clock-rates = <48000000>;
245 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
[all …]
H A DOK3568-C.dts41 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
42 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
43 assigned-clock-rates = <0>, <125000000>;
68 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
69 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
70 assigned-clock-rates = <0>, <125000000>;
109 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
110 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL> , <&cru PLL_GPLL>;
H A D.OK3568-C.dtb.pre.tmp
H A Drk3568-evb.dts41 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
42 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
43 assigned-clock-rates = <0>, <125000000>;
68 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
69 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
70 assigned-clock-rates = <0>, <125000000>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx7ulp.dtsi154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
[all …]
H A Dexynos4412-odroid-common.dtsi125 assigned-clocks = <&clock CLK_FOUT_EPLL>;
126 assigned-clock-rates = <45158401>;
130 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
136 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
139 assigned-clock-rates = <0>, <0>,
207 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
209 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
210 assigned-clock-rates = <0>, <176000000>;
215 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
217 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
H A Dimx7d-pico.dtsi105 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
107 assigned-clock-parents = <&clks IMX7D_CKIL>;
108 assigned-clock-rates = <0>, <32768>;
121 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
123 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
124 assigned-clock-rates = <0>, <100000000>;
278 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
280 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
281 assigned-clock-rates = <0>, <24576000>;
313 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
[all …]
H A Dimx7d-zii-rpu2.dts189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>;
[all …]
H A Dimx7d-sdb.dts210 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
212 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
213 assigned-clock-rates = <0>, <100000000>;
237 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
239 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
240 assigned-clock-rates = <0>, <100000000>;
381 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
384 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
385 assigned-clock-rates = <0>, <884736000>, <12288000>;
417 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
[all …]
H A Dimx7d-cl-som-imx7.dts47 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
50 assigned-clock-rates = <0>, <100000000>;
75 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78 assigned-clock-rates = <0>, <100000000>;
197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
213 assigned-clock-rates = <400000000>;
H A Dimx7s-warp.dts84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
85 assigned-clock-rates = <884736000>;
268 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
270 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
271 assigned-clock-rates = <0>, <36864000>;
278 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
279 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
286 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
295 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
[all …]
H A Dimx7d-nitrogen7.dts114 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
116 assigned-clock-parents = <&clks IMX7D_CKIL>;
117 assigned-clock-rates = <0>, <32768>;
131 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
133 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
134 assigned-clock-rates = <0>, <100000000>;
322 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
323 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
330 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
331 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
[all …]
H A Dexynos4412-itop-elite.dts130 assigned-clocks = <&clock CLK_MOUT_CAM0>;
131 assigned-clock-parents = <&clock CLK_XUSBXTI>;
135 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
139 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
141 assigned-clock-rates = <0>, <0>, <112896000>, <11289600>;
159 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
161 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
162 assigned-clock-rates = <0>, <176000000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
H A Dmt2701-afe-pcm.txt47 - assigned-clocks: list of input clocks and dividers for the audio system.
49 - assigned-clocks-parents: parent of input clocks of assigned clocks.
50 - assigned-clock-rates: list of clock frequencies of assigned clocks.
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
144 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/img/
H A Dpistachio.dtsi51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rng/
H A Drockchip,rng.txt12 - assigned-clocks: Main clock, should be <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
14 - assigned-clock-rates : The rng core clk frequency, shall be: <150000000>, <150000000>,
25 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
26 assigned-clock-rates = <150000000>, <100000000>;
39 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
41 assigned-clock-rates = <150000000>, <150000000>,
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/msm/
H A Ddpu.txt38 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
39 - assigned-clock-rates: list of clock frequencies sorted in the same order as
40 the assigned-clocks property.
70 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
71 - assigned-clock-rates: list of clock frequencies sorted in the same order as
72 the assigned-clocks property.
87 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
88 assigned-clock-rates = <300000000>;
116 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
118 assigned-clock-rates = <0 0 300000000 19200000>;
/OK3568_Linux_fs/kernel/drivers/s390/char/
H A Dsclp_cmd.c241 u16 assigned; member
264 for (i = 0; i < sccb->assigned; i++) { in sclp_attach_storage()
425 static void __init insert_increment(u16 rn, int standby, int assigned) in insert_increment() argument
439 if (assigned && incr->rn > rn) in insert_increment()
441 if (!assigned && incr->rn - last_rn > 1) in insert_increment()
446 if (!assigned) in insert_increment()
478 int i, id, assigned, rc; in sclp_detect_standby_memory() local
488 assigned = 0; in sclp_detect_standby_memory()
498 for (i = 0; i < sccb->assigned; i++) { in sclp_detect_standby_memory()
501 assigned++; in sclp_detect_standby_memory()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j721e-main.dtsi396 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
397 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
405 assigned-clocks = <&wiz0_pll0_refclk>;
406 assigned-clock-parents = <&k3_clks 292 11>;
412 assigned-clocks = <&wiz0_pll1_refclk>;
413 assigned-clock-parents = <&k3_clks 292 0>;
419 assigned-clocks = <&wiz0_refclk_dig>;
420 assigned-clock-parents = <&k3_clks 292 11>;
453 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
454 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mq.dtsi517 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
521 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
524 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
607 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
610 assigned-clock-rates = <0>, <0>,
612 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
918 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
921 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
923 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
957 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
[all …]

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