xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx7d-pico.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2017 NXP
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/dts-v1/;
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "imx7d.dtsi"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	backlight: backlight {
11*4882a593Smuzhiyun		compatible = "pwm-backlight";
12*4882a593Smuzhiyun		pwms = <&pwm4 0 50000 0>;
13*4882a593Smuzhiyun		brightness-levels = <0 36 72 108 144 180 216 255>;
14*4882a593Smuzhiyun		default-brightness-level = <6>;
15*4882a593Smuzhiyun	};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	/* Will be filled by the bootloader */
18*4882a593Smuzhiyun	memory@80000000 {
19*4882a593Smuzhiyun		device_type = "memory";
20*4882a593Smuzhiyun		reg = <0x80000000 0>;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	panel {
24*4882a593Smuzhiyun		compatible = "vxt,vl050-8048nt-c01";
25*4882a593Smuzhiyun		backlight = <&backlight>;
26*4882a593Smuzhiyun		power-supply = <&reg_lcd_3v3>;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		port {
29*4882a593Smuzhiyun			panel_in: endpoint {
30*4882a593Smuzhiyun				remote-endpoint = <&display_out>;
31*4882a593Smuzhiyun			};
32*4882a593Smuzhiyun		};
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	reg_lcd_3v3: regulator-lcd-3v3 {
36*4882a593Smuzhiyun		compatible = "regulator-fixed";
37*4882a593Smuzhiyun		pinctrl-names = "default";
38*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_lcdreg_on>;
39*4882a593Smuzhiyun		regulator-name = "lcd-3v3";
40*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
41*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
42*4882a593Smuzhiyun		gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
43*4882a593Smuzhiyun		enable-active-high;
44*4882a593Smuzhiyun        };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	reg_wlreg_on: regulator-wlreg_on {
47*4882a593Smuzhiyun		compatible = "regulator-fixed";
48*4882a593Smuzhiyun		pinctrl-names = "default";
49*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_wlreg_on>;
50*4882a593Smuzhiyun		regulator-name = "wlreg_on";
51*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
52*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
53*4882a593Smuzhiyun		gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
54*4882a593Smuzhiyun		enable-active-high;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	reg_2p5v: regulator-2p5v {
58*4882a593Smuzhiyun		compatible = "regulator-fixed";
59*4882a593Smuzhiyun		regulator-name = "2P5V";
60*4882a593Smuzhiyun		regulator-min-microvolt = <2500000>;
61*4882a593Smuzhiyun		regulator-max-microvolt = <2500000>;
62*4882a593Smuzhiyun		regulator-always-on;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
66*4882a593Smuzhiyun		compatible = "regulator-fixed";
67*4882a593Smuzhiyun		regulator-name = "3P3V";
68*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
69*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
70*4882a593Smuzhiyun		regulator-always-on;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
74*4882a593Smuzhiyun		pinctrl-names = "default";
75*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbotg1_pwr>;
76*4882a593Smuzhiyun		compatible = "regulator-fixed";
77*4882a593Smuzhiyun		regulator-name = "usb_otg1_vbus";
78*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
79*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
80*4882a593Smuzhiyun		gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
84*4882a593Smuzhiyun		compatible = "regulator-fixed";
85*4882a593Smuzhiyun		regulator-name = "usb_otg2_vbus";
86*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
87*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	reg_vref_1v8: regulator-vref-1v8 {
91*4882a593Smuzhiyun		compatible = "regulator-fixed";
92*4882a593Smuzhiyun		regulator-name = "vref-1v8";
93*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
94*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
95*4882a593Smuzhiyun	};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun	usdhc2_pwrseq: usdhc2_pwrseq {
98*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
99*4882a593Smuzhiyun		clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
100*4882a593Smuzhiyun		clock-names = "ext_clock";
101*4882a593Smuzhiyun	};
102*4882a593Smuzhiyun};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun&clks {
105*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
106*4882a593Smuzhiyun			  <&clks IMX7D_CLKO2_ROOT_DIV>;
107*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_CKIL>;
108*4882a593Smuzhiyun	assigned-clock-rates = <0>, <32768>;
109*4882a593Smuzhiyun};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun&ecspi3 {
112*4882a593Smuzhiyun	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
113*4882a593Smuzhiyun	pinctrl-names = "default";
114*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi3>;
115*4882a593Smuzhiyun	status = "okay";
116*4882a593Smuzhiyun};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun&fec1 {
119*4882a593Smuzhiyun	pinctrl-names = "default";
120*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet1>;
121*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
122*4882a593Smuzhiyun			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
123*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
124*4882a593Smuzhiyun	assigned-clock-rates = <0>, <100000000>;
125*4882a593Smuzhiyun	phy-mode = "rgmii-id";
126*4882a593Smuzhiyun	phy-handle = <&ethphy0>;
127*4882a593Smuzhiyun	fsl,magic-packet;
128*4882a593Smuzhiyun	phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
129*4882a593Smuzhiyun	status = "okay";
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun	mdio {
132*4882a593Smuzhiyun		#address-cells = <1>;
133*4882a593Smuzhiyun		#size-cells = <0>;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun		ethphy0: ethernet-phy@1 {
136*4882a593Smuzhiyun			compatible = "ethernet-phy-ieee802.3-c22";
137*4882a593Smuzhiyun			reg = <1>;
138*4882a593Smuzhiyun			status = "okay";
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun&flexcan1 {
144*4882a593Smuzhiyun	pinctrl-names = "default";
145*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_can1>;
146*4882a593Smuzhiyun	status = "okay";
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&flexcan2 {
150*4882a593Smuzhiyun	pinctrl-names = "default";
151*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_can2>;
152*4882a593Smuzhiyun	status = "okay";
153*4882a593Smuzhiyun};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun&i2c1 {
156*4882a593Smuzhiyun	clock-frequency = <100000>;
157*4882a593Smuzhiyun	pinctrl-names = "default";
158*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
159*4882a593Smuzhiyun	status = "okay";
160*4882a593Smuzhiyun};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun&i2c2 {
163*4882a593Smuzhiyun	pinctrl-names = "default";
164*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
165*4882a593Smuzhiyun	status = "okay";
166*4882a593Smuzhiyun};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun&i2c4 {
169*4882a593Smuzhiyun	pinctrl-names = "default";
170*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c4>;
171*4882a593Smuzhiyun	status = "okay";
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun	pmic: pfuze3000@8 {
174*4882a593Smuzhiyun		compatible = "fsl,pfuze3000";
175*4882a593Smuzhiyun		reg = <0x08>;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun		regulators {
178*4882a593Smuzhiyun			sw1a_reg: sw1a {
179*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
180*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
181*4882a593Smuzhiyun				regulator-boot-on;
182*4882a593Smuzhiyun				regulator-always-on;
183*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
184*4882a593Smuzhiyun			};
185*4882a593Smuzhiyun			/* use sw1c_reg to align with pfuze100/pfuze200 */
186*4882a593Smuzhiyun			sw1c_reg: sw1b {
187*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
188*4882a593Smuzhiyun				regulator-max-microvolt = <1475000>;
189*4882a593Smuzhiyun				regulator-boot-on;
190*4882a593Smuzhiyun				regulator-always-on;
191*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
192*4882a593Smuzhiyun			};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun			sw2_reg: sw2 {
195*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
196*4882a593Smuzhiyun				regulator-max-microvolt = <1850000>;
197*4882a593Smuzhiyun				regulator-boot-on;
198*4882a593Smuzhiyun				regulator-always-on;
199*4882a593Smuzhiyun			};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun			sw3a_reg: sw3 {
202*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
203*4882a593Smuzhiyun				regulator-max-microvolt = <1650000>;
204*4882a593Smuzhiyun				regulator-boot-on;
205*4882a593Smuzhiyun				regulator-always-on;
206*4882a593Smuzhiyun			};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun			swbst_reg: swbst {
209*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
210*4882a593Smuzhiyun				regulator-max-microvolt = <5150000>;
211*4882a593Smuzhiyun			};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun			snvs_reg: vsnvs {
214*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
215*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
216*4882a593Smuzhiyun				regulator-boot-on;
217*4882a593Smuzhiyun				regulator-always-on;
218*4882a593Smuzhiyun			};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun			vref_reg: vrefddr {
221*4882a593Smuzhiyun				regulator-boot-on;
222*4882a593Smuzhiyun				regulator-always-on;
223*4882a593Smuzhiyun			};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun			vgen1_reg: vldo1 {
226*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
227*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
228*4882a593Smuzhiyun				regulator-always-on;
229*4882a593Smuzhiyun			};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun			vgen2_reg: vldo2 {
232*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
233*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
234*4882a593Smuzhiyun			};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun			vgen3_reg: vccsd {
237*4882a593Smuzhiyun				regulator-min-microvolt = <2850000>;
238*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
239*4882a593Smuzhiyun				regulator-always-on;
240*4882a593Smuzhiyun			};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun			vgen4_reg: v33 {
243*4882a593Smuzhiyun				regulator-min-microvolt = <2850000>;
244*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
245*4882a593Smuzhiyun				regulator-always-on;
246*4882a593Smuzhiyun			};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun			vgen5_reg: vldo3 {
249*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
250*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
251*4882a593Smuzhiyun				regulator-always-on;
252*4882a593Smuzhiyun			};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun			vgen6_reg: vldo4 {
255*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
256*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
257*4882a593Smuzhiyun				regulator-always-on;
258*4882a593Smuzhiyun			};
259*4882a593Smuzhiyun		};
260*4882a593Smuzhiyun	};
261*4882a593Smuzhiyun};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun&lcdif {
264*4882a593Smuzhiyun	pinctrl-names = "default";
265*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lcdif>;
266*4882a593Smuzhiyun	status = "okay";
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun	port {
269*4882a593Smuzhiyun		display_out: endpoint {
270*4882a593Smuzhiyun			remote-endpoint = <&panel_in>;
271*4882a593Smuzhiyun		};
272*4882a593Smuzhiyun	};
273*4882a593Smuzhiyun};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun&sai1 {
276*4882a593Smuzhiyun	pinctrl-names = "default";
277*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_sai1>;
278*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
279*4882a593Smuzhiyun			  <&clks IMX7D_SAI1_ROOT_CLK>;
280*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
281*4882a593Smuzhiyun	assigned-clock-rates = <0>, <24576000>;
282*4882a593Smuzhiyun	status = "okay";
283*4882a593Smuzhiyun};
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun&pwm1 {
287*4882a593Smuzhiyun	pinctrl-names = "default";
288*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
289*4882a593Smuzhiyun	status = "okay";
290*4882a593Smuzhiyun};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun&pwm2 {
293*4882a593Smuzhiyun	pinctrl-names = "default";
294*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm2>;
295*4882a593Smuzhiyun	status = "okay";
296*4882a593Smuzhiyun};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun&pwm3 {
299*4882a593Smuzhiyun	pinctrl-names = "default";
300*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
301*4882a593Smuzhiyun	status = "okay";
302*4882a593Smuzhiyun};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun&pwm4 { /* Backlight */
305*4882a593Smuzhiyun	pinctrl-names = "default";
306*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm4>;
307*4882a593Smuzhiyun	status = "okay";
308*4882a593Smuzhiyun};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun&uart5 {
311*4882a593Smuzhiyun	pinctrl-names = "default";
312*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart5>;
313*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
314*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
315*4882a593Smuzhiyun	status = "okay";
316*4882a593Smuzhiyun};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun&uart6 {
319*4882a593Smuzhiyun	pinctrl-names = "default";
320*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart6>;
321*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
322*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
323*4882a593Smuzhiyun	uart-has-rtscts;
324*4882a593Smuzhiyun	status = "okay";
325*4882a593Smuzhiyun};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun&uart7 { /* Bluetooth */
328*4882a593Smuzhiyun	pinctrl-names = "default";
329*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart7>;
330*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
331*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
332*4882a593Smuzhiyun	uart-has-rtscts;
333*4882a593Smuzhiyun	status = "okay";
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun&usbotg1 {
337*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg1_vbus>;
338*4882a593Smuzhiyun	status = "okay";
339*4882a593Smuzhiyun};
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun&usbotg2 {
342*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg2_vbus>;
343*4882a593Smuzhiyun	dr_mode = "host";
344*4882a593Smuzhiyun	status = "okay";
345*4882a593Smuzhiyun};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun&usdhc1 {
348*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
349*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
350*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
351*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
352*4882a593Smuzhiyun	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
353*4882a593Smuzhiyun	bus-width = <4>;
354*4882a593Smuzhiyun	fsl,tuning-step = <2>;
355*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
356*4882a593Smuzhiyun	wakeup-source;
357*4882a593Smuzhiyun	no-1-8-v;
358*4882a593Smuzhiyun	keep-power-in-suspend;
359*4882a593Smuzhiyun	status = "okay";
360*4882a593Smuzhiyun};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun&usdhc2 { /* Wifi SDIO */
363*4882a593Smuzhiyun	pinctrl-names = "default";
364*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
365*4882a593Smuzhiyun	no-1-8-v;
366*4882a593Smuzhiyun	non-removable;
367*4882a593Smuzhiyun	keep-power-in-suspend;
368*4882a593Smuzhiyun	wakeup-source;
369*4882a593Smuzhiyun	vmmc-supply = <&reg_wlreg_on>;
370*4882a593Smuzhiyun	mmc-pwrseq = <&usdhc2_pwrseq>;
371*4882a593Smuzhiyun	status = "okay";
372*4882a593Smuzhiyun};
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun&usdhc3 {
375*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
376*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
377*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
378*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
379*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
380*4882a593Smuzhiyun	assigned-clock-rates = <400000000>;
381*4882a593Smuzhiyun	bus-width = <8>;
382*4882a593Smuzhiyun	no-1-8-v;
383*4882a593Smuzhiyun	fsl,tuning-step = <2>;
384*4882a593Smuzhiyun	non-removable;
385*4882a593Smuzhiyun	status = "okay";
386*4882a593Smuzhiyun};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun&wdog1 {
389*4882a593Smuzhiyun	pinctrl-names = "default";
390*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_wdog>;
391*4882a593Smuzhiyun	fsl,ext-reset-output;
392*4882a593Smuzhiyun	status = "okay";
393*4882a593Smuzhiyun};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun&iomuxc {
396*4882a593Smuzhiyun	pinctrl_ecspi3: ecspi3grp {
397*4882a593Smuzhiyun		fsl,pins = <
398*4882a593Smuzhiyun			MX7D_PAD_I2C1_SCL__ECSPI3_MISO		0x2
399*4882a593Smuzhiyun			MX7D_PAD_I2C1_SDA__ECSPI3_MOSI		0x2
400*4882a593Smuzhiyun			MX7D_PAD_I2C2_SCL__ECSPI3_SCLK		0x2
401*4882a593Smuzhiyun			MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x14
402*4882a593Smuzhiyun		>;
403*4882a593Smuzhiyun	};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
406*4882a593Smuzhiyun		fsl,pins = <
407*4882a593Smuzhiyun			MX7D_PAD_UART1_TX_DATA__I2C1_SDA	0x4000007f
408*4882a593Smuzhiyun			MX7D_PAD_UART1_RX_DATA__I2C1_SCL	0x4000007f
409*4882a593Smuzhiyun		>;
410*4882a593Smuzhiyun	};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
413*4882a593Smuzhiyun		fsl,pins = <
414*4882a593Smuzhiyun			MX7D_PAD_UART2_TX_DATA__I2C2_SDA	0x4000007f
415*4882a593Smuzhiyun			MX7D_PAD_UART2_RX_DATA__I2C2_SCL	0x4000007f
416*4882a593Smuzhiyun		>;
417*4882a593Smuzhiyun	};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun	pinctrl_enet1: enet1grp {
420*4882a593Smuzhiyun		fsl,pins = <
421*4882a593Smuzhiyun			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3
422*4882a593Smuzhiyun			MX7D_PAD_SD2_WP__ENET1_MDC			0x3
423*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
424*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
425*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
426*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
427*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
428*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
429*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
430*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
431*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
432*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
433*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
434*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
435*4882a593Smuzhiyun			MX7D_PAD_SD3_RESET_B__GPIO6_IO11                0x1  /* Ethernet reset */
436*4882a593Smuzhiyun		>;
437*4882a593Smuzhiyun	};
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun	pinctrl_can1: can1frp {
440*4882a593Smuzhiyun		fsl,pins = <
441*4882a593Smuzhiyun			MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX	0x59
442*4882a593Smuzhiyun			MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX	0x59
443*4882a593Smuzhiyun		>;
444*4882a593Smuzhiyun	};
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun	pinctrl_can2: can2frp {
447*4882a593Smuzhiyun		fsl,pins = <
448*4882a593Smuzhiyun			MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX	0x59
449*4882a593Smuzhiyun			MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX	0x59
450*4882a593Smuzhiyun		>;
451*4882a593Smuzhiyun	};
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun	pinctrl_i2c4: i2c4grp {
454*4882a593Smuzhiyun		fsl,pins = <
455*4882a593Smuzhiyun			MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA		0x4000007f
456*4882a593Smuzhiyun			MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL		0x4000007f
457*4882a593Smuzhiyun		>;
458*4882a593Smuzhiyun	};
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun	pinctrl_lcdif: lcdifgrp {
461*4882a593Smuzhiyun		fsl,pins = <
462*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
463*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
464*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
465*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
466*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79
467*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79
468*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79
469*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79
470*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79
471*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79
472*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79
473*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79
474*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79
475*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79
476*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79
477*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79
478*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
479*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
480*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
481*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
482*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
483*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
484*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
485*4882a593Smuzhiyun			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
486*4882a593Smuzhiyun			MX7D_PAD_LCD_CLK__LCD_CLK		0x79
487*4882a593Smuzhiyun			MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x78
488*4882a593Smuzhiyun			MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x78
489*4882a593Smuzhiyun			MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x78
490*4882a593Smuzhiyun			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x14
491*4882a593Smuzhiyun		>;
492*4882a593Smuzhiyun	};
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun	pinctrl_pwm1: pwm1 {
495*4882a593Smuzhiyun		fsl,pins = <
496*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO08__PWM1_OUT   0x7f
497*4882a593Smuzhiyun		>;
498*4882a593Smuzhiyun	};
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun	pinctrl_pwm2: pwm2 {
501*4882a593Smuzhiyun		fsl,pins = <
502*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO09__PWM2_OUT   0x7f
503*4882a593Smuzhiyun		>;
504*4882a593Smuzhiyun	};
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun	pinctrl_pwm3: pwm3 {
507*4882a593Smuzhiyun		fsl,pins = <
508*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO10__PWM3_OUT   0x7f
509*4882a593Smuzhiyun		>;
510*4882a593Smuzhiyun	};
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun	pinctrl_pwm4: pwm4grp{
513*4882a593Smuzhiyun		fsl,pins = <
514*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO11__PWM4_OUT	0x7f
515*4882a593Smuzhiyun		>;
516*4882a593Smuzhiyun	};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun	pinctrl_reg_wlreg_on: regregongrp {
519*4882a593Smuzhiyun		fsl,pins = <
520*4882a593Smuzhiyun			MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16	0x59
521*4882a593Smuzhiyun		>;
522*4882a593Smuzhiyun	};
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun	pinctrl_sai1: sai1grp {
525*4882a593Smuzhiyun		fsl,pins = <
526*4882a593Smuzhiyun			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK	0x1f
527*4882a593Smuzhiyun			MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC	0x1f
528*4882a593Smuzhiyun			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30
529*4882a593Smuzhiyun			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f
530*4882a593Smuzhiyun		>;
531*4882a593Smuzhiyun	};
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun	pinctrl_uart5: uart5grp {
534*4882a593Smuzhiyun		fsl,pins = <
535*4882a593Smuzhiyun			MX7D_PAD_I2C4_SDA__UART5_DCE_TX		0x79
536*4882a593Smuzhiyun			MX7D_PAD_I2C4_SCL__UART5_DCE_RX		0x79
537*4882a593Smuzhiyun		>;
538*4882a593Smuzhiyun	};
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun	pinctrl_uart6: uart6grp {
541*4882a593Smuzhiyun		fsl,pins = <
542*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA08__UART6_DCE_RX	0x79
543*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA09__UART6_DCE_TX	0x79
544*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS	0x79
545*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS	0x79
546*4882a593Smuzhiyun		>;
547*4882a593Smuzhiyun	};
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun	pinctrl_uart7: uart7grp {
550*4882a593Smuzhiyun		fsl,pins = <
551*4882a593Smuzhiyun			MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX	0x79
552*4882a593Smuzhiyun			MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX	0x79
553*4882a593Smuzhiyun			MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS	0x79
554*4882a593Smuzhiyun			MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS	0x79
555*4882a593Smuzhiyun		>;
556*4882a593Smuzhiyun	};
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun	pinctrl_usbotg1_pwr: usbotg_pwr {
559*4882a593Smuzhiyun		fsl,pins = <
560*4882a593Smuzhiyun			MX7D_PAD_UART3_TX_DATA__GPIO4_IO5	0x14
561*4882a593Smuzhiyun		>;
562*4882a593Smuzhiyun	};
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
565*4882a593Smuzhiyun		fsl,pins = <
566*4882a593Smuzhiyun			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
567*4882a593Smuzhiyun			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
568*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
569*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
570*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
571*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
572*4882a593Smuzhiyun			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x15
573*4882a593Smuzhiyun		>;
574*4882a593Smuzhiyun	};
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
577*4882a593Smuzhiyun		fsl,pins = <
578*4882a593Smuzhiyun			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
579*4882a593Smuzhiyun			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
580*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
581*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
582*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
583*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
584*4882a593Smuzhiyun			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x15
585*4882a593Smuzhiyun		>;
586*4882a593Smuzhiyun	};
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
589*4882a593Smuzhiyun		fsl,pins = <
590*4882a593Smuzhiyun			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
591*4882a593Smuzhiyun			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
592*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
593*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
594*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
595*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
596*4882a593Smuzhiyun			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x15
597*4882a593Smuzhiyun		>;
598*4882a593Smuzhiyun	};
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
601*4882a593Smuzhiyun		fsl,pins = <
602*4882a593Smuzhiyun			MX7D_PAD_SD2_CMD__SD2_CMD		0x59
603*4882a593Smuzhiyun			MX7D_PAD_SD2_CLK__SD2_CLK		0x19
604*4882a593Smuzhiyun			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
605*4882a593Smuzhiyun			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
606*4882a593Smuzhiyun			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
607*4882a593Smuzhiyun			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
608*4882a593Smuzhiyun		>;
609*4882a593Smuzhiyun	};
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun	pinctrl_usdhc3: usdhc3grp {
612*4882a593Smuzhiyun		fsl,pins = <
613*4882a593Smuzhiyun			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
614*4882a593Smuzhiyun			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
615*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
616*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
617*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
618*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
619*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
620*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
621*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
622*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
623*4882a593Smuzhiyun		>;
624*4882a593Smuzhiyun	};
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
627*4882a593Smuzhiyun		fsl,pins = <
628*4882a593Smuzhiyun			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
629*4882a593Smuzhiyun			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
630*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
631*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
632*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
633*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
634*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
635*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
636*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
637*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
638*4882a593Smuzhiyun		>;
639*4882a593Smuzhiyun	};
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
642*4882a593Smuzhiyun		fsl,pins = <
643*4882a593Smuzhiyun			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
644*4882a593Smuzhiyun			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
645*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
646*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
647*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
648*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
649*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
650*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
651*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
652*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
653*4882a593Smuzhiyun		>;
654*4882a593Smuzhiyun	};
655*4882a593Smuzhiyun};
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun&iomuxc_lpsr {
658*4882a593Smuzhiyun	pinctrl_wifi_clk: wificlkgrp {
659*4882a593Smuzhiyun		fsl,pins = <
660*4882a593Smuzhiyun			MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2	0x7d
661*4882a593Smuzhiyun		>;
662*4882a593Smuzhiyun	};
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun	pinctrl_reg_lcdreg_on: reglcdongrp {
665*4882a593Smuzhiyun	fsl,pins = <
666*4882a593Smuzhiyun			MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6	0x59
667*4882a593Smuzhiyun		>;
668*4882a593Smuzhiyun	};
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun	pinctrl_wdog: wdoggrp {
671*4882a593Smuzhiyun		fsl,pins = <
672*4882a593Smuzhiyun			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x74
673*4882a593Smuzhiyun		>;
674*4882a593Smuzhiyun	};
675*4882a593Smuzhiyun};
676