1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6/dts-v1/; 7#include <dt-bindings/display/media-bus-format.h> 8#include <dt-bindings/clock/rk618-cru.h> 9#include "px30-ad-r35-mb.dtsi" 10 11/ { 12 panel { 13 compatible = "simple-panel"; 14 backlight = <&backlight>; 15 power-supply = <&vcc3v3_lcd>; 16 enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; 17 prepare-delay-ms = <120>; 18 enable-delay-ms = <120>; 19 disable-delay-ms = <120>; 20 unprepare-delay-ms = <120>; 21 bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>; 22 width-mm = <231>; 23 height-mm = <154>; 24 25 display-timings { 26 native-mode = <&timing1>; 27 28 timing1: timing1 { 29 clock-frequency = <72000000>; 30 hactive = <1280>; 31 vactive = <800>; 32 hback-porch = <60>; 33 hfront-porch = <60>; 34 vback-porch = <16>; 35 vfront-porch = <16>; 36 hsync-len = <40>; 37 vsync-len = <6>; 38 hsync-active = <0>; 39 vsync-active = <0>; 40 de-active = <0>; 41 pixelclk-active = <0>; 42 }; 43 }; 44 45 port { 46 panel_in_lvds: endpoint { 47 remote-endpoint = <&lvds_out_panel>; 48 }; 49 }; 50 }; 51}; 52 53&dmc { 54 auto-freq-en = <0>; 55}; 56 57&i2c0 { 58 status = "okay"; 59 60 rk618@50 { 61 compatible = "rockchip,rk618"; 62 reg = <0x50>; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&i2s1_2ch_mclk>; 65 clocks = <&cru SCLK_I2S1_OUT>; 66 clock-names = "clkin"; 67 assigned-clocks = <&cru SCLK_I2S1_OUT>; 68 assigned-clock-rates = <11289600>; 69 reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; 70 status = "okay"; 71 72 clock: cru { 73 compatible = "rockchip,rk618-cru"; 74 clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; 75 clock-names = "clkin", "lcdc0_dclkp"; 76 assigned-clocks = <&clock SCALER_PLLIN_CLK>, 77 <&clock VIF_PLLIN_CLK>, 78 <&clock SCALER_CLK>, 79 <&clock VIF0_PRE_CLK>, 80 <&clock CODEC_CLK>, 81 <&clock DITHER_CLK>; 82 assigned-clock-parents = <&cru SCLK_I2S1_OUT>, 83 <&clock LCDC0_CLK>, 84 <&clock SCALER_PLL_CLK>, 85 <&clock VIF_PLL_CLK>, 86 <&cru SCLK_I2S1_OUT>, 87 <&clock VIF0_CLK>; 88 #clock-cells = <1>; 89 status = "okay"; 90 }; 91 92 hdmi { 93 compatible = "rockchip,rk618-hdmi"; 94 clocks = <&clock HDMI_CLK>; 95 clock-names = "hdmi"; 96 assigned-clocks = <&clock HDMI_CLK>; 97 assigned-clock-parents = <&clock VIF0_CLK>; 98 interrupt-parent = <&gpio2>; 99 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 100 status = "okay"; 101 102 ports { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 106 port@0 { 107 reg = <0>; 108 109 hdmi_in_vif: endpoint { 110 remote-endpoint = <&vif_out_hdmi>; 111 }; 112 }; 113 114 port@1 { 115 reg = <1>; 116 117 hdmi_out_scaler: endpoint { 118 remote-endpoint = <&scaler_in_hdmi>; 119 }; 120 }; 121 }; 122 }; 123 124 lvds { 125 compatible = "rockchip,rk618-lvds"; 126 clocks = <&clock LVDS_CLK>; 127 clock-names = "lvds"; 128 status = "okay"; 129 130 ports { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 134 port@0 { 135 reg = <0>; 136 137 lvds_in_scaler: endpoint { 138 remote-endpoint = <&scaler_out_lvds>; 139 }; 140 }; 141 142 port@1 { 143 reg = <1>; 144 145 lvds_out_panel: endpoint { 146 remote-endpoint = <&panel_in_lvds>; 147 }; 148 }; 149 }; 150 }; 151 152 scaler { 153 compatible = "rockchip,rk618-scaler"; 154 clocks = <&clock SCALER_CLK>, <&clock VIF0_CLK>, 155 <&clock DITHER_CLK>; 156 clock-names = "scaler", "vif", "dither"; 157 status = "okay"; 158 159 ports { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 163 port@0 { 164 reg = <0>; 165 166 scaler_in_hdmi: endpoint { 167 remote-endpoint = <&hdmi_out_scaler>; 168 }; 169 }; 170 171 port@1 { 172 reg = <1>; 173 174 scaler_out_lvds: endpoint { 175 remote-endpoint = <&lvds_in_scaler>; 176 }; 177 }; 178 }; 179 }; 180 181 vif { 182 compatible = "rockchip,rk618-vif"; 183 clocks = <&clock VIF0_CLK>, <&clock VIF0_PRE_CLK>; 184 clock-names = "vif", "vif_pre"; 185 status = "okay"; 186 187 ports { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 port@0 { 192 reg = <0>; 193 194 vif_in_rgb: endpoint { 195 remote-endpoint = <&rgb_out_vif>; 196 }; 197 }; 198 199 port@1 { 200 reg = <1>; 201 202 vif_out_hdmi: endpoint { 203 remote-endpoint = <&hdmi_in_vif>; 204 }; 205 }; 206 }; 207 }; 208 }; 209}; 210 211&vopl { 212 assigned-clocks = <&cru PLL_NPLL>; 213 assigned-clock-rates = <1188000000>; 214}; 215 216&rgb { 217 status = "okay"; 218 219 ports { 220 port@1 { 221 reg = <1>; 222 223 rgb_out_vif: endpoint { 224 remote-endpoint = <&vif_in_rgb>; 225 }; 226 }; 227 }; 228}; 229 230&rgb_in_vopb { 231 status = "disabled"; 232}; 233 234&rgb_in_vopl { 235 status = "okay"; 236}; 237 238&route_rgb { 239 connect = <&vopl_out_rgb>; 240 status = "okay"; 241}; 242