Searched refs:MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET (Results 1 – 17 of 17) sorted by relevance
451 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display_b850v3()495 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display_bx50v3()
456 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in enable_lvds()544 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in enable_spi_display()
173 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
409 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) in setup_display_clock()
352 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
360 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
482 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display()
284 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
408 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display()
567 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
517 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
597 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
782 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
501 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 macro
719 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
651 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET | in setup_display()
457 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()