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Searched refs:DPLL_MODE_SHIFT (Results 1 – 12 of 12) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3066.h172 DPLL_MODE_SHIFT = 4, enumerator
173 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
H A Dcru_rk3036.h106 DPLL_MODE_SHIFT = 4, enumerator
107 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
H A Dcru_rk3288.h246 DPLL_MODE_SHIFT = 4, enumerator
247 DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT,
H A Dcru_px30.h168 DPLL_MODE_SHIFT = 4, enumerator
169 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
H A Dcru_rk3188.h182 DPLL_MODE_SHIFT = 4, enumerator
H A Dcru_rk3308.h141 DPLL_MODE_SHIFT = 2, enumerator
142 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3188.c169 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
170 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); in rkclk_configure_ddr()
179 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
180 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); in rkclk_configure_ddr()
253 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
H A Dclk_rk3066.c172 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); in rkclk_configure_ddr()
182 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); in rkclk_configure_ddr()
255 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
H A Dclk_rk3288.c277 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
333 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); in rkclk_configure_ddr()
343 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); in rkclk_configure_ddr()
H A Dclk_rk3036.c209 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, in rkclk_pll_get_rate()
H A Dclk_px30.c94 APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c333 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); in rkdclk_init()
352 DPLL_MODE_NORM << DPLL_MODE_SHIFT); in rkdclk_init()