Searched refs:CLK_SDMMC2 (Results 1 – 15 of 15) sorted by relevance
| /OK3568_Linux_fs/kernel/include/dt-bindings/clock/ |
| H A D | exynos5250.h | 85 #define CLK_SDMMC2 282 macro
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| H A D | exynos4.h | 137 #define CLK_SDMMC2 299 macro
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| H A D | exynos3250.h | 229 #define CLK_SDMMC2 223 macro
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| H A D | rk3568-cru.h | 257 #define CLK_SDMMC2 194 macro
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| /OK3568_Linux_fs/u-boot/include/dt-bindings/clock/ |
| H A D | rk3568-cru.h | 257 #define CLK_SDMMC2 194 macro
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3568.c | 1433 case CLK_SDMMC2: in rk3568_sdmmc_get_clk() 1503 case CLK_SDMMC2: in rk3568_sdmmc_set_clk() 2580 case CLK_SDMMC2: in rk3568_clk_get_rate() 2766 case CLK_SDMMC2: in rk3568_clk_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk-exynos5250.c | 563 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
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| H A D | clk-exynos3250.c | 643 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
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| H A D | clk-exynos4.c | 843 GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | exynos3250.dtsi | 395 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
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| H A D | exynos4.dtsi | 341 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
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| H A D | exynos5250.dtsi | 562 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3568.c | 974 COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0,
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| /OK3568_Linux_fs/u-boot/arch/arm/dts/ |
| H A D | rk3568.dtsi | 1642 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3568.dtsi | 2307 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
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