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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sram/
H A Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
H A Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
19 "#address-cells":
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-zynq/
H A Du-boot-spl.lds3 * Copyright (c) 2004-2008 Texas Instruments
8 * SPDX-License-Identifier: GPL-2.0+
11 MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
16 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
28 } > .sram
33 } > .sram
38 } > .sram
43 } > .sram
51 /* Move BSS section to RAM because of FAT */
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
H A Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&intc>;
13 osc24M: clk-24M {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 clock-output-names = "osc24M";
20 osc32k: clk-32k {
[all …]
H A Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
H A Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
H A Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/
H A Dti-emif-pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/
H A Dhwinit-common.c12 * SPDX-License-Identifier: GPL-2.0+
32 writew(pad->val, base + pad->offset); in do_set_mux()
92 printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev); in omap_rev_string()
107 * do_board_detect() - Detect board description
117 * vcores_init() - Assign omap_vcores based on board
131 * early_system_init - Does Early system initialization.
136 * 1. SPL running from SRAM
137 * 2. U-Boot running from FLASH
138 * 3. U-Boot loaded to SDRAM by SPL
139 * 4. U-Boot loaded to SDRAM by ROM code using the
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]
H A Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-tcon-top.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/thermal/thermal.h>
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/OK3568_Linux_fs/u-boot/tools/binman/etype/
H A Du_boot_ucode.py4 # SPDX-License-Identifier: GPL-2.0+
6 # Entry-type module for a U-Boot binary with an embedded microcode pointer
14 """U-Boot microcode block
16 U-Boot on x86 needs a single block of microcode. This is collected from
20 microcode is supplied before there is any SRAM available to use (i.e.
21 the FSP sets up the SRAM / cache-as-RAM but does so in the call that
23 microcode the same way in U-Boot (even non-FSP platforms). This is that
26 platforms), or used to set up the microcode (for non-FSP platforms).
28 the microcode into a single blob and accessible without SRAM.
32 entry (u-boot-ucode) is empty. If there is more than one update, then
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/OK3568_Linux_fs/kernel/drivers/input/touchscreen/gt9xx/
H A Dgt9xx_update.c3 * 2010 - 2012 Goodix Technology.
33 * 1. multi-system supported
143 buf[2~len-1]: read data buffer.
152 s32 ret=-1; in gup_i2c_read()
158 msgs[0].addr = client->addr; in gup_i2c_read()
166 msgs[1].addr = client->addr; in gup_i2c_read()
167 msgs[1].len = len - GTP_ADDR_LENGTH; in gup_i2c_read()
175 ret = i2c_transfer(client->adapter, msgs, 2); in gup_i2c_read()
189 buf[2~len-1]: data buffer
198 s32 ret=-1; in gup_i2c_write()
[all …]
/OK3568_Linux_fs/u-boot/board/cadence/xtfpga/
H A DREADME8 - XT-AV60 / LX60
9 - XT-AV110 / LX110
10 - XT-AV200 / LX200
11 - ML605
12 - KC705
16 - An Xtensa or Diamond processor core.
17 - An on-chip-debug (OCD) JTAG interface.
18 - A 16550 compatible UART and serial port.
19 - An OpenCores Wishbone 10/100-base-T ethernet interface.
20 - A 32 char two line LCD display. (except for the LX200)
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/
H A Du-boot-spl.lds7 * SPDX-License-Identifier: GPL-2.0+
35 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
36 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
70 /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
72 .bootpg ADDR(.text) - 0x1000 :
86 #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
89 #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
/OK3568_Linux_fs/kernel/arch/csky/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
119 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
162 # VA_BITS - PAGE_SHIFT - 3
196 prompt "C-SKY PMU type"
226 bool "Tightly-Coupled/Sram Memory"
229 The implementation are not only used by TCM (Tightly-Coupled Meory)
230 but also used by sram on SOC bus. It follow existed linux tcm
232 re-used directly.
276 bool "Symmetric Multi-Processing (SMP) support for C-SKY"
281 int "Maximum number of CPUs (2-32)"
[all …]
/OK3568_Linux_fs/kernel/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
10 * Asynchronous SRAM like memories and application specific integrated
14 * Pseudo-SRAM devices
17 IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1
85 4. read async non-muxed
107 6. read sync non-muxed
131 8. write async non-muxed
157 10. write sync non-muxed
/OK3568_Linux_fs/kernel/sound/soc/intel/catpt/
H A Ddsp.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
19 return param == chan->device->dev; in catpt_dma_filter()
39 chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev); in catpt_dma_request_config_chan()
41 dev_err(cdev->dev, "request channel failed\n"); in catpt_dma_request_config_chan()
42 return ERR_PTR(-ENODEV); in catpt_dma_request_config_chan()
54 dev_err(cdev->dev, "slave config failed: %d\n", ret); in catpt_dma_request_config_chan()
73 dev_err(cdev->dev, "prep dma memcpy failed\n"); in catpt_dma_memcpy()
74 return -EIO; in catpt_dma_memcpy()
79 CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id), in catpt_dma_memcpy()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/
H A Du-boot.lds2 * Copyright (c) 2004-2008 Texas Instruments
7 * SPDX-License-Identifier: GPL-2.0+
13 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
24 * bundle with u-boot, and code offsets are fixed. Secure zone
30 * be included in u-boot address space, and some absolute address
32 * code also needs to be relocated along with the accompanying u-boot
52 /* Align the secure section only if we're going to use it in situ */
91 /* Align end of stack section to page boundary */
98 * We are not checking (__secure_end - __secure_start) here,
100 * stack section. Instead, use the end of the stack section
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-rockchip/
H A Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Tony Xie <tony.xie@rock-chips.com>
14 * ddr to sram for system resumeing.
15 * so it is ".data section".
64 .word . - rockchip_slp_cpu_resume
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun5i-a10s.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&intc>;
60 #address-cells = <1>;
61 #size-cells = <1>;
65 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
67 allwinner,pipeline = "de_be0-lcd0-hdmi";
[all …]
H A Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun4i-a10-pll2.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&intc>;
60 #address-cells = <1>;
61 #size-cells = <1>;
65 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
[all …]
/OK3568_Linux_fs/kernel/drivers/atm/
H A Dnicstar.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 have 32K x 32bit SRAM, in which case
48 128K x 32bit SRAM will limit the maximum
56 #define NUM_HB 8 /* Pre-allocated huge buffers */
107 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
108 (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
111 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
112 #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
114 #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */
122 * RSQ - Receive Status Queue
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/ti-common/
H A Dsys_proto.h5 * SPDX-License-Identifier: GPL-2.0+
32 * u-boot can be running from sdram either because of configuration in uboot_loaded_by_spl()
36 * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a in uboot_loaded_by_spl()
37 * mandatory section if CH is present. in uboot_loaded_by_spl()
39 if (gd->arch.omap_ch_flags & CH_FLAGS_CHSETTINGS) in uboot_loaded_by_spl()
48 * 1. SPL running from SRAM
49 * 2. U-Boot running from FLASH
50 * 3. Non-XIP U-Boot loaded to SDRAM by SPL
51 * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the

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