1 /*
2 *
3 * Common functions for OMAP4/5 based boards
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Author :
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14 #include <common.h>
15 #include <debug_uart.h>
16 #include <spl.h>
17 #include <asm/arch/sys_proto.h>
18 #include <linux/sizes.h>
19 #include <asm/emif.h>
20 #include <asm/omap_common.h>
21 #include <linux/compiler.h>
22 #include <asm/system.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
do_set_mux(u32 base,struct pad_conf_entry const * array,int size)26 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
27 {
28 int i;
29 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
30
31 for (i = 0; i < size; i++, pad++)
32 writew(pad->val, base + pad->offset);
33 }
34
set_mux_conf_regs(void)35 static void set_mux_conf_regs(void)
36 {
37 switch (omap_hw_init_context()) {
38 case OMAP_INIT_CONTEXT_SPL:
39 set_muxconf_regs();
40 break;
41 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
42 break;
43 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
44 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
45 set_muxconf_regs();
46 break;
47 }
48 }
49
cortex_rev(void)50 u32 cortex_rev(void)
51 {
52
53 unsigned int rev;
54
55 /* Read Main ID Register (MIDR) */
56 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
57
58 return rev;
59 }
60
omap_rev_string(void)61 static void omap_rev_string(void)
62 {
63 u32 omap_rev = omap_revision();
64 u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
65 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
66 u32 major_rev = (omap_rev & 0x00000F00) >> 8;
67 u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
68
69 const char *sec_s;
70
71 switch (get_device_type()) {
72 case TST_DEVICE:
73 sec_s = "TST";
74 break;
75 case EMU_DEVICE:
76 sec_s = "EMU";
77 break;
78 case HS_DEVICE:
79 sec_s = "HS";
80 break;
81 case GP_DEVICE:
82 sec_s = "GP";
83 break;
84 default:
85 sec_s = "?";
86 }
87
88 if (soc_variant)
89 printf("OMAP");
90 else
91 printf("DRA");
92 printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev);
93 }
94
95 #ifdef CONFIG_SPL_BUILD
spl_display_print(void)96 void spl_display_print(void)
97 {
98 omap_rev_string();
99 }
100 #endif
101
srcomp_enable(void)102 void __weak srcomp_enable(void)
103 {
104 }
105
106 /**
107 * do_board_detect() - Detect board description
108 *
109 * Function to detect board description. This is expected to be
110 * overridden in the SoC family board file where desired.
111 */
do_board_detect(void)112 void __weak do_board_detect(void)
113 {
114 }
115
116 /**
117 * vcores_init() - Assign omap_vcores based on board
118 *
119 * Function to pick the vcores based on board. This is expected to be
120 * overridden in the SoC family board file where desired.
121 */
vcores_init(void)122 void __weak vcores_init(void)
123 {
124 }
125
s_init(void)126 void s_init(void)
127 {
128 }
129
130 /**
131 * early_system_init - Does Early system initialization.
132 *
133 * Does early system init of watchdog, muxing, andclocks
134 * Watchdog disable is done always. For the rest what gets done
135 * depends on the boot mode in which this function is executed when
136 * 1. SPL running from SRAM
137 * 2. U-Boot running from FLASH
138 * 3. U-Boot loaded to SDRAM by SPL
139 * 4. U-Boot loaded to SDRAM by ROM code using the
140 * Configuration Header feature
141 * Please have a look at the respective functions to see what gets
142 * done in each of these cases
143 * This function is called with SRAM stack.
144 */
early_system_init(void)145 void early_system_init(void)
146 {
147 init_omap_revision();
148 hw_data_init();
149
150 #ifdef CONFIG_SPL_BUILD
151 if (warm_reset())
152 force_emif_self_refresh();
153 #endif
154 watchdog_init();
155 set_mux_conf_regs();
156 #ifdef CONFIG_SPL_BUILD
157 srcomp_enable();
158 do_io_settings();
159 #endif
160 setup_early_clocks();
161 #ifdef CONFIG_SPL_BUILD
162 /*
163 * Save the boot parameters passed from romcode.
164 * We cannot delay the saving further than this,
165 * to prevent overwrites.
166 */
167 save_omap_boot_params();
168 spl_early_init();
169 #endif
170 do_board_detect();
171 vcores_init();
172 #ifdef CONFIG_DEBUG_UART_OMAP
173 debug_uart_init();
174 #endif
175 prcm_init();
176 }
177
178 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)179 void board_init_f(ulong dummy)
180 {
181 early_system_init();
182 #ifdef CONFIG_BOARD_EARLY_INIT_F
183 board_early_init_f();
184 #endif
185 /* For regular u-boot sdram_init() is called from dram_init() */
186 sdram_init();
187 gd->ram_size = omap_sdram_size();
188 }
189 #endif
190
arch_cpu_init_dm(void)191 int arch_cpu_init_dm(void)
192 {
193 early_system_init();
194 return 0;
195 }
196
197 /*
198 * Routine: wait_for_command_complete
199 * Description: Wait for posting to finish on watchdog
200 */
wait_for_command_complete(struct watchdog * wd_base)201 void wait_for_command_complete(struct watchdog *wd_base)
202 {
203 int pending = 1;
204 do {
205 pending = readl(&wd_base->wwps);
206 } while (pending);
207 }
208
209 /*
210 * Routine: watchdog_init
211 * Description: Shut down watch dogs
212 */
watchdog_init(void)213 void watchdog_init(void)
214 {
215 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
216
217 writel(WD_UNLOCK1, &wd2_base->wspr);
218 wait_for_command_complete(wd2_base);
219 writel(WD_UNLOCK2, &wd2_base->wspr);
220 }
221
222
223 /*
224 * This function finds the SDRAM size available in the system
225 * based on DMM section configurations
226 * This is needed because the size of memory installed may be
227 * different on different versions of the board
228 */
omap_sdram_size(void)229 u32 omap_sdram_size(void)
230 {
231 u32 section, i, valid;
232 u64 sdram_start = 0, sdram_end = 0, addr,
233 size, total_size = 0, trap_size = 0, trap_start = 0;
234
235 for (i = 0; i < 4; i++) {
236 section = __raw_readl(DMM_BASE + i*4);
237 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
238 (EMIF_SDRC_ADDRSPC_SHIFT);
239 addr = section & EMIF_SYS_ADDR_MASK;
240
241 /* See if the address is valid */
242 if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
243 (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
244 size = ((section & EMIF_SYS_SIZE_MASK) >>
245 EMIF_SYS_SIZE_SHIFT);
246 size = 1 << size;
247 size *= SZ_16M;
248
249 if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
250 if (!sdram_start || (addr < sdram_start))
251 sdram_start = addr;
252 if (!sdram_end || ((addr + size) > sdram_end))
253 sdram_end = addr + size;
254 } else {
255 trap_size = size;
256 trap_start = addr;
257 }
258 }
259 }
260
261 if ((trap_start >= sdram_start) && (trap_start < sdram_end))
262 total_size = (sdram_end - sdram_start) - (trap_size);
263 else
264 total_size = sdram_end - sdram_start;
265
266 return total_size;
267 }
268
269
270 /*
271 * Routine: dram_init
272 * Description: sets uboots idea of sdram size
273 */
dram_init(void)274 int dram_init(void)
275 {
276 sdram_init();
277 gd->ram_size = omap_sdram_size();
278 return 0;
279 }
280
281 /*
282 * Print board information
283 */
checkboard(void)284 int checkboard(void)
285 {
286 puts(sysinfo.board_string);
287 return 0;
288 }
289
290 #if defined(CONFIG_DISPLAY_CPUINFO)
291 /*
292 * Print CPU information
293 */
print_cpuinfo(void)294 int print_cpuinfo(void)
295 {
296 puts("CPU : ");
297 omap_rev_string();
298
299 return 0;
300 }
301 #endif
302