1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun * Author: Tony Xie <tony.xie@rock-chips.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <linux/linkage.h> 8*4882a593Smuzhiyun#include <asm/assembler.h> 9*4882a593Smuzhiyun#include <asm/memory.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun.data 12*4882a593Smuzhiyun/* 13*4882a593Smuzhiyun * this code will be copied from 14*4882a593Smuzhiyun * ddr to sram for system resumeing. 15*4882a593Smuzhiyun * so it is ".data section". 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun .align 2 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunENTRY(rockchip_slp_cpu_resume) 20*4882a593Smuzhiyun setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off 21*4882a593Smuzhiyun mrc p15, 0, r1, c0, c0, 5 22*4882a593Smuzhiyun and r1, r1, #0xf 23*4882a593Smuzhiyun cmp r1, #0 24*4882a593Smuzhiyun /* olny cpu0 can continue to run, the others is halt here */ 25*4882a593Smuzhiyun beq cpu0run 26*4882a593Smuzhiyunsecondary_loop: 27*4882a593Smuzhiyun wfe 28*4882a593Smuzhiyun b secondary_loop 29*4882a593Smuzhiyuncpu0run: 30*4882a593Smuzhiyun ldr r3, rkpm_bootdata_l2ctlr_f 31*4882a593Smuzhiyun cmp r3, #0 32*4882a593Smuzhiyun beq sp_set 33*4882a593Smuzhiyun ldr r3, rkpm_bootdata_l2ctlr 34*4882a593Smuzhiyun mcr p15, 1, r3, c9, c0, 2 35*4882a593Smuzhiyunsp_set: 36*4882a593Smuzhiyun ldr sp, rkpm_bootdata_cpusp 37*4882a593Smuzhiyun ldr r1, rkpm_bootdata_cpu_code 38*4882a593Smuzhiyun bx r1 39*4882a593SmuzhiyunENDPROC(rockchip_slp_cpu_resume) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun/* Parameters filled in by the kernel */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun/* Flag for whether to restore L2CTLR on resume */ 44*4882a593Smuzhiyun .global rkpm_bootdata_l2ctlr_f 45*4882a593Smuzhiyunrkpm_bootdata_l2ctlr_f: 46*4882a593Smuzhiyun .long 0 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun/* Saved L2CTLR to restore on resume */ 49*4882a593Smuzhiyun .global rkpm_bootdata_l2ctlr 50*4882a593Smuzhiyunrkpm_bootdata_l2ctlr: 51*4882a593Smuzhiyun .long 0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun/* CPU resume SP addr */ 54*4882a593Smuzhiyun .globl rkpm_bootdata_cpusp 55*4882a593Smuzhiyunrkpm_bootdata_cpusp: 56*4882a593Smuzhiyun .long 0 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun/* CPU resume function (physical address) */ 59*4882a593Smuzhiyun .globl rkpm_bootdata_cpu_code 60*4882a593Smuzhiyunrkpm_bootdata_cpu_code: 61*4882a593Smuzhiyun .long 0 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunENTRY(rk3288_bootram_sz) 64*4882a593Smuzhiyun .word . - rockchip_slp_cpu_resume 65