1*4882a593Smuzhiyun.. SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun======================================== 4*4882a593SmuzhiyunGPMC (General Purpose Memory Controller) 5*4882a593Smuzhiyun======================================== 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunGPMC is an unified memory controller dedicated to interfacing external 8*4882a593Smuzhiyunmemory devices like 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun * Asynchronous SRAM like memories and application specific integrated 11*4882a593Smuzhiyun circuit devices. 12*4882a593Smuzhiyun * Asynchronous, synchronous, and page mode burst NOR flash devices 13*4882a593Smuzhiyun NAND flash 14*4882a593Smuzhiyun * Pseudo-SRAM devices 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunGPMC is found on Texas Instruments SoC's (OMAP based) 17*4882a593SmuzhiyunIP details: https://www.ti.com/lit/pdf/spruh73 section 7.1 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunGPMC generic timing calculation: 21*4882a593Smuzhiyun================================ 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunGPMC has certain timings that has to be programmed for proper 24*4882a593Smuzhiyunfunctioning of the peripheral, while peripheral has another set of 25*4882a593Smuzhiyuntimings. To have peripheral work with gpmc, peripheral timings has to 26*4882a593Smuzhiyunbe translated to the form gpmc can understand. The way it has to be 27*4882a593Smuzhiyuntranslated depends on the connected peripheral. Also there is a 28*4882a593Smuzhiyundependency for certain gpmc timings on gpmc clock frequency. Hence a 29*4882a593Smuzhiyungeneric timing routine was developed to achieve above requirements. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunGeneric routine provides a generic method to calculate gpmc timings 32*4882a593Smuzhiyunfrom gpmc peripheral timings. struct gpmc_device_timings fields has to 33*4882a593Smuzhiyunbe updated with timings from the datasheet of the peripheral that is 34*4882a593Smuzhiyunconnected to gpmc. A few of the peripheral timings can be fed either 35*4882a593Smuzhiyunin time or in cycles, provision to handle this scenario has been 36*4882a593Smuzhiyunprovided (refer struct gpmc_device_timings definition). It may so 37*4882a593Smuzhiyunhappen that timing as specified by peripheral datasheet is not present 38*4882a593Smuzhiyunin timing structure, in this scenario, try to correlate peripheral 39*4882a593Smuzhiyuntiming to the one available. If that doesn't work, try to add a new 40*4882a593Smuzhiyunfield as required by peripheral, educate generic timing routine to 41*4882a593Smuzhiyunhandle it, make sure that it does not break any of the existing. 42*4882a593SmuzhiyunThen there may be cases where peripheral datasheet doesn't mention 43*4882a593Smuzhiyuncertain fields of struct gpmc_device_timings, zero those entries. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunGeneric timing routine has been verified to work properly on 46*4882a593Smuzhiyunmultiple onenand's and tusb6010 peripherals. 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunA word of caution: generic timing routine has been developed based 49*4882a593Smuzhiyunon understanding of gpmc timings, peripheral timings, available 50*4882a593Smuzhiyuncustom timing routines, a kind of reverse engineering without 51*4882a593Smuzhiyunmost of the datasheets & hardware (to be exact none of those supported 52*4882a593Smuzhiyunin mainline having custom timing routine) and by simulation. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyungpmc timing dependency on peripheral timings: 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun[<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...] 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun1. common 59*4882a593Smuzhiyun 60*4882a593Smuzhiyuncs_on: 61*4882a593Smuzhiyun t_ceasu 62*4882a593Smuzhiyunadv_on: 63*4882a593Smuzhiyun t_avdasu, t_ceavd 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun2. sync common 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunsync_clk: 68*4882a593Smuzhiyun clk 69*4882a593Smuzhiyunpage_burst_access: 70*4882a593Smuzhiyun t_bacc 71*4882a593Smuzhiyunclk_activation: 72*4882a593Smuzhiyun t_ces, t_avds 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun3. read async muxed 75*4882a593Smuzhiyun 76*4882a593Smuzhiyunadv_rd_off: 77*4882a593Smuzhiyun t_avdp_r 78*4882a593Smuzhiyunoe_on: 79*4882a593Smuzhiyun t_oeasu, t_aavdh 80*4882a593Smuzhiyunaccess: 81*4882a593Smuzhiyun t_iaa, t_oe, t_ce, t_aa 82*4882a593Smuzhiyunrd_cycle: 83*4882a593Smuzhiyun t_rd_cycle, t_cez_r, t_oez 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun4. read async non-muxed 86*4882a593Smuzhiyun 87*4882a593Smuzhiyunadv_rd_off: 88*4882a593Smuzhiyun t_avdp_r 89*4882a593Smuzhiyunoe_on: 90*4882a593Smuzhiyun t_oeasu 91*4882a593Smuzhiyunaccess: 92*4882a593Smuzhiyun t_iaa, t_oe, t_ce, t_aa 93*4882a593Smuzhiyunrd_cycle: 94*4882a593Smuzhiyun t_rd_cycle, t_cez_r, t_oez 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun5. read sync muxed 97*4882a593Smuzhiyun 98*4882a593Smuzhiyunadv_rd_off: 99*4882a593Smuzhiyun t_avdp_r, t_avdh 100*4882a593Smuzhiyunoe_on: 101*4882a593Smuzhiyun t_oeasu, t_ach, cyc_aavdh_oe 102*4882a593Smuzhiyunaccess: 103*4882a593Smuzhiyun t_iaa, cyc_iaa, cyc_oe 104*4882a593Smuzhiyunrd_cycle: 105*4882a593Smuzhiyun t_cez_r, t_oez, t_ce_rdyz 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun6. read sync non-muxed 108*4882a593Smuzhiyun 109*4882a593Smuzhiyunadv_rd_off: 110*4882a593Smuzhiyun t_avdp_r 111*4882a593Smuzhiyunoe_on: 112*4882a593Smuzhiyun t_oeasu 113*4882a593Smuzhiyunaccess: 114*4882a593Smuzhiyun t_iaa, cyc_iaa, cyc_oe 115*4882a593Smuzhiyunrd_cycle: 116*4882a593Smuzhiyun t_cez_r, t_oez, t_ce_rdyz 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun7. write async muxed 119*4882a593Smuzhiyun 120*4882a593Smuzhiyunadv_wr_off: 121*4882a593Smuzhiyun t_avdp_w 122*4882a593Smuzhiyunwe_on, wr_data_mux_bus: 123*4882a593Smuzhiyun t_weasu, t_aavdh, cyc_aavhd_we 124*4882a593Smuzhiyunwe_off: 125*4882a593Smuzhiyun t_wpl 126*4882a593Smuzhiyuncs_wr_off: 127*4882a593Smuzhiyun t_wph 128*4882a593Smuzhiyunwr_cycle: 129*4882a593Smuzhiyun t_cez_w, t_wr_cycle 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun8. write async non-muxed 132*4882a593Smuzhiyun 133*4882a593Smuzhiyunadv_wr_off: 134*4882a593Smuzhiyun t_avdp_w 135*4882a593Smuzhiyunwe_on, wr_data_mux_bus: 136*4882a593Smuzhiyun t_weasu 137*4882a593Smuzhiyunwe_off: 138*4882a593Smuzhiyun t_wpl 139*4882a593Smuzhiyuncs_wr_off: 140*4882a593Smuzhiyun t_wph 141*4882a593Smuzhiyunwr_cycle: 142*4882a593Smuzhiyun t_cez_w, t_wr_cycle 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun9. write sync muxed 145*4882a593Smuzhiyun 146*4882a593Smuzhiyunadv_wr_off: 147*4882a593Smuzhiyun t_avdp_w, t_avdh 148*4882a593Smuzhiyunwe_on, wr_data_mux_bus: 149*4882a593Smuzhiyun t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we 150*4882a593Smuzhiyunwe_off: 151*4882a593Smuzhiyun t_wpl, cyc_wpl 152*4882a593Smuzhiyuncs_wr_off: 153*4882a593Smuzhiyun t_wph 154*4882a593Smuzhiyunwr_cycle: 155*4882a593Smuzhiyun t_cez_w, t_ce_rdyz 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun10. write sync non-muxed 158*4882a593Smuzhiyun 159*4882a593Smuzhiyunadv_wr_off: 160*4882a593Smuzhiyun t_avdp_w 161*4882a593Smuzhiyunwe_on, wr_data_mux_bus: 162*4882a593Smuzhiyun t_weasu, t_rdyo 163*4882a593Smuzhiyunwe_off: 164*4882a593Smuzhiyun t_wpl, cyc_wpl 165*4882a593Smuzhiyuncs_wr_off: 166*4882a593Smuzhiyun t_wph 167*4882a593Smuzhiyunwr_cycle: 168*4882a593Smuzhiyun t_cez_w, t_ce_rdyz 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun 171*4882a593SmuzhiyunNote: 172*4882a593Smuzhiyun Many of gpmc timings are dependent on other gpmc timings (a few 173*4882a593Smuzhiyun gpmc timings purely dependent on other gpmc timings, a reason that 174*4882a593Smuzhiyun some of the gpmc timings are missing above), and it will result in 175*4882a593Smuzhiyun indirect dependency of peripheral timings to gpmc timings other than 176*4882a593Smuzhiyun mentioned above, refer timing routine for more details. To know what 177*4882a593Smuzhiyun these peripheral timings correspond to, please see explanations in 178*4882a593Smuzhiyun struct gpmc_device_timings definition. And for gpmc timings refer 179*4882a593Smuzhiyun IP details (link above). 180