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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
17 dt-bindings/clock/qcom,dispcc-sm8150.h
18 dt-bindings/clock/qcom,dispcc-sm8250.h
23 - qcom,sm8150-dispcc
24 - qcom,sm8250-dispcc
28 - description: Board XO source
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H A Dqcom,sdm845-dispcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,dispcc-sdm845.h.
20 const: qcom,sdm845-dispcc
27 - description: Board XO source
28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
[all …]
/OK3568_Linux_fs/buildroot/board/avnet/s6lx9_microboard/
H A Dlx9_mmu.dts4 * (C) Copyright 2007-2008 Xilinx, Inc.
5 * (C) Copyright 2007-2009 Michal Simek
22 * MA 02111-1307 USA
27 * XPS project directory: device-tree_bsp_230-orig
30 /dts-v1/;
32 #address-cells = <1>;
33 #size-cells = <1>;
46 linux,stdout-path = "/axi@0/serial@40600000";
49 #address-cells = <1>;
51 #size-cells = <0>;
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
29 compatible = "gpio-keys";
31 power-button {
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
42 gpio-keys {
43 compatible = "gpio-keys";
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dzynqmp-zcu102-revA.dts8 * SPDX-License-Identifier: GPL-2.0+
11 /dts-v1/;
14 #include "zynqmp-clk.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
37 stdout-path = "serial0:115200n8";
45 gpio-keys {
46 compatible = "gpio-keys";
47 #address-cells = <1>;
48 #size-cells = <0>;
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H A D.rk3288-phycore-rdk.dtb.dts.tmp
H A Drk3288.dtsi2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3288-cru.h>
10 #include <dt-bindings/power-domain/rk3288.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include <dt-bindings/video/rk3288.h>
18 interrupt-parent = <&gic>;
[all …]
H A D.rk3288-vyasa.dtb.dts.tmp
H A D.rk3288-rock2-square.dtb.dts.tmp
H A D.rk3288-popmetal.dtb.dts.tmp
H A D.rk3288-tinker.dtb.dts.tmp
H A D.rk3288-evb.dtb.dts.tmp
H A D.rk3288-fennec.dtb.dts.tmp
H A D.rk3288-firefly.dtb.dts.tmp
H A D.rk3288-miqi.dtb.dts.tmp
H A D.rk3288-veyron-mickey.dtb.dts.tmp
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
33 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
39 * IOSF-SB port.
43 * logic. CH0 common lane also contains the IOSF-SB logic for the
53 * each spline is made up of one Physical Access Coding Sub-Layer
55 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
59 * for each channel. This is used for DP AUX communication, but
97 * ---------------------------------
100 * |---------------|---------------| Display PHY
102 * |-------|-------|-------|-------|
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
46 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
108 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
191 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
196 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
266 /* HPD pin number (0 or 1) or -ENODEV */
292 return regmap_read_poll_timeout(tc->regmap, addr, val, in tc_poll_timeout()
310 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); in tc_aux_write_data()
322 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); in tc_aux_read_data()
333 u32 auxcfg0 = msg->request; in tc_auxcfg0()
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/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-usb2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
11 #include <linux/extcon-provider.h>
60 * enum usb_chg_state - Different states involved in USB charger detection.
100 * struct rockchip_chg_det_reg - usb charger detect registers
105 * @idp_sink_en: open dp sink current.
109 * @vdp_src_en: open dp voltage source.
126 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
209 * struct rockchip_usb2phy_cfg - usb-phy configuration.
210 * @reg: the address offset of grf for usb-phy config.
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/xlnx/
H A Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
27 #include <linux/dma-mapping.h>
43 * --------
45 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
48 * +------------------------------------------------------------+
49 * +--------+ | +----------------+ +-----------+ |
50 * | DPDMA | --->| | --> | Video | Video +-------------+ |
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_8852b_api.c3 * Copyright(c) 2007 - 2020 Realtek Corporation.
33 if (pw_ofst < -16 || pw_ofst > 15) { in halbb_set_pwr_ul_tb_ofst_8852b()
39 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD288, BIT31, 1); in halbb_set_pwr_ul_tb_ofst_8852b()
42 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD28c, 0x1f, pw_ofst); in halbb_set_pwr_ul_tb_ofst_8852b()
45 if (pw_ofst < -13) in halbb_set_pwr_ul_tb_ofst_8852b()
46 pw_ofst = -13; in halbb_set_pwr_ul_tb_ofst_8852b()
47 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD290, 0x1f, pw_ofst - 3); in halbb_set_pwr_ul_tb_ofst_8852b()
56 /*0:0dB 1:-4dB 2:-5dB 3:-6dB*/ in halbb_tx_triangular_shap_cfg_8852b()
142 rtw_hal_rf_tssi_scan_ch(bb->hal_com, HW_PHY_0, path); in halbb_tssi_cont_en_8852b()
151 //Protest SW-SI in halbb_bb_reset_all_8852b()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_8852b_api.c3 * Copyright(c) 2007 - 2020 Realtek Corporation.
33 if (pw_ofst < -16 || pw_ofst > 15) { in halbb_set_pwr_ul_tb_ofst_8852b()
39 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD288, BIT31, 1); in halbb_set_pwr_ul_tb_ofst_8852b()
42 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD28c, 0x1f, pw_ofst); in halbb_set_pwr_ul_tb_ofst_8852b()
45 if (pw_ofst < -13) in halbb_set_pwr_ul_tb_ofst_8852b()
46 pw_ofst = -13; in halbb_set_pwr_ul_tb_ofst_8852b()
47 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD290, 0x1f, pw_ofst - 3); in halbb_set_pwr_ul_tb_ofst_8852b()
56 /*0:0dB 1:-4dB 2:-5dB 3:-6dB*/ in halbb_tx_triangular_shap_cfg_8852b()
142 rtw_hal_rf_tssi_scan_ch(bb->hal_com, HW_PHY_0, path); in halbb_tssi_cont_en_8852b()
151 //Protest SW-SI in halbb_bb_reset_all_8852b()
[all …]
/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-inno-usb2.c4 * SPDX-License-Identifier: GPL-2.0+
10 #include <generic-phy.h>
18 #include <reset-uclass.h>
36 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */
59 * @idp_sink_en: open dp sink current.
63 * @vdp_src_en: open dp voltage source.
80 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
129 * struct rockchip_usb2phy_cfg: usb-phy configuration.
130 * @reg: the address offset of grf for usb-phy config.
169 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; in get_reg_base()
[all …]

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