Lines Matching +full:dp +full:- +full:phy0
8 * SPDX-License-Identifier: GPL-2.0+
11 /dts-v1/;
14 #include "zynqmp-clk.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
37 stdout-path = "serial0:115200n8";
45 gpio-keys {
46 compatible = "gpio-keys";
47 #address-cells = <1>;
48 #size-cells = <0>;
54 gpio-key,wakeup;
60 compatible = "gpio-leds";
64 linux,default-trigger = "heartbeat";
80 xlnx,include-sg; /* for testing purpose */
83 xlnx,src-issue = <31>;
89 xlnx,src-issue = <4>; /* for testing purpose */
98 xlnx,include-sg; /* for testing purpose */
107 xlnx,include-sg; /* for testing purpose */
116 xlnx,include-sg; /* for testing purpose */
121 local-mac-address = [00 0a 35 00 02 90];
122 phy-handle = <&phy0>;
123 phy-mode = "rgmii-id";
124 phy0: phy@21 { label
126 ti,rx-internal-delay = <0x8>;
127 ti,tx-internal-delay = <0xa>;
128 ti,fifo-depth = <0x1>;
142 clock-frequency = <400000>;
146 * Enable all GTs to out from U-Boot
147 * i2c mw 20 6 0 - setup IO to output
148 * i2c mw 20 2 ef - setup output values on pins 0-7
149 * i2c mw 20 3 ff - setup output values on pins 10-17
153 gpio-controller;
154 #gpio-cells = <2>;
158 * 0 - PS_GTR_LAN_SEL0
159 * 1 - PS_GTR_LAN_SEL1
160 * 2 - PS_GTR_LAN_SEL2
161 * 3 - PS_GTR_LAN_SEL3
162 * 4 - PCI_CLK_DIR_SEL
163 * 5 - IIC_MUX_RESET_B
164 * 6 - GEM3_EXP_RESET_B
165 * 7, 10 - 17 - not connected
169 gpio-hog;
171 output-high; /* PCIE = 0, DP = 1 */
172 line-name = "sel0";
175 gpio-hog;
177 output-high; /* PCIE = 0, DP = 1 */
178 line-name = "sel1";
181 gpio-hog;
183 output-high; /* PCIE = 0, USB0 = 1 */
184 line-name = "sel2";
187 gpio-hog;
189 output-high; /* PCIE = 0, SATA = 1 */
190 line-name = "sel3";
197 gpio-controller;
198 #gpio-cells = <2>;
202 * 0 - VCCPSPLL_EN
203 * 1 - MGTRAVCC_EN
204 * 2 - MGTRAVTT_EN
205 * 3 - VCCPSDDRPLL_EN
206 * 4 - MIO26_PMU_INPUT_LS
207 * 5 - PL_PMBUS_ALERT
208 * 6 - PS_PMBUS_ALERT
209 * 7 - MAXIM_PMBUS_ALERT
210 * 10 - PL_DDR4_VTERM_EN
211 * 11 - PL_DDR4_VPP_2V5_EN
212 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
213 * 13 - PS_DIMM_SUSPEND_EN
214 * 14 - PS_DDR4_VTERM_EN
215 * 15 - PS_DDR4_VPP_2V5_EN
216 * 16 - 17 - not connected
222 #address-cells = <1>;
223 #size-cells = <0>;
226 #address-cells = <1>;
227 #size-cells = <0>;
233 shunt-resistor = <5000>;
238 shunt-resistor = <5000>;
243 shunt-resistor = <5000>;
248 shunt-resistor = <5000>;
253 shunt-resistor = <5000>;
258 shunt-resistor = <5000>;
263 shunt-resistor = <5000>;
268 shunt-resistor = <5000>;
273 shunt-resistor = <5000>;
278 shunt-resistor = <5000>;
282 #address-cells = <1>;
283 #size-cells = <0>;
289 shunt-resistor = <2000>;
294 shunt-resistor = <5000>;
299 shunt-resistor = <5000>;
304 shunt-resistor = <5000>;
309 shunt-resistor = <5000>;
314 shunt-resistor = <5000>;
319 shunt-resistor = <5000>;
324 shunt-resistor = <5000>;
328 #address-cells = <1>;
329 #size-cells = <0>;
331 /* MAXIM_PMBUS - 00 */
383 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
385 max20751@72 { /* u95 FIXME - not detected */
389 max20751@73 { /* u96 FIXME - not detected */
397 /* FIXME PMOD - j160 */
398 /* FIXME MSP430F - u41 - not detected */
403 clock-frequency = <400000>;
404 /* FIXME PL i2c via PCA9306 - u45 */
405 /* FIXME MSP430 - u41 - not detected */
408 #address-cells = <1>;
409 #size-cells = <0>;
412 #address-cells = <1>;
413 #size-cells = <0>;
418 * 0 - 256B address 0x54
419 * 256B - 512B address 0x55
420 * 512B - 768B address 0x56
421 * 768B - 1024B address 0x57
429 #address-cells = <1>;
430 #size-cells = <0>;
432 si5341: clock-generator1@36 { /* SI5341 - u69 */
439 #address-cells = <1>;
440 #size-cells = <0>;
442 si570_1: clock-generator2@5d { /* USER SI570 - u42 */
443 #clock-cells = <0>;
446 temperature-stability = <50>;
447 factory-fout = <300000000>;
448 clock-frequency = <300000000>;
452 #address-cells = <1>;
453 #size-cells = <0>;
455 si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
456 #clock-cells = <0>;
459 temperature-stability = <50>; /* copy from zc702 */
460 factory-fout = <156250000>;
461 clock-frequency = <148500000>;
465 #address-cells = <1>;
466 #size-cells = <0>;
468 si5328: clock-generator4@69 {/* SI5328 - u20 */
473 /* 5 - 7 unconnected */
478 #address-cells = <1>;
479 #size-cells = <0>;
483 #address-cells = <1>;
484 #size-cells = <0>;
489 #address-cells = <1>;
490 #size-cells = <0>;
495 #address-cells = <1>;
496 #size-cells = <0>;
501 #address-cells = <1>;
502 #size-cells = <0>;
505 dev@19 { /* u-boot detection */
509 dev@30 { /* u-boot detection */
513 dev@35 { /* u-boot detection */
517 dev@36 { /* u-boot detection */
521 dev@51 { /* u-boot detection - maybe SPD */
527 #address-cells = <1>;
528 #size-cells = <0>;
533 #address-cells = <1>;
534 #size-cells = <0>;
539 #address-cells = <1>;
540 #size-cells = <0>;
545 #address-cells = <1>;
546 #size-cells = <0>;
559 is-dual = <1>;
562 #address-cells = <1>;
563 #size-cells = <1>;
565 spi-tx-bus-width = <1>;
566 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
567 spi-max-frequency = <108000000>; /* Based on DC1 spec */
568 partition@qspi-fsbl-uboot { /* for testing purpose */
569 label = "qspi-fsbl-uboot";
572 partition@qspi-linux { /* for testing purpose */
573 label = "qspi-linux";
576 partition@qspi-device-tree { /* for testing purpose */
577 label = "qspi-device-tree";
580 partition@qspi-rootfs { /* for testing purpose */
581 label = "qspi-rootfs";
594 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
595 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
596 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
597 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
598 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
599 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
600 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
601 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
607 no-1-8-v; /* for 1.0 silicon */
640 xlnx,vid-clk-pl;