Lines Matching +full:dp +full:- +full:phy0
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <generic-phy.h>
18 #include <reset-uclass.h>
36 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */
59 * @idp_sink_en: open dp sink current.
63 * @vdp_src_en: open dp voltage source.
80 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
129 * struct rockchip_usb2phy_cfg: usb-phy configuration.
130 * @reg: the address offset of grf for usb-phy config.
169 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; in get_reg_base()
177 tmp = en ? reg->enable : reg->disable; in property_enable()
178 mask = GENMASK(reg->bitend, reg->bitstart); in property_enable()
179 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); in property_enable()
181 return regmap_write(base, reg->offset, val); in property_enable()
188 u32 mask = GENMASK(reg->bitend, reg->bitstart); in property_enabled()
190 regmap_read(base, reg->offset, &orig); in property_enabled()
192 tmp = (orig & mask) >> reg->bitstart; in property_enabled()
194 return tmp == reg->enable; in property_enabled()
218 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); in rockchip_chg_enable_dcd()
219 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); in rockchip_chg_enable_dcd()
227 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); in rockchip_chg_enable_primary_det()
228 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); in rockchip_chg_enable_primary_det()
236 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); in rockchip_chg_enable_secondary_det()
237 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); in rockchip_chg_enable_secondary_det()
245 while (rphy->primary_retries--) { in rockchip_chg_primary_det_retry()
246 /* voltage source on DP, probe on DM */ in rockchip_chg_primary_det_retry()
249 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); in rockchip_chg_primary_det_retry()
268 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); in rockchip_chg_get_type()
269 if (ret == -ENODEV) { in rockchip_chg_get_type()
279 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in rockchip_chg_get_type()
281 /* Check USB-Vbus status first */ in rockchip_chg_get_type()
282 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { in rockchip_chg_get_type()
292 /* Suspend USB-PHY and put the controller in non-driving mode */ in rockchip_chg_get_type()
293 property_enable(base, &port_cfg->phy_sus, true); in rockchip_chg_get_type()
294 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); in rockchip_chg_get_type()
296 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; in rockchip_chg_get_type()
297 rphy->primary_retries = CHG_PRI_MAX_RETRIES; in rockchip_chg_get_type()
302 while (rphy->dcd_retries--) { in rockchip_chg_get_type()
306 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); in rockchip_chg_get_type()
308 if (is_dcd || !rphy->dcd_retries) { in rockchip_chg_get_type()
311 * voltage source on DP, probe on DM. in rockchip_chg_get_type()
320 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); in rockchip_chg_get_type()
323 /* stage 3, voltage source on DM, probe on DP */ in rockchip_chg_get_type()
326 if (!rphy->dcd_retries) { in rockchip_chg_get_type()
337 /* stage 3, voltage source on DM, probe on DP */ in rockchip_chg_get_type()
348 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); in rockchip_chg_get_type()
357 /* Resume USB-PHY and put the controller in normal mode */ in rockchip_chg_get_type()
358 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); in rockchip_chg_get_type()
359 property_enable(base, &port_cfg->phy_sus, false); in rockchip_chg_get_type()
384 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); in otg_phy_init()
385 if (ret == -ENODEV) { in otg_phy_init()
395 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in otg_phy_init()
397 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ in otg_phy_init()
398 if(rphy->phy_cfg->clkout_ctl.disable) in otg_phy_init()
399 property_enable(base, &rphy->phy_cfg->clkout_ctl, true); in otg_phy_init()
401 /* Reset USB-PHY */ in otg_phy_init()
402 property_enable(base, &port_cfg->phy_sus, true); in otg_phy_init()
404 property_enable(base, &port_cfg->phy_sus, false); in otg_phy_init()
412 if (rphy->phy_rst.dev) { in rockchip_usb2phy_reset()
413 ret = reset_assert(&rphy->phy_rst); in rockchip_usb2phy_reset()
421 ret = reset_deassert(&rphy->phy_rst); in rockchip_usb2phy_reset()
435 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_init()
440 if (phy->id == USB2PHY_PORT_OTG) { in rockchip_usb2phy_init()
441 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in rockchip_usb2phy_init()
442 } else if (phy->id == USB2PHY_PORT_HOST) { in rockchip_usb2phy_init()
443 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; in rockchip_usb2phy_init()
445 dev_err(phy->dev, "phy id %lu not support", phy->id); in rockchip_usb2phy_init()
446 return -EINVAL; in rockchip_usb2phy_init()
449 property_enable(base, &port_cfg->phy_sus, false); in rockchip_usb2phy_init()
459 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_exit()
464 if (phy->id == USB2PHY_PORT_OTG) { in rockchip_usb2phy_exit()
465 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in rockchip_usb2phy_exit()
466 } else if (phy->id == USB2PHY_PORT_HOST) { in rockchip_usb2phy_exit()
467 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; in rockchip_usb2phy_exit()
469 dev_err(phy->dev, "phy id %lu not support", phy->id); in rockchip_usb2phy_exit()
470 return -EINVAL; in rockchip_usb2phy_exit()
473 property_enable(base, &port_cfg->phy_sus, true); in rockchip_usb2phy_exit()
480 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_power_on()
482 struct udevice *vbus = rphy->vbus_supply[phy->id]; in rockchip_usb2phy_power_on()
498 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_power_off()
500 struct udevice *vbus = rphy->vbus_supply[phy->id]; in rockchip_usb2phy_power_off()
517 const char *dev_name = phy->dev->name; in rockchip_usb2phy_of_xlate()
518 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_of_xlate()
521 if (!strcasecmp(dev_name, "host-port")) { in rockchip_usb2phy_of_xlate()
522 phy->id = USB2PHY_PORT_HOST; in rockchip_usb2phy_of_xlate()
523 device_get_supply_regulator(phy->dev, "phy-supply", in rockchip_usb2phy_of_xlate()
524 &rphy->vbus_supply[USB2PHY_PORT_HOST]); in rockchip_usb2phy_of_xlate()
525 } else if (!strcasecmp(dev_name, "otg-port")) { in rockchip_usb2phy_of_xlate()
526 phy->id = USB2PHY_PORT_OTG; in rockchip_usb2phy_of_xlate()
527 device_get_supply_regulator(phy->dev, "phy-supply", in rockchip_usb2phy_of_xlate()
528 &rphy->vbus_supply[USB2PHY_PORT_OTG]); in rockchip_usb2phy_of_xlate()
529 if (!rphy->vbus_supply[USB2PHY_PORT_OTG]) in rockchip_usb2phy_of_xlate()
530 device_get_supply_regulator(phy->dev, "vbus-supply", in rockchip_usb2phy_of_xlate()
531 &rphy->vbus_supply[USB2PHY_PORT_OTG]); in rockchip_usb2phy_of_xlate()
534 return -EINVAL; in rockchip_usb2phy_of_xlate()
549 debug("%s: %s subnode not found", __func__, dev->name); in rockchip_usb2phy_bind()
550 return -ENXIO; in rockchip_usb2phy_bind()
572 struct udevice *parent = dev->parent; in rockchip_usb2phy_probe()
578 rphy->phy_base = (void __iomem *)dev_read_addr(dev); in rockchip_usb2phy_probe()
579 if (IS_ERR(rphy->phy_base)) { in rockchip_usb2phy_probe()
583 if (!strncmp(parent->name, "root_driver", 11) && in rockchip_usb2phy_probe()
592 rphy->grf_base = syscon_get_regmap(syscon); in rockchip_usb2phy_probe()
594 rphy->grf_base = syscon_get_regmap(parent); in rockchip_usb2phy_probe()
597 if (rphy->grf_base <= 0) { in rockchip_usb2phy_probe()
599 return -EINVAL; in rockchip_usb2phy_probe()
610 rphy->usbgrf_base = syscon_get_regmap(syscon); in rockchip_usb2phy_probe()
611 if (rphy->usbgrf_base <= 0) { in rockchip_usb2phy_probe()
613 return -EINVAL; in rockchip_usb2phy_probe()
616 rphy->usbgrf_base = NULL; in rockchip_usb2phy_probe()
619 if (!strncmp(parent->name, "root_driver", 11)) { in rockchip_usb2phy_probe()
628 return -EINVAL; in rockchip_usb2phy_probe()
631 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst); in rockchip_usb2phy_probe()
639 return -EINVAL; in rockchip_usb2phy_probe()
646 rphy->phy_cfg = &phy_cfgs[index]; in rockchip_usb2phy_probe()
652 if (!rphy->phy_cfg) { in rockchip_usb2phy_probe()
653 dev_err(dev, "no phy-config can be matched\n"); in rockchip_usb2phy_probe()
654 return -EINVAL; in rockchip_usb2phy_probe()
657 if (rphy->phy_cfg->phy_tuning) in rockchip_usb2phy_probe()
658 rphy->phy_cfg->phy_tuning(rphy); in rockchip_usb2phy_probe()
668 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ in rk322x_usb2phy_tuning()
669 if (rphy->phy_cfg->reg == 0x760) in rk322x_usb2phy_tuning()
682 /* Enable otg/host port pre-emphasis during non-chirp phase */ in rk3308_usb2phy_tuning()
711 /* Enable host port pre-emphasis during non-chirp phase */ in rk3308_usb2phy_tuning()
751 /* Enable otg/host port pre-emphasis during non-chirp phase */ in rk3328_usb2phy_tuning()
780 /* Enable host port pre-emphasis during non-chirp phase */ in rk3328_usb2phy_tuning()
818 reg = readl(rphy->phy_base + 0x70); in rv1106_usb2phy_tuning()
819 writel(reg | BIT(2), rphy->phy_base + 0x70); in rv1106_usb2phy_tuning()
829 if (IS_ERR(rphy->phy_base)) { in rk3528_usb2phy_tuning()
830 return PTR_ERR(rphy->phy_base); in rk3528_usb2phy_tuning()
834 reg = readl(rphy->phy_base + 0x30); in rk3528_usb2phy_tuning()
835 writel(reg & ~BIT(2), rphy->phy_base + 0x30); in rk3528_usb2phy_tuning()
838 reg = readl(rphy->phy_base + 0x0430); in rk3528_usb2phy_tuning()
839 writel(reg & ~BIT(2), rphy->phy_base + 0x0430); in rk3528_usb2phy_tuning()
842 reg = readl(rphy->phy_base + 0x30); in rk3528_usb2phy_tuning()
845 writel(reg, rphy->phy_base + 0x30); in rk3528_usb2phy_tuning()
848 reg = readl(rphy->phy_base + 0x430); in rk3528_usb2phy_tuning()
851 writel(reg, rphy->phy_base + 0x430); in rk3528_usb2phy_tuning()
854 reg = readl(rphy->phy_base + 0x94); in rk3528_usb2phy_tuning()
857 writel(reg, rphy->phy_base + 0x94); in rk3528_usb2phy_tuning()
860 reg = readl(rphy->phy_base + 0x41c); in rk3528_usb2phy_tuning()
863 writel(reg, rphy->phy_base + 0x41c); in rk3528_usb2phy_tuning()
873 if (IS_ERR(rphy->phy_base)) { in rk3562_usb2phy_tuning()
874 return PTR_ERR(rphy->phy_base); in rk3562_usb2phy_tuning()
878 reg = readl(rphy->phy_base + 0x30); in rk3562_usb2phy_tuning()
879 writel(reg & ~BIT(2), rphy->phy_base + 0x30); in rk3562_usb2phy_tuning()
881 reg = readl(rphy->phy_base + 0x0430); in rk3562_usb2phy_tuning()
882 writel(reg & ~BIT(2), rphy->phy_base + 0x0430); in rk3562_usb2phy_tuning()
884 /* Enable pre-emphasis during non-chirp phase */ in rk3562_usb2phy_tuning()
885 reg = readl(rphy->phy_base); in rk3562_usb2phy_tuning()
888 writel(reg, rphy->phy_base); in rk3562_usb2phy_tuning()
890 reg = readl(rphy->phy_base + 0x0400); in rk3562_usb2phy_tuning()
893 writel(reg, rphy->phy_base + 0x0400); in rk3562_usb2phy_tuning()
896 reg = readl(rphy->phy_base + 0x0030); in rk3562_usb2phy_tuning()
899 writel(reg, rphy->phy_base + 0x0030); in rk3562_usb2phy_tuning()
901 reg = readl(rphy->phy_base + 0x0430); in rk3562_usb2phy_tuning()
904 writel(reg, rphy->phy_base + 0x0430); in rk3562_usb2phy_tuning()
929 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ in rk3588_usb2phy_tuning()
1748 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs },
1751 { .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs },
1754 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs },
1757 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs },
1760 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs },
1763 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs },
1766 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs },
1769 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs },
1772 { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs },
1775 { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs },
1778 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs },
1781 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs },
1784 { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs },
1787 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs },