1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Jonathan Marek <jonathan@marek.ca> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Qualcomm display clock control module which supports the clocks, resets and 14*4882a593Smuzhiyun power domains on SM8150 and SM8250. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun See also: 17*4882a593Smuzhiyun dt-bindings/clock/qcom,dispcc-sm8150.h 18*4882a593Smuzhiyun dt-bindings/clock/qcom,dispcc-sm8250.h 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun enum: 23*4882a593Smuzhiyun - qcom,sm8150-dispcc 24*4882a593Smuzhiyun - qcom,sm8250-dispcc 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clocks: 27*4882a593Smuzhiyun items: 28*4882a593Smuzhiyun - description: Board XO source 29*4882a593Smuzhiyun - description: Byte clock from DSI PHY0 30*4882a593Smuzhiyun - description: Pixel clock from DSI PHY0 31*4882a593Smuzhiyun - description: Byte clock from DSI PHY1 32*4882a593Smuzhiyun - description: Pixel clock from DSI PHY1 33*4882a593Smuzhiyun - description: Link clock from DP PHY 34*4882a593Smuzhiyun - description: VCO DIV clock from DP PHY 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clock-names: 37*4882a593Smuzhiyun items: 38*4882a593Smuzhiyun - const: bi_tcxo 39*4882a593Smuzhiyun - const: dsi0_phy_pll_out_byteclk 40*4882a593Smuzhiyun - const: dsi0_phy_pll_out_dsiclk 41*4882a593Smuzhiyun - const: dsi1_phy_pll_out_byteclk 42*4882a593Smuzhiyun - const: dsi1_phy_pll_out_dsiclk 43*4882a593Smuzhiyun - const: dp_phy_pll_link_clk 44*4882a593Smuzhiyun - const: dp_phy_pll_vco_div_clk 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun '#clock-cells': 47*4882a593Smuzhiyun const: 1 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun '#reset-cells': 50*4882a593Smuzhiyun const: 1 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun '#power-domain-cells': 53*4882a593Smuzhiyun const: 1 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun reg: 56*4882a593Smuzhiyun maxItems: 1 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunrequired: 59*4882a593Smuzhiyun - compatible 60*4882a593Smuzhiyun - reg 61*4882a593Smuzhiyun - clocks 62*4882a593Smuzhiyun - clock-names 63*4882a593Smuzhiyun - '#clock-cells' 64*4882a593Smuzhiyun - '#reset-cells' 65*4882a593Smuzhiyun - '#power-domain-cells' 66*4882a593Smuzhiyun 67*4882a593SmuzhiyunadditionalProperties: false 68*4882a593Smuzhiyun 69*4882a593Smuzhiyunexamples: 70*4882a593Smuzhiyun - | 71*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,rpmh.h> 72*4882a593Smuzhiyun clock-controller@af00000 { 73*4882a593Smuzhiyun compatible = "qcom,sm8250-dispcc"; 74*4882a593Smuzhiyun reg = <0x0af00000 0x10000>; 75*4882a593Smuzhiyun clocks = <&rpmhcc RPMH_CXO_CLK>, 76*4882a593Smuzhiyun <&dsi0_phy 0>, 77*4882a593Smuzhiyun <&dsi0_phy 1>, 78*4882a593Smuzhiyun <&dsi1_phy 0>, 79*4882a593Smuzhiyun <&dsi1_phy 1>, 80*4882a593Smuzhiyun <&dp_phy 0>, 81*4882a593Smuzhiyun <&dp_phy 1>; 82*4882a593Smuzhiyun clock-names = "bi_tcxo", 83*4882a593Smuzhiyun "dsi0_phy_pll_out_byteclk", 84*4882a593Smuzhiyun "dsi0_phy_pll_out_dsiclk", 85*4882a593Smuzhiyun "dsi1_phy_pll_out_byteclk", 86*4882a593Smuzhiyun "dsi1_phy_pll_out_dsiclk", 87*4882a593Smuzhiyun "dp_phy_pll_link_clk", 88*4882a593Smuzhiyun "dp_phy_pll_vco_div_clk"; 89*4882a593Smuzhiyun #clock-cells = <1>; 90*4882a593Smuzhiyun #reset-cells = <1>; 91*4882a593Smuzhiyun #power-domain-cells = <1>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun... 94