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Searched refs:u32Int (Results 1 – 13 of 13) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/
H A DhalHDMITx.c621 void MHal_HDMITx_Int_Disable(MS_U32 u32Int) in MHal_HDMITx_Int_Disable() argument
625 … MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int); in MHal_HDMITx_Int_Disable()
627 …_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) ); in MHal_HDMITx_Int_Disable()
633 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank in MHal_HDMITx_Int_Disable()
646 void MHal_HDMITx_Int_Enable(MS_U32 u32Int) in MHal_HDMITx_Int_Enable() argument
650 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int); in MHal_HDMITx_Int_Enable()
652 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
658 if(u32Int & E_HDMITX_IRQ_12) in MHal_HDMITx_Int_Enable()
672 void MHal_HDMITx_Int_Clear(MS_U32 u32Int) in MHal_HDMITx_Int_Clear() argument
676 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int); in MHal_HDMITx_Int_Clear()
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/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/
H A DhalHDMITx.c644 void MHal_HDMITx_Int_Disable(MS_U32 u32Int) in MHal_HDMITx_Int_Disable() argument
648 … MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int); in MHal_HDMITx_Int_Disable()
650 …_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) ); in MHal_HDMITx_Int_Disable()
656 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank in MHal_HDMITx_Int_Disable()
669 void MHal_HDMITx_Int_Enable(MS_U32 u32Int) in MHal_HDMITx_Int_Enable() argument
673 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int); in MHal_HDMITx_Int_Enable()
675 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
681 if(u32Int & E_HDMITX_IRQ_12) in MHal_HDMITx_Int_Enable()
695 void MHal_HDMITx_Int_Clear(MS_U32 u32Int) in MHal_HDMITx_Int_Clear() argument
699 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int); in MHal_HDMITx_Int_Clear()
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/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/
H A DhalHDMITx.c670 void MHal_HDMITx_Int_Disable(MS_U32 u32Int) in MHal_HDMITx_Int_Disable() argument
674 … MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int); in MHal_HDMITx_Int_Disable()
676 …_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) ); in MHal_HDMITx_Int_Disable()
682 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank in MHal_HDMITx_Int_Disable()
695 void MHal_HDMITx_Int_Enable(MS_U32 u32Int) in MHal_HDMITx_Int_Enable() argument
699 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int); in MHal_HDMITx_Int_Enable()
701 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
707 if(u32Int & E_HDMITX_IRQ_12) in MHal_HDMITx_Int_Enable()
721 void MHal_HDMITx_Int_Clear(MS_U32 u32Int) in MHal_HDMITx_Int_Clear() argument
725 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int); in MHal_HDMITx_Int_Clear()
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/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/
H A DhalHDMITx.c658 void MHal_HDMITx_Int_Disable(MS_U32 u32Int) in MHal_HDMITx_Int_Disable() argument
662 … MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int); in MHal_HDMITx_Int_Disable()
664 …_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) ); in MHal_HDMITx_Int_Disable()
670 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank in MHal_HDMITx_Int_Disable()
683 void MHal_HDMITx_Int_Enable(MS_U32 u32Int) in MHal_HDMITx_Int_Enable() argument
687 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int); in MHal_HDMITx_Int_Enable()
689 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
695 if(u32Int & E_HDMITX_IRQ_12) in MHal_HDMITx_Int_Enable()
709 void MHal_HDMITx_Int_Clear(MS_U32 u32Int) in MHal_HDMITx_Int_Clear() argument
713 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int); in MHal_HDMITx_Int_Clear()
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/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/
H A DhalHDMITx.c792 void MHal_HDMITx_Int_Disable(MS_U32 u32Int) in MHal_HDMITx_Int_Disable() argument
796 … MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int); in MHal_HDMITx_Int_Disable()
798 …_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) ); in MHal_HDMITx_Int_Disable()
804 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank in MHal_HDMITx_Int_Disable()
817 void MHal_HDMITx_Int_Enable(MS_U32 u32Int) in MHal_HDMITx_Int_Enable() argument
821 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int); in MHal_HDMITx_Int_Enable()
823 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
829 if(u32Int & E_HDMITX_IRQ_12) in MHal_HDMITx_Int_Enable()
843 void MHal_HDMITx_Int_Clear(MS_U32 u32Int) in MHal_HDMITx_Int_Clear() argument
847 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int); in MHal_HDMITx_Int_Clear()
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/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/
H A DhalHDMITx.c847 void MHal_HDMITx_Int_Disable(MS_U32 u32Int) in MHal_HDMITx_Int_Disable() argument
851 … MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int); in MHal_HDMITx_Int_Disable()
853 …_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) ); in MHal_HDMITx_Int_Disable()
859 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank in MHal_HDMITx_Int_Disable()
872 void MHal_HDMITx_Int_Enable(MS_U32 u32Int) in MHal_HDMITx_Int_Enable() argument
876 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int); in MHal_HDMITx_Int_Enable()
878 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 ); in MHal_HDMITx_Int_Enable()
884 if(u32Int & E_HDMITX_IRQ_12) in MHal_HDMITx_Int_Enable()
898 void MHal_HDMITx_Int_Clear(MS_U32 u32Int) in MHal_HDMITx_Int_Clear() argument
902 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int); in MHal_HDMITx_Int_Clear()
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/utopia/UTPA2-700.0.x/modules/hdmi/drv/hdmitx/include/
H A DhalHDMITx.h652 INTERFACEE void MHal_HDMITx_Int_Disable(MS_U32 u32Int);
653 INTERFACEE void MHal_HDMITx_Int_Enable(MS_U32 u32Int);
654 INTERFACEE void MHal_HDMITx_Int_Clear(MS_U32 u32Int);
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/mmfi/
H A DhalMMFilein.c601 void HAL_MMFI_HWInt_Clear(MS_U32 u32Int) in HAL_MMFI_HWInt_Clear() argument
603 _HAL_REG32_W(&_MFCtrl_AU->SWRst_HWInt, (_HAL_REG32_R(&_MFCtrl_AU->SWRst_HWInt) & ~u32Int)); in HAL_MMFI_HWInt_Clear()
H A DhalMMFilein.h191 void HAL_MMFI_HWInt_Clear(MS_U32 u32Int);
/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/mmfi/
H A DhalMMFilein.c609 void HAL_MMFI_HWInt_Clear(MS_U32 u32Int) in HAL_MMFI_HWInt_Clear() argument
611 _HAL_REG32_W(&_MFCtrl_AU->SWRst_HWInt, (_HAL_REG32_R(&_MFCtrl_AU->SWRst_HWInt) & ~u32Int)); in HAL_MMFI_HWInt_Clear()
H A DhalMMFilein.h191 void HAL_MMFI_HWInt_Clear(MS_U32 u32Int);
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/mmfi/
H A DhalMMFilein.c609 void HAL_MMFI_HWInt_Clear(MS_U32 u32Int) in HAL_MMFI_HWInt_Clear() argument
611 _HAL_REG32_W(&_MFCtrl_AU->SWRst_HWInt, (_HAL_REG32_R(&_MFCtrl_AU->SWRst_HWInt) & ~u32Int)); in HAL_MMFI_HWInt_Clear()
H A DhalMMFilein.h191 void HAL_MMFI_HWInt_Clear(MS_U32 u32Int);