1 //<MStar Software>
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #define MHAL_HDMITX_C
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 // Common Definition
101 #ifdef MSOS_TYPE_LINUX_KERNEL
102 #include <linux/string.h>
103 #else
104 #include <string.h>
105 #endif
106
107 #include "MsCommon.h"
108
109 // Internal Definition
110 #include "regHDMITx.h"
111 #include "halHDMIUtilTx.h"
112 #include "halHDMITx.h"
113 #include "drvHDMITx.h"
114
115 // External Definition
116 #include "drvGPIO.h"
117 #include "drvSYS.h"
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126
127 #define GENERAL_PKT_NUM 0x0BU //wilson@kano
128 #define INFOFRM_PKT_NUM 0x08U //for HDR packet ID = 0x87; 0x06U //wilson@kano
129
130
131 #define HDMITX_VS_INFO_PKT_VER 0x01U
132 #define HDMITX_VS_INFO_PKT_LEN 0x1BU
133
134 #define HDMITX_AVI_INFO_PKT_VER 0x02U
135 #define HDMITX_AVI_INFO_PKT_LEN 0x0DU
136
137 #define HDMITX_SPD_INFO_PKT_VER 0x01U
138 #define HDMITX_SPD_INFO_PKT_LEN 0x19U
139
140 #define HDMITX_AUD_INFO_PKT_VER 0x01U
141 #define HDMITX_AUD_INFO_PKT_LEN 0x0AU
142
143 #define HDMITX_HDR_INFO_PKT_VER 0x01U
144 #define HDMITX_HDR_INFO_PKT_LEN 0x1BU //wilson@kano: temp solution
145
146
147
148 #define IS_STOP_PKT(_X_) ( (_X_ & E_HDMITX_STOP_PACKET) ? 1 : 0 )
149 #define IS_CYCLIC_PKT(_X_) ( (_X_ & E_HDMITX_CYCLIC_PACKET) ? 1 : 0 )
150
151 // HDMI packet cyclic frame count
152 #define HDMITX_PACKET_NULL_FCNT 0U ///< 0 ~ 31
153 #define HDMITX_PACKET_ACR_FCNT 0U ///< 0 ~ 15
154 #define HDMITX_PACKET_GC_FCNT 0U ///< 0 ~ 1
155 #define HDMITX_PACKET_ACP_FCNT 15U ///< 0 ~ 31
156 #define HDMITX_PACKET_ISRC_FCNT 15U ///< 0 ~ 31
157
158 #define HDMITX_PACKET_VS_FCNT 0U ///< 0 ~ 31
159 #define HDMITX_PACKET_AVI_FCNT 0U ///< 0 ~ 31
160 #define HDMITX_PACKET_SPD_FCNT 1U ///< 0 ~ 31
161 #define HDMITX_PACKET_AUD_FCNT 0U ///< 0 ~ 31
162 #define HDMITX_PACKET_HDR_FCNT 0U
163
164 #define HDMITX_PACKET_SPD_SDI 1U // Digital STB
165 #define HDMITX_CSC_SUPPORT_R2Y 1U
166 #define HDMITX_SUPPORT_P2I 1U
167 #define HDMITX_SUPPORT_444TO420 1U
168 #define HDMITX_MAX_PIXEL_CLK 597000000 //Max cupported pixel clock
169 //-------------------------------------------------------------------------------------------------
170 // Local Structures
171 //-------------------------------------------------------------------------------------------------
172
173 //*********************//
174 // Video //
175 //*********************//
176
177 typedef enum
178 {
179 E_HDMITX_VIDEO_INTERLACE_MODE = 0,
180 E_HDMITX_VIDEO_PROGRESSIVE_MODE = 1,
181 } MDrv_HDMITx_VIDEO_MODE;
182
183 typedef enum
184 {
185 E_HDMITX_VIDEO_POLARITY_HIGH = 0,
186 E_HDMITX_VIDEO_POLARITY_LOW = 1,
187 } MDrv_HDMITx_VIDEO_POLARITY;
188
189 typedef struct
190 {
191 MDrv_HDMITx_VIDEO_MODE i_p_mode; // interlace / progressive mode
192 MDrv_HDMITx_VIDEO_POLARITY h_polarity; // Hsync polarity
193 MDrv_HDMITx_VIDEO_POLARITY v_polarity; // Vsync polarity
194 MS_U16 vs_width; // Vsync pulse width
195 MS_U16 vs_bporch; // Vsync back-porch
196 MS_U16 vde_width; // Vde active width
197 MS_U16 vs_delayline; // Vsync line delay
198 MS_U16 vs_delaypixel; // Vsync pixel delay
199 MS_U16 hs_width; // Hsync pulse width
200 MS_U16 hs_bporch; // Hsync back-porch
201 MS_U16 hde_width; // Hde active width
202 MS_U16 hs_delay; // Hsync delay
203 MS_U16 vtotal; // Vsync total
204 MS_U16 htotal; // Hsync total
205 MS_U16 frame_rate; // Frame Rate
206 MS_U32 pixel_clk; //pixel clock
207 } MDrv_HDMITx_VIDEO_MODE_INFO_TYPE;
208
209 //*********************//
210 // Packet //
211 //*********************//
212
213 typedef enum
214 {
215 E_HDMITX_ACT_GCP_CMD = 0,
216 E_HDMITX_ACT_ACR_CMD = 1,
217 E_HDMITX_ACT_AVI_CMD = 2,
218 E_HDMITX_ACT_AUD_CMD = 3,
219 E_HDMITX_ACT_SPD_CMD = 4,
220 E_HDMITX_ACT_MPG_CMD = 5,
221 E_HDMITX_ACT_VSP_CMD = 6,
222 E_HDMITX_ACT_NUL_CMD = 7,
223 E_HDMITX_ACT_ACP_CMD = 8,
224 E_HDMITX_ACT_ISRC_CMD = 9,
225 E_HDMITX_ACT_GCP_DC_CMD = 10, // GCP with non-zero CD
226 E_HDMITX_ACT_GMP_CMD = 11, // Gamut Metadata packet
227 } MDrvHDMITX_PKTS_ACT_CMD;
228
229 typedef struct PKT
230 {
231 MS_BOOL User_Define;
232 MsHDMITX_PACKET_PROCESS Define_Process;
233 MS_U8 Define_FCnt;
234 }PKT_Behavior;
235 //*********************//
236 // Audio //
237 //*********************//
238 typedef struct
239 {
240 MS_U8 CH_Status3;
241 MS_U32 NcodeValue;
242 } MDrv_HDMITx_AUDIO_FREQ_TYPE;
243
244 //-------------------------------------------------------------------------------------------------
245 // Global Variables
246 //-------------------------------------------------------------------------------------------------
247 MS_U8 gDivider = 0x00;
248 MS_BOOL gDivFlag = FALSE;
249 static MS_U8 gu8ChipVerNum = 0x00;
250 MS_BOOL g_bSupportSCDC = FALSE;
251
252 stHDMITx_PKT_ATTRIBUTE gbGeneralPktList[GENERAL_PKT_NUM]; //wilson@kano
253 stHDMITx_PKT_ATTRIBUTE gbInfoFrmPktList[INFOFRM_PKT_NUM]; //wilson@kano
254
255 // User defined packet behavior
256 PKT_Behavior NULL_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
257 PKT_Behavior ACR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
258 PKT_Behavior AS_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
259 PKT_Behavior GC_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
260 PKT_Behavior ACP_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
261 PKT_Behavior ISRC1_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
262 PKT_Behavior ISRC2_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
263 PKT_Behavior DSD_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
264 PKT_Behavior HBR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
265 PKT_Behavior GM_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
266
267 PKT_Behavior VS_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
268 PKT_Behavior AVI_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
269 PKT_Behavior SPD_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
270 PKT_Behavior AUDIO_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
271 PKT_Behavior MPEG_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
272 //-------------------------------------------------------------------------------------------------
273 // Local Variables
274 //-------------------------------------------------------------------------------------------------
275
276 //*********************//
277 // Video //
278 //*********************//
279
280 // It should be mapped with MsHDMITX_VIDEO_TIMING structure in drvHDMITx.h
281 MDrv_HDMITx_VIDEO_MODE_INFO_TYPE HDMITxVideoModeTbl[E_HDMITX_RES_MAX]=
282 {
283 //IorPMode; PolarityH; PolarityV; VSW; VbckP; VDe; VSDel; VSDelP; HSW; HbckP; HDe; HSDel; VSTotal; HSTotal;
284 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0002, 0x0021, 0x01E0, 0x000A, 0, 0x0060, 0x0030, 0x0280, 0x0010, 0x020D, 0x0320, 60, 25175000}, // 0: 640x480p
285 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x000F, 0x01E0, 0x0004, 0, 0x007C, 0x0072, 0x05A0, 0x0026, 0x020D, 0x06B4, 60, 27000000}, // 1: 720x480i
286 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x0013, 0x0240, 0x0002, 0, 0x007E, 0x008A, 0x05A0, 0x0018, 0x0271, 0x06C0, 50, 27000000}, // 2: 720x576i
287 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0006, 0x001E, 0x01E0, 0x0009, 0, 0x003E, 0x003C, 0x02D0, 0x0010, 0x020D, 0x035A, 60, 27000000}, // 3: 720x480p
288 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0005, 0x0027, 0x0240, 0x0005, 0, 0x0040, 0x0044, 0x02D0, 0x000C, 0x0271, 0x0360, 50, 27000000}, // 4: 720x576p
289 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x02EE, 0x07BC, 50, 74250000}, // 5: 1280x720p_50Hz
290 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x02EE, 0x0672, 60, 74250000}, // 6: 1280x720p_60Hz
291 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 50, 74250000}, // 7: 1920x1080i_50Hz
292 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 60, 74250000}, // 8: 1920x1080i_60Hz
293 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x0465, 0x0ABE, 24, 74250000}, // 9: 1920x1080p_24Hz
294 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 25, 74250000}, // 10: 1920x1080p_25Hz
295 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 30, 74250000}, // 11: 1920x1080p_30Hz
296 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 50, 148500000}, // 12: 1920x1080p_50Hz
297 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 60, 148500000}, // 13: 1920x1080p_60Hz
298 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x089D, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x08CA, 0x0ABE, 24, 148500000}, // 14: 1920x2205p_24Hz //3D: 1920x1080p_24Hz x2
299 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x05DC, 0x07BC, 50, 148500000}, // 15: 1280x1470p_50Hz //3D: 1280x720_50Hz x2
300 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x05DC, 0x0672, 60, 148500000}, // 16: 1280x1470p_60Hz //3D: 1280x720_60Hz x2
301
302 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x04FC, 0x08CA, 0x157C, 24, 297000000}, // 17:93: 3840x2160p_24Hz
303 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0, 25, 297000000}, // 18:94: 3840x2160p_25Hz
304 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130, 30, 297000000}, // 19:95: 3840x2160p_30Hz
305 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0, 50, 594000000}, // 20:96: 3840x2160p_50Hz
306 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130, 60, 594000000}, // 21:97: 3840x2160p_60Hz
307
308 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x1000, 0x03FC, 0x08CA, 0x157C, 24, 297000000}, // 22:98: 4096x2160p_24Hz
309 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0, 25, 297000000}, // 23:99: 4096x2160p_25Hz
310 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130, 30, 297000000}, // 24:100: 4096x2160p_30Hz
311 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0, 50, 594000000}, // 25:101: 4096x2160p_50Hz
312 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130, 60, 594000000}, // 26:102: 4096x2160p_60Hz
313
314 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0003, 0x002E, 0x04B0, 0x0001, 0, 0x00C0, 0x0130, 0x0640, 0x0040, 0x04E2, 0x0870, 60, 162000000}, // 27: 1600x1200p_60Hz
315 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0006, 0x0019, 0x0384, 0x0003, 0, 0x0098, 0x00E8, 0x05A0, 0x0050, 0x03A6, 0x0770, 60, 106500000}, // 28: 1440x900p_60Hz
316 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0003, 0x0026, 0x0400, 0x0001, 0, 0x0070, 0x00F8, 0x0500, 0x0030, 0x042A, 0x0698, 60, 108000000}, // 29: 1280x1024p_60Hz
317 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0006, 0x001D, 0x0300, 0x0003, 0, 0x0088, 0x00A0, 0x0400, 0x0024, 0x0326, 0x0540, 60, 65000000}, // 30: 1024x768p_60Hz
318 };
319
320 //atop setting
321 stHDMITx_ATOP_SETTING HDMITxVideoAtopSetting[HDMITX_COLOR_DEPTH_TYPE_NUM][E_HDMITX_RES_MAX] =
322 {
323 //color depth = 8bit
324 {
325 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
326 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
327 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
328 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
329 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
330 // 74Mhz
331 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
332 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
333 #if (defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
334 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
335 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 8: 1920x1080i_60Hz
336 #else
337 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
338 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
339 #endif
340 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
341 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
342 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
343 // 148Mhz
344 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 12: 1920x1080p_50Hz
345 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 13: 1920x1080p_60Hz
346 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 14: 1920x2205p_24Hz
347 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 15: 1280x1470p_50Hz
348 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 16: 1280x1470p_60Hz
349 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
350 // 300Mhz
351 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
352 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
353 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
354 // 600Mhz
355 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
356 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
357 // 300Mhz
358 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
359 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
360 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
361 // 600Mhz
362 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
363 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
364
365 // 150MHz
366 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x2AAAAA}, // 27: 1600x1200p_60Hz
367 // 106.5MHz
368 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x40EB71}, // 28: 1440x900p_60Hz
369 // 108MHz
370 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 29: 1280x1024p_60Hz
371 // 65MHz
372 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x352B52}, // 30: 1024x768p_60Hz
373 },
374
375 //color depth = 10 bit
376 {
377 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 0: 640x480p
378 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 1: 720x480i
379 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 2: 720x576i
380 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 3: 720x480p
381 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 4: 720x576p
382 // 74Mhz
383 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 5: 1280x720p_50Hz
384 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 6: 1280x720p_60Hz
385 #if (defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
386 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 7: 1920x1080i_50Hz
387 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 8: 1920x1080i_60Hz
388 #else
389 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 7: 1920x1080i_50Hz
390 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x25460A}, // 8: 1920x1080i_60Hz
391 #endif
392 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 9: 1920x1080p_24Hz
393 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 10: 1920x1080p_25Hz
394 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 11: 1920x1080p_30Hz
395 // 148Mhz
396 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 12: 1920x1080p_50Hz
397 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 13: 1920x1080p_60Hz
398 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 14: 1920x2205p_24Hz
399 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 15: 1280x1470p_50Hz
400 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 16: 1280x1470p_60Hz
401 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
402
403 // 300Mhz
404 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 17:93: 3840x2160p_24Hz
405 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 18:94: 3840x2160p_25Hz
406 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 19:95: 3840x2160p_30Hz
407 // 600Mhz ==> not support !!!
408 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 20:96: 3840x2160p_50Hz
409 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 21:97: 3840x2160p_60Hz
410 // 300Mhz
411 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 22:98: 4096x2160p_24Hz
412 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 23:99: 4096x2160p_25Hz
413 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 24:100: 4096x2160p_30Hz
414 // 600Mhz ==> not support !!!
415 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 25:101: 4096x2160p_50Hz
416 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 26:102: 4096x2160p_60Hz
417
418 // 150MHz
419 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x222222}, // 27: 1600x1200p_60Hz
420 // 106.5MHz
421 //{0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x33EBCE}, // 28: 1440x900p_60Hz
422 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x33EF8D},
423 // 108MHz
424 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 29: 1280x1024p_60Hz
425 // 65MHz
426 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x2A890E}, // 30: 1024x768p_60Hz
427 },
428
429 //color depth = 12 bit
430 {
431 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 0: 640x480p
432 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 1: 720x480i
433 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 2: 720x576i
434 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 3: 720x480p
435 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 4: 720x576p
436 // 74Mhz
437 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 5: 1280x720p_50Hz
438 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 6: 1280x720p_60Hz
439 #if (defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
440 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 7: 1920x1080i_50Hz
441 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 8: 1920x1080i_60Hz
442 #else
443 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 7: 1920x1080i_50Hz
444 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F0FB3}, // 8: 1920x1080i_60Hz
445 #endif
446 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 9: 1920x1080p_24Hz
447 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 10: 1920x1080p_25Hz
448 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 11: 1920x1080p_30Hz
449 // 148Mhz
450 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 12: 1920x1080p_50Hz
451 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 13: 1920x1080p_60Hz
452 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 14: 1920x2205p_24Hz
453 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 15: 1280x1470p_50Hz
454 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 16: 1280x1470p_60Hz
455 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
456
457 // 300Mhz
458 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 17:93: 3840x2160p_24Hz
459 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 18:94: 3840x2160p_25Hz
460 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 19:95: 3840x2160p_30Hz
461 // 600Mhz ==> not support !!!
462 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 20:96: 3840x2160p_50Hz
463 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 21:97: 3840x2160p_60Hz
464 // 300Mhz
465 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 22:98: 4096x2160p_24Hz
466 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 23:99: 4096x2160p_25Hz
467 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 24:100: 4096x2160p_30Hz
468 // 600Mhz ==> not support !!!
469 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 25:101: 4096x2160p_50Hz
470 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 26:102: 4096x2160p_60Hz
471
472 // 150MHz
473 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x04, 0x1C71C7}, // 27: 1600x1200p_60Hz
474 // 106.5MHz
475 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x2B47A0}, // 28: 1440x900p_60Hz
476 // 108MHz
477 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x2AAAAA}, // 29: 1280x1024p_60Hz
478 // 65MHz
479 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x237237}, // 30: 1024x768p_60Hz
480 },
481
482 //color depth = 16 bit
483 {
484 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
485 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
486 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
487 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
488 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
489 // 74Mhz
490 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
491 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
492 #if (defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
493 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 7: 1920x1080i_50Hz
494 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 8: 1920x1080i_60Hz
495 #else
496 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
497 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
498 #endif
499 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
500 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
501 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
502 // 148Mhz
503 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 12: 1920x1080p_50Hz
504 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 13: 1920x1080p_60Hz
505 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 14: 1920x2205p_24Hz
506 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 15: 1280x1470p_50Hz
507 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 16: 1280x1470p_60Hz
508 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
509
510 // 300Mhz
511 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
512 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
513 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
514 // 600Mhz ==> Not support !!!
515 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
516 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
517 // 300Mhz
518 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
519 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
520 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
521 // 600Mhz ==> Not support !!!
522 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
523 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
524
525 // 150MHz
526 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x04, 0x2AAAAA}, // 27: 1600x1200p_60Hz
527 // 106.5MHz
528 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x40EB71}, // 28: 1440x900p_60Hz
529 // 108MHz
530 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x400000}, // 29: 1280x1024p_60Hz
531 // 65MHz
532 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x352B52}, // 30: 1024x768p_60Hz
533 },
534 };
535
536 #if( defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1) )
537 //For Maxim 420 and Interlace Only HDMITXPHY_0x15[14:12]
538 MS_U8 HDMITxVideo_OTMDS_ODATA_Ratio[HDMITX_COLOR_DEPTH_TYPE_NUM][E_HDMITX_RES_MAX] =
539 {
540 //color depth = 8bit
541 {
542 0x03, // 0: 640x480p
543 0x03, // 1: 720x480i
544 0x03, // 2: 720x576i
545 0x03, // 3: 720x480p
546 0x03, // 4: 720x576p
547 // 74Mhz
548 0x02, // 5: 1280x720p_50Hz
549 0x02, // 6: 1280x720p_60Hz
550 0x02, // 7: 1920x1080i_50Hz
551 0x02, // 8: 1920x1080i_60Hz
552 0x02, // 9: 1920x1080p_24Hz
553 0x02, // 10: 1920x1080p_25Hz
554 0x02, // 11: 1920x1080p_30Hz
555 // 148Mhz
556 0x02, // 12: 1920x1080p_50Hz
557 0x02, // 13: 1920x1080p_60Hz
558 0x02, // 14: 1920x2205p_24Hz
559 0x02, // 15: 1280x1470p_50Hz
560 0x02, // 16: 1280x1470p_60Hz
561 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
562 // 300Mhz
563 0x02, // 17:93: 3840x2160p_24Hz
564 0x02, // 18:94: 3840x2160p_25Hz
565 0x02, // 19:95: 3840x2160p_30Hz
566 // 600Mhz
567 0x01, // 20:96: 3840x2160p_50Hz
568 0x01, // 21:97: 3840x2160p_60Hz
569 // 300Mhz
570 0x02, // 22:98: 4096x2160p_24Hz
571 0x02, // 23:99: 4096x2160p_25Hz
572 0x02, // 24:100: 4096x2160p_30Hz
573 // 600Mhz
574 0x01, // 25:101: 4096x2160p_50Hz
575 0x01, // 26:102: 4096x2160p_60Hz
576 },
577
578 //color depth = 10 bit
579 {
580 0x03, // 0: 640x480p
581 0x03, // 1: 720x480i
582 0x03, // 2: 720x576i
583 0x03, // 3: 720x480p
584 0x03, // 4: 720x576p
585 // 74Mhz
586 0x02, // 5: 1280x720p_50Hz
587 0x02, // 6: 1280x720p_60Hz
588 0x02, // 7: 1920x1080i_50Hz
589 0x02, // 8: 1920x1080i_60Hz
590 0x02, // 9: 1920x1080p_24Hz
591 0x02, // 10: 1920x1080p_25Hz
592 0x02, // 11: 1920x1080p_30Hz
593 // 148Mhz
594 0x02, // 12: 1920x1080p_50Hz
595 0x02, // 13: 1920x1080p_60Hz
596 0x02, // 14: 1920x2205p_24Hz
597 0x02, // 15: 1280x1470p_50Hz
598 0x02, // 16: 1280x1470p_60Hz
599 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
600 // 300Mhz
601 0x02, // 17:93: 3840x2160p_24Hz
602 0x02, // 18:94: 3840x2160p_25Hz
603 0x02, // 19:95: 3840x2160p_30Hz
604 // 600Mhz ==> not support !!!
605 0x00, // 20:96: 3840x2160p_50Hz
606 0x00, // 21:97: 3840x2160p_60Hz
607 // 300Mhz
608 0x02, // 22:98: 4096x2160p_24Hz
609 0x02, // 23:99: 4096x2160p_25Hz
610 0x02, // 24:100: 4096x2160p_30Hz
611 // 600Mhz ==> not support !!!
612 0x00, // 25:101: 4096x2160p_50Hz
613 0x00, // 26:102: 4096x2160p_60Hz
614 },
615
616 //color depth = 12 bit
617 {
618 0x03, // 0: 640x480p
619 0x03, // 1: 720x480i
620 0x03, // 2: 720x576i
621 0x03, // 3: 720x480p
622 0x03, // 4: 720x576p
623 // 74Mhz
624 0x02, // 5: 1280x720p_50Hz
625 0x02, // 6: 1280x720p_60Hz
626 0x02, // 7: 1920x1080i_50Hz
627 0x02, // 8: 1920x1080i_60Hz
628 0x02, // 9: 1920x1080p_24Hz
629 0x02, // 10: 1920x1080p_25Hz
630 0x02, // 11: 1920x1080p_30Hz
631 // 148Mhz
632 0x02, // 12: 1920x1080p_50Hz
633 0x02, // 13: 1920x1080p_60Hz
634 0x02, // 14: 1920x2205p_24Hz
635 0x02, // 15: 1280x1470p_50Hz
636 0x02, // 16: 1280x1470p_60Hz
637 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
638 // 300Mhz
639 0x02, // 17:93: 3840x2160p_24Hz
640 0x02, // 18:94: 3840x2160p_25Hz
641 0x02, // 19:95: 3840x2160p_30Hz
642 // 600Mhz ==> not support !!!
643 0x00, // 20:96: 3840x2160p_50Hz
644 0x00, // 21:97: 3840x2160p_60Hz
645 // 300Mhz
646 0x02, // 22:98: 4096x2160p_24Hz
647 0x02, // 23:99: 4096x2160p_25Hz
648 0x02, // 24:100: 4096x2160p_30Hz
649 // 600Mhz ==> not support !!!
650 0x00, // 25:101: 4096x2160p_50Hz
651 0x00, // 26:102: 4096x2160p_60Hz
652 },
653
654 //color depth = 16 bit
655 {
656 0x02, // 0: 640x480p
657 0x02, // 1: 720x480i
658 0x02, // 2: 720x576i
659 0x02, // 3: 720x480p
660 0x02, // 4: 720x576p
661 // 74Mhz
662 0x01, // 5: 1280x720p_50Hz
663 0x01, // 6: 1280x720p_60Hz
664 0x01, // 7: 1920x1080i_50Hz
665 0x01, // 8: 1920x1080i_60Hz
666 0x01, // 9: 1920x1080p_24Hz
667 0x01, // 10: 1920x1080p_25Hz
668 0x01, // 11: 1920x1080p_30Hz
669 // 148Mhz
670 0x01, // 12: 1920x1080p_50Hz
671 0x01, // 13: 1920x1080p_60Hz
672 0x01, // 14: 1920x2205p_24Hz
673 0x01, // 15: 1280x1470p_50Hz
674 0x01, // 16: 1280x1470p_60Hz
675 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
676 // 300Mhz
677 0x01, // 17:93: 3840x2160p_24Hz
678 0x01, // 18:94: 3840x2160p_25Hz
679 0x01, // 19:95: 3840x2160p_30Hz
680 // 600Mhz ==> Not support !!!
681 0x00, // 20:96: 3840x2160p_50Hz
682 0x00, // 21:97: 3840x2160p_60Hz
683 // 300Mhz
684 0x01, // 22:98: 4096x2160p_24Hz
685 0x01, // 23:99: 4096x2160p_25Hz
686 0x01, // 24:100: 4096x2160p_30Hz
687 // 600Mhz ==> Not support !!!
688 0x00, // 25:101: 4096x2160p_50Hz
689 0x00, // 26:102: 4096x2160p_60Hz
690 },
691 };
692 #endif
693
694 //*********************//
695 // Audio //
696 //*********************//
697
698 MSTHDMITX_REG_TYPE HDMITxAudioOnTbl[] =
699 {
700 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enable audio FIFO, [2]:enable CTS Gen, [1]: automatically block start, [0]: audio FIFO not flush
701 };
702
703 MSTHDMITX_REG_TYPE HDMITxAudioOffTbl[] =
704 {
705 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
706 };
707
708 MSTHDMITX_REG_TYPE HDMITxAudioInitTbl[] =
709 {
710 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
711 };
712
713 MDrv_HDMITx_AUDIO_FREQ_TYPE TxAudioFreqTbl[E_HDMITX_AUDIO_FREQ_MAX_NUM] =
714 {
715 {0x02, 0x001800}, // No signal, set to 48 KHz
716 {0x03, 0x001000}, // 0 ~(32)~ 38 KHz, 4096
717 {0x00, 0x001880}, // 38 ~(44.1)~ 46 KHz, 6272
718 {0x02, 0x001800}, // 46 ~(48)~ 60 KHz, 6144
719 {0x08, 0x003100}, // 60 ~(88.2)~ 92 KHz, 12544
720 {0x0a, 0x003000}, // 92 ~(96)~ 140 KHz, 12288
721 {0x0c, 0x006200}, // 140 ~(176.4)~ 180 KHz, 25088
722 {0x0e, 0x006000}, // 180 ~(192)~ ~~ KHz, 24576
723 };
724
725 //*********************//
726 // Packet //
727 //*********************//
728
729 MS_U8 HDMITX_AviCmrTbl[E_HDMITX_RES_MAX] =
730 {
731 0x48, 0x48, 0x48, 0x48, 0x48, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, // SDTV C=01(601),M=00(no data) ,R=1000(same)
732 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0x48,
733 0xA8, 0x48, 0x48,
734 };
735
736 MS_U8 HDMITX_AviVicTbl[E_HDMITX_RES_MAX] =
737 {
738 1, 6, 21, 2, 17, 19, 4, 20, 5, 32, 33, 34, 31, 16, // SDTV 480i60,576i50,480p60,576p50,720p50,720p60,1080i50,1080i60,1080p24,1080p25,1080p30, 1080p50, 1080p60
739 32, 19, 4, 0, 0, 0, 96, 97, 0, 99, 100, 101, 102, 0,
740 0, 0, 0,
741 };
742
743 MS_U8 HDMITX_VendorName[8] =
744 {
745 "MStar "
746 };
747
748 MS_U8 HDMITX_ProductName[16] =
749 {
750 "HDMI Tx Demo",
751 };
752
753 MS_U8 _gHPDGpioPin = 0;
754
755 //-------------------------------------------------------------------------------------------------
756 // Debug Functions
757 //-------------------------------------------------------------------------------------------------
758
759 #ifdef MS_DEBUG
760 #define DBG_HDMITX(_f) (_f)
761 #else
762 #define DBG_HDMITX(_f)
763 #endif
764
765 //-------------------------------------------------------------------------------------------------
766 // Local Functions
767 //-------------------------------------------------------------------------------------------------
768
769
770 //-------------------------------------------------------------------------------------------------
771 // Global Functions
772 //-------------------------------------------------------------------------------------------------
773 /*********************************************************************/
774 /* */
775 /* HDCP22 Relative */
776 /* */
777 /*********************************************************************/
MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)778 void MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)
779 {
780 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x11, bEnable ? 0x11 : 0x00); // bit 0: enable hdcp22; bit 4: enable EESS
781 if (bEnable)
782 {
783 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x02); //reset hdcp22 FSM
784 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x00);
785 }
786 }
787
MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)788 void MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)
789 {
790 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x04, bEnable ? 0x04 : 0x00); //bit 2: authentication pass
791 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x08, bEnable ? 0x08 : 0x00); //bit 3: enable hdcp22 to issue encryption enable signal
792 }
793
MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 * pu8Riv,MS_U8 * pu8KsXORLC128)794 void MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 *pu8Riv, MS_U8 *pu8KsXORLC128)
795 {
796 #define DEF_HDCP2CIPHER_DBG 0
797 #define SIZE_OF_KSXORLC128 16
798 #define SIZE_OF_RIV 8
799
800 MS_U8 cnt = 0;
801
802 #if (DEF_HDCP2CIPHER_DBG == 1)
803 printf("Ks^LC128:\r\n");
804 for ( cnt = 0; cnt < SIZE_OF_KSXORLC128; cnt++ )
805 {
806 printf("0x%02X ", *(pu8KsXORLC128 + cnt));
807 }
808 printf("\r\n");
809
810 printf("Riv:\r\n");
811 for ( cnt = 0; cnt < SIZE_OF_RIV; cnt++ )
812 {
813 printf("0x%02X ", *(pu8Riv + cnt));
814 }
815 printf("\r\n");
816 #endif
817
818 #undef DEF_HDCP2CIPHER_DBG
819 //MHal_HDMITx_Mask_Write(0x172F00, 0x01, 0x0020, 0x0020); //reverse order of cihper key
820 //MHal_HDMITx_Mask_Write(0x172B00, 0x01, 0x8000, 0x0000); //disable hdcp 1.4 module
821
822 for ( cnt = 0; cnt < (SIZE_OF_KSXORLC128>>1); cnt++)
823 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x60 + (SIZE_OF_KSXORLC128 >> 1) - 1 - cnt, *(pu8KsXORLC128 + cnt*2 + 1)|(*(pu8KsXORLC128 + cnt*2)<<8));
824
825 for ( cnt = 0; cnt < (SIZE_OF_RIV>>1); cnt++)
826 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x68 + (SIZE_OF_RIV >> 1) - 1 - cnt, *(pu8Riv + cnt*2 + 1)|(*(pu8Riv + cnt*2)<<8));
827 }
828
Mhal_HDMITx_SetSCDCCapability(MS_BOOL bFlag)829 void Mhal_HDMITx_SetSCDCCapability(MS_BOOL bFlag)
830 {
831 g_bSupportSCDC = bFlag;
832 }
833
MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)834 void MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)
835 {
836 gu8ChipVerNum = u8ChipVer;
837 }
838
839 // HPD: GPIO_PM[11] -> external interrupt[11], register 0x000E00[14]
840 // DVI disconnet: must power down clock termination resistor: TM_REG[0] = 1, TM_REG[16:15] = 00, TM_REG[35:34] = 00.
841 // Interrupt helper functoins
842 //------------------------------------------------------------------------------
843 /// @brief Disable interrupt
844 /// @param[in] u32Int interrupter value
845 /// @return None
846 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Disable(MS_U32 u32Int)847 void MHal_HDMITx_Int_Disable(MS_U32 u32Int)
848 {
849 //MS_U16 u16reg_val = 0;
850
851 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int);
852 // [9]: mask FIQ, [8]: mask IRQ
853 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) );
854
855 #if 0 // K1 HPD pin doesn't have interrupt function
856 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
857 {
858 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
859 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank
860 {
861 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask
862 }
863 }
864 #endif
865 }
866
867 //------------------------------------------------------------------------------
868 /// @brief Enable interrupt
869 /// @param[in] u32Int interrupter value
870 /// @return None
871 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Enable(MS_U32 u32Int)872 void MHal_HDMITx_Int_Enable(MS_U32 u32Int)
873 {
874 //MS_U16 u16reg_val = 0;
875
876 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int);
877 // [9]: mask FIQ, [8]: unmask IRQ
878 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 );
879
880 #if 0 // K1 HPD pin doesn't have interrupt function
881 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
882 {
883 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
884 if(u32Int & E_HDMITX_IRQ_12)
885 {
886 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_PM output disable
887 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask
888 }
889 }
890 #endif
891 }
892
893 //------------------------------------------------------------------------------
894 /// @brief MHal_HDMITx_Int_Clear
895 /// @param[in] u32Int interrupter value
896 /// @return None
897 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Clear(MS_U32 u32Int)898 void MHal_HDMITx_Int_Clear(MS_U32 u32Int)
899 {
900 //MS_U16 u16reg_val = 0;
901
902 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int);
903 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16));
904
905 #if 0 // K1 HPD pin doesn't have interrupt function
906 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
907 {
908 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
909 if(u32Int & E_HDMITX_IRQ_12)
910 {
911 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val);
912 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0);
913 }
914 }
915 #endif
916 }
917
918 //------------------------------------------------------------------------------
919 /// @brief MHal_HDMITx_Int_Status
920 /// @param[in] u32Int interrupter value
921 /// @return None
922 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Status(void)923 MS_U32 MHal_HDMITx_Int_Status(void)
924 {
925 //MS_U16 u16reg_val = 0;
926 MS_U32 reg_value=0;
927
928 reg_value |= MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E);
929 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16);
930
931 #if 0 // K1 HPD pin doesn't have interrupt function
932 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4
933 {
934 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
935 reg_value = ((MHal_HDMITxPM_Read(PMBK_PMSLEEP_REG_BASE, 0x0A) & u16reg_val) ? (reg_value|E_HDMITX_IRQ_12):(reg_value&(~E_HDMITX_IRQ_12)));
936 }
937 #endif
938 return reg_value;
939 }
940
941
942 //------------------------------------------------------------------------------
943 /// @brief This routine is to get HDMI receiver DVI clock and HPD status.
944 /// @return MsHDMITX_RX_STATUS
945 //------------------------------------------------------------------------------
MHal_HDMITx_GetRXStatus(void)946 MsHDMITX_RX_STATUS MHal_HDMITx_GetRXStatus(void)
947 {
948 MS_BOOL dviclock_s, hpd_s = FALSE;
949 MsHDMITX_RX_STATUS state;
950
951 dviclock_s = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F) & BIT0 ? FALSE : TRUE;
952
953 hpd_s = mdrv_gpio_get_level(_gHPDGpioPin);
954
955 if((dviclock_s == FALSE) && (hpd_s == FALSE))
956 state = E_HDMITX_DVIClock_L_HPD_L;
957 else if((dviclock_s == FALSE) && (hpd_s == TRUE))
958 state = E_HDMITX_DVIClock_L_HPD_H;
959 else if((dviclock_s == TRUE) && (hpd_s == FALSE))
960 state = E_HDMITX_DVIClock_H_HPD_L;
961 else
962 state = E_HDMITX_DVIClock_H_HPD_H;
963
964 return state;
965 }
966
967
968 //------------------------------------------------------------------------------
969 /// @brief MHal_HDMITX_SetHDCPConfig
970 /// @param[in] u32Int HDCP mode
971 /// @return None
972 //------------------------------------------------------------------------------
MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)973 void MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)
974 {
975 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8);
976 }
977
978
979 //------------------------------------------------------------------------------
980 /// @brief MHal_HDMITX_GetM02Bytes
981 /// @param[in] u16Int index
982 /// @return M0 2 bytes
983 //------------------------------------------------------------------------------
MHal_HDMITX_GetM02Bytes(MS_U16 idx)984 MS_U16 MHal_HDMITX_GetM02Bytes(MS_U16 idx)
985 {
986 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx));
987 }
988
989
990 //------------------------------------------------------------------------------
991 /// @brief MHal_HDMITx_InitSeq
992 /// @param[in] None
993 /// @return None
994 //------------------------------------------------------------------------------
MHal_HDMITx_InitSeq(void)995 void MHal_HDMITx_InitSeq(void)
996 {
997 MHal_HDMITx_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, 0); // enable clk_hdmi_tx_p
998 MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x0010, 0x0010); //ODCLK source from HDMITx, MST253B Only
999
1000 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_40, 0x0001, 0x0001);//MST253B Only
1001 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3D, 0x0400, 0x0400);//MST253B Only
1002 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_01, 0x0001, 0x0001);//MST253B Only
1003 //MHal_HDMITx_Mask_Write(0x000E00U, 0x72U, 0x1000, 0x1000);//MST253B Only for HPD
1004 //MHal_HDMITx_Mask_Write(0x101E00U, 0x6EU, 0x0004, 0x0004);//MST253B Only for DDC
1005
1006 //set at mboot
1007 //MHal_HDMITx_Mask_Write(0x101E00, 0x0B, BIT12, BIT12); //enable hdmitx DDC
1008
1009 //MAC setting
1010 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1C, 0x0000);
1011 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1D, 0x0000);
1012 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1E, 0xFFFF);
1013 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1F, 0x0000);
1014
1015 //sw reset modules
1016 if(MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E) & 0xE800)
1017 {
1018 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
1019 }
1020 else
1021 {
1022 //disable power down
1023 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
1024 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
1025 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
1026 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0017);
1027 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0000);
1028 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x001F);
1029 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x0000);
1030 }
1031
1032 //MHal_HDMITx_Write(HDMITX_REG_BASE, REG_HPLL_LOCK_CNT_53, 0x0300); // HPLL lock counter
1033
1034 //enable PHY setting
1035 //[0]:enable synth clock; [4]:enable synth clock to a top; [8]:enable tmds clock; [12]: enable atop 40 bit clock
1036 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101, 0x1101);
1037 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
1038 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00);
1039
1040 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F, 0x0010, 0x0010); //reg_atop_nodie_en_disc
1041
1042 //disable power down
1043 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
1044 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, 0x0000);
1045
1046 //rterm set by Mboot according to data of EFUSE, rterm 50 Ohm
1047 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x01F0, 0x0000);
1048
1049 //txpll input div 1
1050 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x03F3, 0x0051);
1051
1052 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3D, 0x030F, 0x0003); //REG_TXPLL_SEL_CLKIN, REG_TXPLL_ICP_ICTRL
1053 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0003); //REG_ICTRL_PREDRV_MAIN_CLK
1054 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0000); //REG_ICTRL_PREDRV_MAIN_CLK
1055 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x003F, 0x0010); //REG_ICTRL_DRV_MAIN_CLK
1056
1057 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_32, 0x3F3F, 0x0000);
1058 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_36, 0x3F3F, 0x0000);
1059 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_37, 0x3F3F, 0x0000);
1060
1061 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
1062
1063 //lane fifo setting
1064 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x0007, 0x0004);
1065 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x0007, 0x0005);
1066 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x0007, 0x0006);
1067 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x0007, 0x0007);
1068
1069 //timing field regen enable (due to scaler can't guarantee field signal and even/odd frame is asynchronize)
1070 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x0010, 0x0010);
1071
1072 //for U02: QD980 CTS compatibility issue
1073 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x8000, 0x8000);
1074
1075 }
1076
1077 //------------------------------------------------------------------------------
1078 /// @brief This routine is the initialization for Video module.
1079 /// @return None
1080 //------------------------------------------------------------------------------
MHal_HDMITx_VideoInit(void)1081 void MHal_HDMITx_VideoInit(void)
1082 {
1083 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, BIT4, BIT4); //enable video engine fifo r/w pointer
1084 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_12, 0x000F, BIT3); // [3]: manual mode of pixel-repetition enable
1085 }
1086
1087 //------------------------------------------------------------------------------
1088 /// @brief This routine is the initialization for Audio module.
1089 /// @return None
1090 //------------------------------------------------------------------------------
MHal_HDMITx_AudioInit(void)1091 void MHal_HDMITx_AudioInit(void)
1092 {
1093 int num;
1094
1095 num = sizeof(HDMITxAudioInitTbl) / sizeof(MSTHDMITX_REG_TYPE);
1096 MHal_HDMITx_RegsTbl_Write(HDMITxAudioInitTbl, num);
1097 }
1098
1099
1100 //------------------------------------------------------------------------------
1101 /// @brief This routine turn on/off HDMI PLL
1102 /// @return None
1103 //------------------------------------------------------------------------------
MHal_HDMITx_PLLOnOff(MS_BOOL bflag)1104 void MHal_HDMITx_PLLOnOff(MS_BOOL bflag)
1105 {
1106 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, bflag ? 0x0000 : 0x0010);
1107 }
1108
1109
MHal_HDMITx_PKT_User_Define_Clear(void)1110 void MHal_HDMITx_PKT_User_Define_Clear(void)
1111 {
1112 MS_U8 i = 0;
1113
1114 for ( i = 0; i < GENERAL_PKT_NUM; i++ )
1115 {
1116 gbGeneralPktList[i].EnableUserDef = FALSE;
1117 gbGeneralPktList[i].FrmCntNum = 0x00;
1118 gbGeneralPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
1119 memset(&gbGeneralPktList[i].PktPara, 0x00, sizeof(gbGeneralPktList[i].PktPara));
1120 }
1121
1122 for ( i = 0; i < INFOFRM_PKT_NUM; i++ )
1123 {
1124 gbInfoFrmPktList[i].EnableUserDef = FALSE;
1125 gbInfoFrmPktList[i].FrmCntNum = 0x00;
1126 gbInfoFrmPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
1127 memset(&gbInfoFrmPktList[i].PktPara, 0x00, sizeof(gbInfoFrmPktList[i].PktPara));
1128 }
1129 }
1130
MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type,MS_BOOL def_flag,MsHDMITX_PACKET_PROCESS def_process,MS_U8 def_fcnt)1131 void MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type, MS_BOOL def_flag,
1132 MsHDMITX_PACKET_PROCESS def_process, MS_U8 def_fcnt)
1133 {
1134 if (packet_type & 0x80) //infoframe packet type
1135 {
1136 gbInfoFrmPktList[packet_type & (~0x80)].EnableUserDef = def_flag;
1137 gbInfoFrmPktList[packet_type & (~0x80)].FrmCntNum = def_fcnt;
1138 gbInfoFrmPktList[packet_type & (~0x80)].enPktCtrl = def_process;
1139 }
1140 else
1141 {
1142 gbGeneralPktList[packet_type].EnableUserDef = def_flag;
1143 gbGeneralPktList[packet_type].FrmCntNum = def_fcnt;
1144 gbGeneralPktList[packet_type].enPktCtrl = def_process;
1145 }
1146 }
1147
MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type,MS_U8 * data,MS_U8 length)1148 MS_BOOL MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type, MS_U8* data, MS_U8 length)
1149 {
1150 MS_BOOL bRet = TRUE;
1151 MS_U8 i, j, *ptr;
1152 ptr = data;
1153
1154 switch(packet_type)
1155 {
1156 case E_HDMITX_VS_INFOFRAME:
1157 for (i=0; i < length; i++)
1158 {
1159 j = i>>1;
1160
1161 if ((REG_PKT_VS_1_27+j > REG_PKT_VS_14_34) || ((REG_PKT_VS_1_27+j == REG_PKT_VS_14_34) && (i % 2 == 1)))
1162 {
1163 //Packet over size, last VS packet PB register is REG_PKT_VS_14_34[7:0]
1164 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
1165 break;
1166 }
1167
1168 if((i%2)==0)
1169 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0x00FF, *(ptr+i));
1170 else
1171 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0xFF00, (*(ptr+i))<<8);
1172 }
1173 break;
1174 case E_HDMITX_SPD_INFOFRAME:
1175 for(i=0;i<length;i++)
1176 {
1177 j = i>>1;
1178
1179 if((REG_PKT_SPD_1_15+j > REG_PKT_SPD_13_21) || ((REG_PKT_SPD_1_15+j == REG_PKT_SPD_13_21) && (i % 2 == 1)))
1180 {
1181 //Packet over size, last SPD packet PB register is REG_PKT_SPD_13_21[7:0]
1182 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
1183 break;
1184 }
1185
1186 if((i%2)==0)
1187 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0x00FF, *(ptr+i));
1188 else
1189 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0xFF00, (*(ptr+i))<<8);
1190 }
1191 break;
1192
1193 case E_HDMITX_AVI_INFOFRAME:
1194 for ( i = 0; i < length; i++ )
1195 {
1196 j = i >> 1;
1197
1198 if (((REG_PKT_AVI_1_09 + j) > REG_PKT_AVI_7_0F) || (((REG_PKT_AVI_1_09 + j) == REG_PKT_AVI_7_0F) && (i % 2 == 1)))
1199 {
1200 DBG_HDMITX(printf("AVI packet over size, length = %d \n", length));
1201 break;
1202 }
1203
1204 if ((i % 2) == 0)
1205 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + j, 0x00FF, *(ptr+i));
1206 else
1207 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + j, 0xFF00, *(ptr+i) << 8);
1208 }
1209 break;
1210
1211 //wilson@kano HDR packet
1212 case E_HDMITX_HDR_INFOFRAME:
1213 //first 3 bytes will follow spec, (1) type code (2) version (3) length, and reamins will be content
1214 length = (length > (HDMITX_HDR_INFO_PKT_LEN + 3)) ? (HDMITX_HDR_INFO_PKT_LEN + 3) : length;
1215 //fill length and version
1216 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F,(*(ptr+2) << 8) | *(ptr+1));
1217
1218 if (length >= 3)
1219 {
1220 for ( i = 0; i < (length-3); i++ )
1221 {
1222 j = i >> 1;
1223
1224 if ( ((REG_HDMI_2_CONFIG_10 + j) > REG_HDMI_2_CONFIG_1D) || (((REG_HDMI_2_CONFIG_10 + j) == REG_HDMI_2_CONFIG_1D) && (i % 2 == 1)) )
1225 {
1226 DBG_HDMITX(printf("HDR packet over size, length = %d \n", length));
1227 break;
1228 }
1229
1230 if ((i % 2) == 0)
1231 {
1232 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0x00FF, *(ptr+i+3));
1233 }
1234 else
1235 {
1236 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0xFF00, (*(ptr+i+3))<<8);
1237 }
1238 }
1239 }
1240 break;
1241
1242 case E_HDMITX_AUDIO_INFOFRAME:
1243 {
1244 //total length should be 192 bits *2 = 384 bits = 48 bytes;
1245
1246 length = (length < ((192>>3)<<1) ) ? length : ((192>>3)<<1);
1247
1248 for ( i = 0; i < length; i++ )
1249 {
1250 j = i >> 1;
1251
1252 if ((i % 2) == 0)
1253 {
1254 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0x00FF, *(ptr+i));
1255 }
1256 else
1257 {
1258 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0xFF00, (*(ptr+i) << 8));
1259 }
1260 }
1261 }
1262 break;
1263
1264 default:
1265 i = 0;
1266 j = 0;
1267 bRet = FALSE;
1268 DBG_HDMITX(printf("Not implemented, packet type = %u\n", packet_type));
1269 break;
1270 }
1271
1272 return bRet;
1273 }
1274
1275 //------------------------------------------------------------------------------
1276 /// @brief This routine turn on/off HDMI Tx TMDS signal
1277 /// @param[in] bRB_Swap: R/B swap; bTMDS: TMDS flag
1278 /// @return None
1279 //------------------------------------------------------------------------------
MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap,MS_BOOL bTMDS)1280 void MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap, MS_BOOL bTMDS)
1281 {
1282 if(bRB_Swap) // R/B channel swap
1283 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, BIT13);
1284 else
1285 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, 0);
1286
1287 //reg_atop_en_data_out[13..15]: Enable data channel data output
1288 if (bTMDS == TRUE)
1289 {
1290 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
1291 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0xE800);
1292 //TBD: turn off tmds clock
1293
1294 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo
1295 MsOS_DelayTask(10);
1296 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000);
1297 }
1298 else
1299 {
1300 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
1301 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0x0000);
1302 //TBD: turn off tmds clock
1303 }
1304 }
1305
1306 //------------------------------------------------------------------------------
1307 /// @brief This routine return on/off status of HDMI Tx TMDS signal
1308 /// @return On/Off
1309 //------------------------------------------------------------------------------
MHal_HDMITx_GetTMDSStatus(void)1310 MS_U32 MHal_HDMITx_GetTMDSStatus(void)
1311 {
1312 MS_U16 usTMDSOutput = 0;
1313 MS_U16 usTMDSPD = 0;
1314 MS_U32 uiTMDSOn = 0;
1315
1316 usTMDSOutput = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E);
1317 usTMDSPD = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39);
1318
1319 if( ((usTMDSOutput&0xE800) == 0xE800) && ((usTMDSPD &0x0FFF) == 0x0000) )
1320 {
1321 uiTMDSOn = TRUE;
1322 }
1323 else
1324 {
1325 uiTMDSOn = FALSE;
1326 }
1327
1328 return uiTMDSOn;
1329 }
1330
1331 //------------------------------------------------------------------------------
1332 /// @brief This routine turn on/off HDMI Tx video output
1333 /// @param[in] bVideo: Video flag; bCSC: CSC flag, b709format = BT.709-5
1334 /// @return None
1335 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo,MS_BOOL bCSC,MS_BOOL b709format)1336 void MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo, MS_BOOL bCSC, MS_BOOL b709format)
1337 {
1338 if (bVideo == TRUE)
1339 {
1340 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0, 0x0000); // disable test pattern
1341 }
1342 else
1343 {
1344 MS_U8 i = 0x00;
1345
1346 DBG_HDMITX(printf("MDrv_HDMITx_SetVideoOnOff: csc flag= %d \n", bCSC));
1347
1348 // enable test pattern
1349 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3A, 0x0000);
1350 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3B, 0x0000);
1351 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3C, 0x03FF); // whole-blue
1352 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0|BIT1, BIT0|BIT1);
1353
1354 for ( i = 0; i < 6; i++ )
1355 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3D + i, 0x0000);
1356 }
1357 }
1358
1359 //------------------------------------------------------------------------------
1360 /// @brief This routine sets video color formatt
1361 /// @param[in] bCSC: CSC flag, YUV422 12 bit, b709format = BT.709-5
1362 /// @return None
1363 //------------------------------------------------------------------------------
MHal_HDMITx_SetColorFormat(MS_BOOL bCSC,MS_BOOL bHdmi422b12,MS_BOOL b709format)1364 void MHal_HDMITx_SetColorFormat(MS_BOOL bCSC, MS_BOOL bHdmi422b12, MS_BOOL b709format)
1365 {
1366 if (bCSC) // YUV -> RGB
1367 {
1368 DBG_HDMITX(printf("YUV -> RGB \n"));
1369 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, BIT0); //bypass
1370 }
1371 else // bypass
1372 {
1373 DBG_HDMITX(printf("bypass YUV -> RGB \n"));
1374 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, 0x00); //bypass
1375 }
1376
1377 // YUV422 12 bits output
1378 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, bHdmi422b12 ? BIT15 : 0x00);
1379 }
1380
1381 //------------------------------------------------------------------------------
1382 /// @brief This routine get CSC capability
1383 /// @param[in]
1384 /// @return False : not support R2Y. Ture : ok.
1385 //------------------------------------------------------------------------------
MHal_HDMITx_CSC_Support_R2Y(void * pDatatIn)1386 MS_BOOL MHal_HDMITx_CSC_Support_R2Y(void* pDatatIn)
1387 {
1388 pDatatIn = pDatatIn;
1389 return HDMITX_CSC_SUPPORT_R2Y;
1390 }
1391
1392 //------------------------------------------------------------------------------
1393 /// @brief This routine sets color domain and color range transform
1394 /// @param[in]
1395 /// @return False : not support this command. Ture : ok.
1396 //------------------------------------------------------------------------------
MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor,MsHDMITX_VIDEO_COLOR_FORMAT outcolor,MsHDMITX_YCC_QUANT_RANGE inrange,MsHDMITX_YCC_QUANT_RANGE outrange)1397 MS_BOOL MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor, MsHDMITX_VIDEO_COLOR_FORMAT outcolor, MsHDMITX_YCC_QUANT_RANGE inrange, MsHDMITX_YCC_QUANT_RANGE outrange)
1398 {
1399 MS_BOOL bReturn = FALSE;
1400
1401 if( (incolor == outcolor) && (inrange == outrange) )
1402 {
1403 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1404 bReturn = TRUE;
1405 DBG_HDMITX(printf("Input equals output \n"));
1406 }
1407 else if(incolor == E_HDMITX_VIDEO_COLOR_RGB444)
1408 {
1409 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LR
1410 {
1411 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1412 { //LR -> LY
1413 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1414 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x020C);
1415 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E24);
1416 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD0);
1417 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1418 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1419 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1420 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F88);
1421 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E6C);
1422 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x020C);
1423 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1424 bReturn = TRUE;
1425 DBG_HDMITX(printf("LR->LY! \n"));
1426 }
1427 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1428 { //LR -> FY
1429 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0CB0);
1430 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0256);
1431 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1DE1);
1432 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FC9);
1433 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00FE);
1434 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0357);
1435 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0056);
1436 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F77);
1437 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E33);
1438 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0256);
1439 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1440 bReturn = TRUE;
1441 DBG_HDMITX(printf("LR->FY! \n"));
1442 }
1443 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_FULL))
1444 { //LR -> FR
1445 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0C10);
1446 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1447 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1448 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1449 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1450 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1451 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1452 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1453 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1454 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1455 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1456 bReturn = TRUE;
1457 DBG_HDMITX(printf("LR->FR! \n"));
1458 }
1459 else
1460 {
1461 DBG_HDMITX(printf("LR->LR! \n"));
1462 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1463 DBG_HDMITX(printf("In/Out Same Color! \n"));
1464 bReturn = TRUE;
1465 }
1466
1467 }
1468 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FR
1469 {
1470 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1471 { //FR -> LY
1472 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00E0);
1473 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x01C0);
1474 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E69);
1475 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD7);
1476 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00BA);
1477 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0273);
1478 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x003F);
1479 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F99);
1480 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1EA6);
1481 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x01C0);
1482 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1483 bReturn = TRUE;
1484 DBG_HDMITX(printf("FR->LY! \n"));
1485 }
1486 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1487 { //FR -> FY
1488 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A1);
1489 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1490 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0200);
1491 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E2F);
1492 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD1);
1493 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1494 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1495 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1496 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F8B);
1497 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E75);
1498 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0200);
1499 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1500 bReturn = TRUE;
1501 DBG_HDMITX(printf("FR->FY! \n"));
1502 }
1503 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1504 { //FR -> LR
1505 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x5040);
1506 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0381);
1507 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1508 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1509 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1510 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1511 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1512 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1513 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1514 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0381);
1515 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1516 bReturn = TRUE;
1517 DBG_HDMITX(printf("FR->LR! \n"));
1518 }
1519 else
1520 {
1521 DBG_HDMITX(printf("FR->FR! \n"));
1522 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1523 DBG_HDMITX(printf("In/Out Same Color! \n"));
1524 bReturn = TRUE;
1525 }
1526 }
1527 else
1528 {
1529 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1530 DBG_HDMITX(printf("Not Support This! \n"));
1531 }
1532 }
1533 else if((incolor == E_HDMITX_VIDEO_COLOR_YUV444) || (incolor == E_HDMITX_VIDEO_COLOR_YUV422))
1534 {
1535 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LY
1536 {
1537 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1538 {//LY->FR
1539 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x001A);
1540 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0731);
1541 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x04AC);
1542 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1543 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1DDD);
1544 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1545 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F25);
1546 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1547 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x04AC);
1548 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0879);
1549 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1550 bReturn = TRUE;
1551 DBG_HDMITX(printf("LY->FR! \n"));
1552 }
1553 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1554 {//LY->LR
1555 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1556 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0629);
1557 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1558 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1559 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E2B);
1560 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1561 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F44);
1562 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1563 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1564 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0742);
1565 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1566 bReturn = TRUE;
1567 DBG_HDMITX(printf("May over range! \n"));
1568 DBG_HDMITX(printf("LY->LR! \n"));
1569 }
1570 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1571 {//LY->FY
1572 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00BA);
1573 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0491);
1574 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1575 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1576 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1577 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1578 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1579 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1580 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1581 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0491);
1582 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1583 bReturn = TRUE;
1584 DBG_HDMITX(printf("LY->FY! \n"));
1585 }
1586 else
1587 {
1588 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1589 DBG_HDMITX(printf("In/Out Same Color! \n"));
1590 DBG_HDMITX(printf("LY->LY! \n"));
1591 bReturn = TRUE;
1592 }
1593
1594 }
1595 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FY
1596 {
1597 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1598 {//FY->FR
1599 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1600 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x064D);
1601 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1602 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1603 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E21);
1604 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1605 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F40);
1606 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1607 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1608 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x076C);
1609 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1610 bReturn = TRUE;
1611 DBG_HDMITX(printf("FY->FR! \n"));
1612 }
1613 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1614 {//FY->LR
1615 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x504A);
1616 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0565);
1617 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x036D);
1618 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1619 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E66);
1620 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1621 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F5C);
1622 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1623 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x036D);
1624 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x065B);
1625 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1626 bReturn = TRUE;
1627 DBG_HDMITX(printf("FY->LR! \n"));
1628 }
1629 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1630 {//FY->LY
1631 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00EA);
1632 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1633 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1634 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1635 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1636 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1637 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1638 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1639 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1640 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1641 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1642 bReturn = TRUE;
1643 DBG_HDMITX(printf("FY->LY! \n"));
1644 }
1645 else
1646 {
1647 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1648 DBG_HDMITX(printf("In/Out Same Color! \n"));
1649 DBG_HDMITX(printf("FY->FY! \n"));
1650 bReturn = TRUE;
1651 }
1652 }
1653 else
1654 {
1655 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1656 DBG_HDMITX(printf("Not Support This! \n"));
1657 }
1658 }
1659 else
1660 {
1661 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1662 DBG_HDMITX(printf("Not Support This! \n"));
1663 }
1664
1665 //if(bReturn == TRUE)
1666 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, (outcolor == E_HDMITX_VIDEO_COLOR_YUV422) ? BIT15 : 0);
1667
1668 return bReturn;
1669 }
1670
1671 //------------------------------------------------------------------------------
1672 /// @brief This routine will set or stop all HDMI packet generation
1673 /// @param[in] bflag True: Enable packet gen, False : Disable packet gen
1674 /// @return None
1675 //------------------------------------------------------------------------------
MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)1676 void MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)
1677 {
1678 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT2, bflag ? BIT2:0);
1679 }
1680
1681 //------------------------------------------------------------------------------
1682 /// @brief This routine sets HDMI/DVI mode
1683 /// @param[in] bflag
1684 /// @return None
1685 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDMImode(MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)1686 void MHal_HDMITx_SetHDMImode(MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)
1687 {
1688 MS_U8 ucRegVal = 0x00;
1689
1690 DBG_HDMITX(printf("[%s][%d]HDMI mode = %d, Color Depth = %d \n", __FUNCTION__, __LINE__, bflag, bflag));
1691
1692 if (bflag) // HDMI mode
1693 {
1694 switch(cd_val)
1695 {
1696 case E_HDMITX_VIDEO_CD_NoID:
1697 case E_HDMITX_VIDEO_CD_24Bits:
1698 default:
1699 ucRegVal = 0x00;
1700 break;
1701
1702 case E_HDMITX_VIDEO_CD_30Bits:
1703 ucRegVal = 0x40;
1704 break;
1705
1706 case E_HDMITX_VIDEO_CD_36Bits:
1707 ucRegVal = 0x80;
1708 break;
1709
1710 case E_HDMITX_VIDEO_CD_48Bits:
1711 ucRegVal = 0xC0;
1712 break;
1713 }
1714
1715 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, ucRegVal|BIT2); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1716 }
1717 else // DVI
1718 {
1719 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, BIT0); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1720 }
1721 }
1722
1723
1724 //------------------------------------------------------------------------------
1725 /// @brief This routine sets audio on/off
1726 /// @param[in] bflag
1727 /// @return None
1728 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)1729 void MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)
1730 {
1731 MS_U8 num;
1732
1733 if(bflag) // audio on
1734 {
1735 num = sizeof(HDMITxAudioOnTbl)/sizeof(MSTHDMITX_REG_TYPE);
1736 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOnTbl, num);
1737 }
1738 else // audio off
1739 {
1740 num = sizeof(HDMITxAudioOffTbl)/sizeof(MSTHDMITX_REG_TYPE);
1741 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOffTbl, num);
1742 }
1743 }
1744
1745 //------------------------------------------------------------------------------
1746 /// @brief This routine sets audio sampling freq.
1747 /// @return None
1748 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,MsHDMITX_AUDIO_CHANNEL_COUNT achidx,MsHDMITX_AUDIO_CODING_TYPE actidx)1749 void MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,
1750 MsHDMITX_AUDIO_CHANNEL_COUNT achidx, MsHDMITX_AUDIO_CODING_TYPE actidx
1751 )
1752 {
1753 // HDMI audio channel setting
1754 if(achidx == E_HDMITX_AUDIO_CH_2) // 2 channels
1755 {
1756 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5]: audio FIFO depth ch1234, [4]=1'b0: 2 channels
1757 }
1758 else // 8 channels
1759 {
1760 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels
1761 }
1762
1763 // Audio channel status
1764 #if 1 //NOTE:: kano: move channel status from address 0x00 to address 0x0A
1765 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1766 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[afidx].CH_Status3 << 8) | (achidx << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
1767 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
1768 #else
1769 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_00, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1770 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_01, 0);
1771 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_02, (achidx<<4)); // [7:4]: audio channel count
1772 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS3_03, TxAudioFreqTbl[afidx].CH_Status3); // [3:0]: audio sampling frequncy
1773 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS4_04, 0);
1774 #endif
1775 // ACR N code
1776 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_2_06, 0x0F00, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000));
1777 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_3_07, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1778
1779 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_61, 0x000F, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000) >> 8);
1780 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_60, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1781 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x0100, 0x0100); //enable cts * 2
1782 }
1783
1784 //------------------------------------------------------------------------------
1785 /// @brief This routine sets audio source format.
1786 /// @return None
1787 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)1788 void MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)
1789 {
1790 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8);
1791 }
1792
1793 //------------------------------------------------------------------------------
1794 /// @brief This routine Get Audio CTS value
1795 /// @return CTS
1796 //------------------------------------------------------------------------------
MHal_HDMITx_GetAudioCTS(void)1797 MS_U32 MHal_HDMITx_GetAudioCTS(void)
1798 {
1799 MS_U32 ret;
1800
1801 ret = ((MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_2_06) & 0x000F) << 16) | MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_1_05);
1802 return ret;
1803 }
1804
1805 //------------------------------------------------------------------------------
1806 /// @brief This routine Mute Audio FIFO
1807 /// @param[in] bflag: True: mute audio, False: unmute audio
1808 /// @return None
1809 //------------------------------------------------------------------------------
MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)1810 void MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)
1811 {
1812 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag);
1813 }
1814
1815 //------------------------------------------------------------------------------
1816 /// @brief This routine sets HDMI Tx HDCP encryption On/Off
1817 /// @return None
1818 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag,MS_BOOL hdmi_flag)1819 void MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag, MS_BOOL hdmi_flag)
1820 {
1821 if(hdcp_flag) // HDCP on
1822 {
1823 if (hdmi_flag) // HDMI EESS
1824 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400);
1825 else // DVI OESS
1826 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000);
1827 // HDCP encryption
1828 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008);
1829 }
1830 else // HDCP off
1831 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000);
1832 }
1833
1834 //------------------------------------------------------------------------------
1835 /// @brief This routine calculate check sum of infoframes.
1836 /// @param[in] packet_type packet type
1837 /// @return checksum
1838 //------------------------------------------------------------------------------
MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)1839 MS_U8 MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)
1840 {
1841 MS_U8 ucSumVal = 0;
1842 MS_U8 i = 0;
1843 MS_U8 j = 0;
1844 MS_U16 wRegVal = 0;
1845
1846 switch (packet_type)
1847 {
1848 case E_HDMITX_VS_INFOFRAME:
1849 ucSumVal += (E_HDMITX_VS_INFOFRAME + HDMITX_VS_INFO_PKT_VER + HDMITX_VS_INFO_PKT_LEN);
1850
1851 for ( i = 0; i < (HDMITX_VS_INFO_PKT_LEN + 1) >> 1; i++ )
1852 {
1853 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_VS_1_27 + i);
1854
1855 for ( j = 0; j < 2; j++ )
1856 {
1857 if ((i == 13) && (j==1))
1858 {
1859 ucSumVal += 0x00;
1860 }
1861 else
1862 {
1863 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1864 }
1865 }
1866 }
1867 break;
1868
1869 case E_HDMITX_AVI_INFOFRAME:
1870 ucSumVal += (E_HDMITX_AVI_INFOFRAME + HDMITX_AVI_INFO_PKT_VER + HDMITX_AVI_INFO_PKT_LEN);
1871
1872 for ( i = 0; i < ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1); i++ )
1873 {
1874 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + i);
1875
1876 for ( j = 0; j < 2; j++ )
1877 {
1878 if ((i == 1) && (j == 0)) // SC[1:0]
1879 {
1880 ucSumVal += (HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)(wRegVal & 0x00FF) & 0x03);
1881 }
1882 else if ((i == 1) && (j == 1)) // VIC[6:0]
1883 {
1884 ucSumVal += ((HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)((wRegVal & 0xFF00) >> 8) & 0x7F) : 0x00);
1885 }
1886 else if ((i == 2) && (j == 0)) // PR[3:0]
1887 {
1888 ucSumVal += (MS_U8)(wRegVal & 0x00FF); //bit 4:7 used for HDR; //ucSumVal += ((MS_U8)(wRegVal & 0x00FF) & 0x0F);
1889 }
1890 #if 0 //not resevered byte anymore; should be counted
1891 else if ((i == 2) && (j == 1)) // reserved
1892 {
1893 ucSumVal += 0x00;
1894 }
1895 #endif
1896 else if (( i == ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1) - 1)&&(j == 1))
1897 {
1898 ucSumVal += 0x00;
1899 }
1900 else
1901 {
1902 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1903 }
1904 }
1905 }
1906 break;
1907
1908 case E_HDMITX_SPD_INFOFRAME:
1909 ucSumVal += (E_HDMITX_SPD_INFOFRAME + HDMITX_SPD_INFO_PKT_VER + HDMITX_SPD_INFO_PKT_LEN);
1910
1911 for ( i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN+ 1) >> 1); i++ )
1912 {
1913 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_SPD_1_15 + i);
1914
1915 for ( j = 0; j < 2; j++ )
1916 {
1917 if ((i == 12) && (j == 0))
1918 {
1919 ucSumVal += (MS_U8)(wRegVal & 0x00FF);
1920 }
1921 else if ((i == 12) && (j == 1)) //reserved
1922 {
1923 ucSumVal += 0x00;
1924 }
1925 else
1926 {
1927 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1928 }
1929 }
1930 }
1931 break;
1932
1933 case E_HDMITX_AUDIO_INFOFRAME:
1934 ucSumVal += (E_HDMITX_AUDIO_INFOFRAME + HDMITX_AUD_INFO_PKT_VER + HDMITX_AUD_INFO_PKT_LEN);
1935
1936 for ( i = 0; i < (((HDMITX_AUD_INFO_PKT_LEN >> 1) + 1) >> 1); i++ )
1937 {
1938 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AUD_1_11 + i);
1939
1940 if (i == 1)
1941 {
1942 for ( j = 0; j < 2; j++ )
1943 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1944 }
1945
1946 if (i == 0)
1947 {
1948 for ( j = 0; j < 2; j++ )
1949 ucSumVal += ( (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xF7) : (((MS_U8)(wRegVal & 0xFF00) >> 8) & 0x1F));
1950 }
1951
1952 if (i == 2)
1953 {
1954 for ( j = 0; j < 2; j++ )
1955 ucSumVal += ((j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xFB) : 0x00);
1956 }
1957 }
1958 break;
1959
1960 case E_HDMITX_MPEG_INFOFRAME:
1961 //TBD
1962 break;
1963
1964 case E_HDMITX_HDR_INFOFRAME:
1965 {
1966 MS_U8 u8PktLen = 0x00;
1967
1968 u8PktLen = (MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0xFF00) >> 8;
1969 ucSumVal += (E_HDMITX_HDR_INFOFRAME + (MS_U8)(MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0x00FF) + u8PktLen);
1970
1971 for ( i = 0; i < ((u8PktLen + 1) >> 1); i++ )
1972 {
1973 wRegVal = MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_10 + i);
1974
1975 for ( j = 0; j < 2; j++ )
1976 {
1977 if ((i == 0x0D) && (j % 2 == 0x00))
1978 ucSumVal += (j % 2 == 0) ? (MS_U8)(wRegVal & 0x00FF) : 0x00;
1979 else
1980 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1981 }
1982 }
1983 }
1984 break;
1985
1986 default:
1987 break;
1988 }
1989
1990 return (MS_U8)((~ucSumVal) + 0x01);
1991
1992 }
1993
1994 //------------------------------------------------------------------------------
1995 /// @brief This routine sets video output mode (color/repetition/regen)
1996 /// @param[in] idx: gHDMITxInfo.output_video_timing
1997 /// @return None
1998 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx,MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val,MsHDMITX_ANALOG_TUNING * pInfo,MS_U8 ubSSCEn)1999 void MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx, MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val, MsHDMITX_ANALOG_TUNING *pInfo, MS_U8 ubSSCEn)
2000 {
2001 //MS_U16 reg_value=0;
2002 MS_U8 ubTimingChanged = TRUE;
2003 MS_U8 ucCDIdx = 0;
2004 MS_U16 wHfront = 0;
2005 MS_U16 wVfront = 0;
2006 MS_BOOL bIsHDMI20 = FALSE;
2007 MS_BOOL bIs420Fmt = FALSE;
2008 MS_BOOL bIsRPMode = FALSE;
2009 MsHDMITX_VIDEO_TIMING eSize_idx = idx;
2010 MS_U32 uiTMDSCLK = 0;
2011
2012 //wilson@kano:TBD
2013 printf("video idx = 0x%X, color depth = 0x%X\r\n", idx, cd_val);
2014 // Deep color FIFO reset
2015 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, BIT10);
2016 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, 0);
2017 MsOS_DelayTask(10);
2018
2019
2020
2021 ucCDIdx = (cd_val == 0)? 0x00 : (cd_val - 4);
2022
2023 // Interlace mode
2024 #if (defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
2025 if (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE)
2026 {
2027 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_2D, 0x0008, 0x0008);
2028 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x005F);
2029 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x4000); //reg_interlace_mode_sel
2030 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0004); // PG interlace enable
2031
2032 if(idx == E_HDMITX_RES_720x480i)
2033 {
2034 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2
2035 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2036 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
2037 }
2038 else if(idx == E_HDMITX_RES_720x576i)
2039 {
2040 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2
2041 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2042 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
2043 }
2044 else if(idx == E_HDMITX_RES_1920x1080i_50Hz)
2045 {
2046 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x01C0); //video,pixel,tmds clock div 2
2047 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0001); //PHY tmds clock div 2
2048 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
2049 }
2050 else if(idx == E_HDMITX_RES_1920x1080i_60Hz)
2051 {
2052 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x01C0); //video,pixel,tmds clock div 2
2053 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0001); //PHY tmds clock div 2
2054 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
2055 }
2056 }
2057 else
2058 {
2059 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_2D, 0x0008, 0x0008);
2060 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x004E);
2061 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x0000); //reg_interlace_mode_sel
2062 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0000); // PG interlace disable
2063
2064 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video clock div 2
2065 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2066 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2067 }
2068 #else
2069 if (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE)
2070 {
2071 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x005F);
2072 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x4000); //reg_interlace_mode_sel
2073 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2
2074 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0004); // PG interlace enable
2075 }
2076 else
2077 {
2078 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x004E);
2079 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x0000); //reg_interlace_mode_sel
2080 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0000); //video clock div 2
2081 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0000); // PG interlace disable
2082 }
2083 #endif
2084
2085 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt != E_HDMITX_VIDEO_COLOR_YUV420) &&
2086 (
2087 (idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || \
2088 (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz) || \
2089 (
2090 (
2091 (idx == E_HDMITX_RES_1280x1470p_60Hz) || \
2092 (idx == E_HDMITX_RES_3840x2160p_24Hz) || \
2093 (idx == E_HDMITX_RES_3840x2160p_25Hz) || \
2094 (idx == E_HDMITX_RES_3840x2160p_30Hz) || \
2095 (idx == E_HDMITX_RES_4096x2160p_24Hz) || \
2096 (idx == E_HDMITX_RES_4096x2160p_25Hz) || \
2097 (idx == E_HDMITX_RES_4096x2160p_30Hz)
2098
2099 ) &&
2100 (
2101 (cd_val != E_HDMITX_VIDEO_CD_24Bits) && (cd_val != E_HDMITX_VIDEO_CD_NoID)
2102 )
2103 )
2104 ))
2105 bIsHDMI20 = TRUE;
2106
2107 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420) &&
2108 ((idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz)) &&
2109 (cd_val != E_HDMITX_VIDEO_CD_24Bits) && (cd_val != E_HDMITX_VIDEO_CD_NoID))
2110 bIsHDMI20 = TRUE;
2111
2112 if (g_bSupportSCDC == TRUE)
2113 {
2114 //for 2.0
2115 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0100, bIsHDMI20 ? 0x0100 : 0x00);
2116 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_52, BIT0, bIsHDMI20 ? BIT0 : 0x00);
2117
2118 //scdc
2119 if (bIsHDMI20 == TRUE)
2120 Mhal_HDMITx_SCDCSetTmdsConfig(TRUE, TRUE);
2121 else
2122 Mhal_HDMITx_SCDCSetTmdsConfig(FALSE, FALSE);
2123 }
2124 else
2125 {
2126 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0100, 0x00);
2127 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_52, BIT0, 0x00);
2128 }
2129
2130
2131 uiTMDSCLK = MHal_HDMITx_GetPixelClk_ByTiming(idx, gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt, cd_val);
2132 uiTMDSCLK /= 1000;
2133
2134 #if (defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1))
2135 if (gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420)
2136 {
2137 if(cd_val > E_HDMITX_VIDEO_CD_24Bits)
2138 {
2139 switch (idx)
2140 {
2141 case E_HDMITX_RES_3840x2160p_50Hz:
2142 idx = E_HDMITX_RES_3840x2160p_25Hz;
2143 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video, pixel,tmds clock div 2 for 420
2144 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2145 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2146 break;
2147
2148 case E_HDMITX_RES_3840x2160p_60Hz:
2149 idx = E_HDMITX_RES_3840x2160p_30Hz;
2150 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video, pixel,tmds clock div 2 for 420
2151 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2152 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2153 break;
2154
2155 case E_HDMITX_RES_4096x2160p_50Hz:
2156 idx = E_HDMITX_RES_4096x2160p_25Hz;
2157 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video, pixel,tmds clock div 2 for 420
2158 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2159 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2160 break;
2161
2162 case E_HDMITX_RES_4096x2160p_60Hz:
2163 idx = E_HDMITX_RES_4096x2160p_30Hz;
2164 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video, pixel,tmds clock div 2 for 420
2165 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2166 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2167 break;
2168
2169 default:
2170 if( idx < E_HDMITX_RES_1920x1080p_50Hz)
2171 {
2172 printf("[HDMITX] Invalid Combination of Color Format & Video Timing, Keep Origional Timing Setting!!\r\n");
2173 }
2174 else
2175 {
2176 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x01C0); //video, pixel,tmds clock div 2 for 420
2177 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0001); //PHY tmds clock div 2
2178 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
2179 }
2180 break;
2181 }
2182 }
2183 else
2184 {
2185 if( idx < E_HDMITX_RES_1920x1080p_50Hz)
2186 {
2187 printf("[HDMITX] Invalid Combination of Color Format & Video Timing, Keep Origional Timing Setting!!\r\n");
2188 }
2189 else
2190 {
2191 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x01C0); //video, pixel,tmds clock div 2 for 420
2192 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0001); //PHY tmds clock div 2
2193 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
2194 }
2195 }
2196
2197 bIs420Fmt = TRUE;
2198 //MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2 for 420
2199
2200 }
2201 else if (HDMITxVideoModeTbl[idx].i_p_mode != E_HDMITX_VIDEO_INTERLACE_MODE)//Not 420
2202 {
2203 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video, pixel,tmds clock div 2 for 420
2204 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2205 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2206 }
2207 #else
2208 if (gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420)
2209 {
2210 switch (idx)
2211 {
2212 case E_HDMITX_RES_3840x2160p_50Hz:
2213 idx = E_HDMITX_RES_3840x2160p_25Hz;
2214 break;
2215
2216 case E_HDMITX_RES_3840x2160p_60Hz:
2217 idx = E_HDMITX_RES_3840x2160p_30Hz;
2218 break;
2219
2220 case E_HDMITX_RES_4096x2160p_50Hz:
2221 idx = E_HDMITX_RES_4096x2160p_25Hz;
2222 break;
2223
2224 case E_HDMITX_RES_4096x2160p_60Hz:
2225 idx = E_HDMITX_RES_4096x2160p_30Hz;
2226 break;
2227
2228 default:
2229 printf("[HDMITX] Invalid Combination of Color Format & Video Timing, Keep Origional Timing Setting!!\r\n");
2230 break;
2231 }
2232
2233 bIs420Fmt = TRUE;
2234 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2 for 420
2235 }
2236 #endif
2237
2238 //Timing Changed Judgement
2239 if( (MHal_HDMITx_Read(HDMITX_VIDEO_REG_BASE, REG_VE_STATUS_15) & 0x3FFF) == HDMITxVideoModeTbl[idx].vtotal)
2240 {
2241 if( MHal_HDMITx_Read(HDMITX_VIDEO_REG_BASE, REG_VE_STATUS_16) == HDMITxVideoModeTbl[idx].htotal)
2242 {
2243 MS_U32 uiSynthSet = 0;
2244 uiSynthSet |= (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0x0FFF);
2245 uiSynthSet = uiSynthSet << 16;
2246 uiSynthSet |= MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02);
2247
2248
2249 if(uiSynthSet == HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet)
2250 {
2251 ubTimingChanged = FALSE;
2252 }
2253 }
2254 }
2255
2256 if((idx == E_HDMITX_RES_720x480i) || (idx == E_HDMITX_RES_720x576i))
2257 {
2258 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x008B);
2259 MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x000F, 0x0001);//Repetition times
2260
2261 bIsRPMode = TRUE;
2262 }
2263 else
2264 {
2265 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x00AC);
2266 MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x000F, 0x0000);//Repetition times
2267
2268 bIsRPMode = FALSE;
2269 }
2270
2271 //enable H, VSync regen
2272 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x8001, 0x8001);
2273 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0002, HDMITxVideoModeTbl[idx].h_polarity ? 0x0002 : 0x0000);
2274 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0004, HDMITxVideoModeTbl[idx].v_polarity ? 0x0004 : 0x0000);
2275
2276 //deep color setting
2277 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00C0, ucCDIdx << 6);
2278
2279 //HDMITx phy clock
2280 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0xCC0C, 0x0000);
2281
2282 #if( (!(defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1))) && (!(defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))) )
2283 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2284 #endif
2285
2286 //sythesizer setting
2287 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, (MS_U16)(HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0000FFFF));
2288 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x0FFF, (MS_U16)((HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0FFF0000) >> 16));
2289
2290 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1003, 0x0000);
2291 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_26, 0x0100, 0x0000);
2292
2293 //atop
2294 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x0003, HDMITxVideoAtopSetting[ucCDIdx][idx].MUX_DIVSEL_POST);
2295 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0xC000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 14);
2296 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x3000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_PIXEL << 12);
2297
2298 #if 0
2299 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
2300 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
2301 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012);
2302 #else //RD suggestion
2303 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, 0x0000);
2304 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, 0x0000);
2305 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, 0x0000);
2306 #endif
2307
2308 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
2309 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
2310 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012);
2311
2312 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x000F, HDMITxVideoAtopSetting[ucCDIdx][idx].PD_RT);
2313
2314
2315 // Timing regeneration
2316 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT10|BIT13, 0x0000/*BIT10|BIT13*/); // 0: delay from DE end; 1: delay from end of h, v sync
2317
2318 #if( (!(defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1))) && (!(defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))) )
2319 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_02, HDMITxVideoModeTbl[idx].vs_width);
2320 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_05, HDMITxVideoModeTbl[idx].vs_delayline);
2321 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_06, HDMITxVideoModeTbl[idx].vs_delaypixel);
2322 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_07, HDMITxVideoModeTbl[idx].hs_width >> (bIs420Fmt ? 0x01 : 0x00));
2323 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_0A, HDMITxVideoModeTbl[idx].hs_delay >> (bIs420Fmt ? 0x01 : 0x00));
2324
2325 //for PG
2326 wHfront = HDMITxVideoModeTbl[idx].hs_delay;
2327 wVfront = HDMITxVideoModeTbl[idx].vs_delayline;
2328
2329 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0003, 0x0003);
2330 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hde_width/4 - 1) : (HDMITxVideoModeTbl[idx].hde_width/2 - 1));
2331 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, (bIs420Fmt||bIsRPMode) ?
2332 ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/4 - 1) : ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/2 - 1));
2333 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (bIs420Fmt||bIsRPMode) ? (wHfront/4 - 1) : (wHfront/2 - 1));
2334 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hs_width/4 - 1) : (HDMITxVideoModeTbl[idx].hs_width/2 - 1));
2335
2336 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_35, HDMITxVideoModeTbl[idx].vde_width - 1);
2337 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_36, (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) ?
2338 ((HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width)/2 - 1) : (HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width - 1));
2339 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_37, wVfront - 1);
2340 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_38, HDMITxVideoModeTbl[idx].vs_width - 1);
2341
2342 #else//444->420 || P2I
2343
2344 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_02, HDMITxVideoModeTbl[eSize_idx].vs_width);
2345 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_05, HDMITxVideoModeTbl[eSize_idx].vs_delayline);
2346 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_06, HDMITxVideoModeTbl[eSize_idx].vs_delaypixel);
2347 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_07, HDMITxVideoModeTbl[eSize_idx].hs_width >> (bIs420Fmt ? 0x01 : 0x00));
2348 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_0A, HDMITxVideoModeTbl[eSize_idx].hs_delay >> (bIs420Fmt ? 0x01 : 0x00));
2349
2350 //for PG
2351 wHfront = HDMITxVideoModeTbl[eSize_idx].hs_delay;
2352 wVfront = HDMITxVideoModeTbl[eSize_idx].vs_delayline;
2353
2354 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0003, 0x0003);
2355 #if (defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1))
2356 if( ( (eSize_idx == E_HDMITX_RES_3840x2160p_60Hz) || (eSize_idx == E_HDMITX_RES_3840x2160p_50Hz) || \
2357 (eSize_idx == E_HDMITX_RES_4096x2160p_50Hz) || (eSize_idx == E_HDMITX_RES_4096x2160p_60Hz)
2358 ) && bIs420Fmt && (cd_val > E_HDMITX_VIDEO_CD_24Bits)
2359 )//4K60 420
2360 {
2361 if( MHal_HDMITx_Read(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31) != (HDMITxVideoModeTbl[eSize_idx].hde_width/4 - 1) )
2362 {
2363 if(ubTimingChanged == FALSE)
2364 {
2365 ubTimingChanged = TRUE;
2366 }
2367 }
2368
2369 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (HDMITxVideoModeTbl[eSize_idx].hde_width/4 - 1) );
2370 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, ((HDMITxVideoModeTbl[eSize_idx].htotal - HDMITxVideoModeTbl[eSize_idx].hde_width)/4 - 1) );
2371 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (wHfront/4 - 1) );
2372 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (HDMITxVideoModeTbl[eSize_idx].hs_width/4 - 1) );
2373 }
2374 else
2375 {
2376 if(bIsRPMode)
2377 {
2378 if( MHal_HDMITx_Read(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31) != (HDMITxVideoModeTbl[eSize_idx].hde_width/4 - 1) )
2379 {
2380 if(ubTimingChanged == FALSE)
2381 {
2382 ubTimingChanged = TRUE;
2383 }
2384 }
2385 }
2386 else
2387 {
2388 if( MHal_HDMITx_Read(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31) != (HDMITxVideoModeTbl[eSize_idx].hde_width/2 - 1) )
2389 {
2390 if(ubTimingChanged == FALSE)
2391 {
2392 ubTimingChanged = TRUE;
2393 }
2394 }
2395 }
2396
2397 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (bIsRPMode) ? (HDMITxVideoModeTbl[eSize_idx].hde_width/4 - 1) : (HDMITxVideoModeTbl[eSize_idx].hde_width/2 - 1));
2398 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, (bIsRPMode) ?
2399 ((HDMITxVideoModeTbl[eSize_idx].htotal - HDMITxVideoModeTbl[eSize_idx].hde_width)/4 - 1) : ((HDMITxVideoModeTbl[eSize_idx].htotal - HDMITxVideoModeTbl[eSize_idx].hde_width)/2 - 1));
2400 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (bIsRPMode) ? (wHfront/4 - 1) : (wHfront/2 - 1));
2401 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (bIsRPMode) ? (HDMITxVideoModeTbl[eSize_idx].hs_width/4 - 1) : (HDMITxVideoModeTbl[eSize_idx].hs_width/2 - 1));
2402 }
2403 #else//Not 444->420
2404 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hde_width/4 - 1) : (HDMITxVideoModeTbl[idx].hde_width/2 - 1));
2405 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, (bIs420Fmt||bIsRPMode) ?
2406 ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/4 - 1) : ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/2 - 1));
2407 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (bIs420Fmt||bIsRPMode) ? (wHfront/4 - 1) : (wHfront/2 - 1));
2408 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hs_width/4 - 1) : (HDMITxVideoModeTbl[idx].hs_width/2 - 1));
2409 #endif
2410
2411 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_35, HDMITxVideoModeTbl[eSize_idx].vde_width - 1);
2412
2413 #if(defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
2414 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_36, (HDMITxVideoModeTbl[eSize_idx].vtotal - HDMITxVideoModeTbl[eSize_idx].vde_width - 1) );
2415 #else
2416 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_36, (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) ?
2417 ((HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width)/2 - 1) : (HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width - 1));
2418 #endif
2419 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_37, wVfront - 1);
2420 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_38, HDMITxVideoModeTbl[eSize_idx].vs_width - 1);
2421
2422 //P2I Setting
2423 #if(defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
2424 if(HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE)
2425 {
2426 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_50, 0x000D, 0x000D);
2427 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_52, wVfront);
2428 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_53, HDMITxVideoModeTbl[eSize_idx].vs_width);
2429 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_54, bIsRPMode ? wHfront/2 : wHfront);
2430 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_55, wHfront ? HDMITxVideoModeTbl[eSize_idx].hs_width/2 : HDMITxVideoModeTbl[eSize_idx].hs_width);
2431 }
2432 else
2433 {
2434 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_50, 0x000D, 0x0000);
2435 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_52, wVfront);
2436 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_53, HDMITxVideoModeTbl[eSize_idx].vs_width);
2437 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_54, bIsRPMode ? wHfront/2 : wHfront);
2438 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_55, wHfront ? HDMITxVideoModeTbl[eSize_idx].hs_width/2 : HDMITxVideoModeTbl[eSize_idx].hs_width);
2439 }
2440 #endif
2441
2442 //444 -> 420
2443 #if (defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1))
2444 if(bIs420Fmt)
2445 {
2446 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_50, 0x0002, 0x0002);
2447 }
2448 else
2449 {
2450 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_50, 0x0002, 0x0000);
2451 }
2452 #endif///444->420
2453
2454 #endif//!444->420 && !P2I
2455
2456 MHal_HDMITx_EnableSSC(ubSSCEn, uiTMDSCLK);
2457
2458 // fifo reset
2459 if(ubTimingChanged)
2460 {
2461 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0x0008);
2462 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0);
2463 }
2464 }
2465
2466 //------------------------------------------------------------------------------
2467 /// @brief This routine will power on or off HDMITx clock (power saving)
2468 /// @param[in] bEnable: TRUE/FALSE
2469 /// @return None
2470 //------------------------------------------------------------------------------
MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)2471 void MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)
2472 {
2473 if (bEnable)
2474 {
2475 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, 0);
2476 }
2477 else
2478 {
2479 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, BIT0);
2480 }
2481 }
2482
2483
MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq,MS_BOOL bflag)2484 MS_BOOL MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq, MS_BOOL bflag)
2485 {
2486 //wilson@kano:TBD
2487 #if 1
2488 return FALSE;
2489 #else
2490 printf("[HDMITx] Bypass Mode = 0x%d\r\n", bflag);
2491 if (bflag == TRUE)
2492 {
2493 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, BIT0); //reg_atop_en_clko_vcodiv8_syn
2494
2495 //Note: change frequency tolerance if need
2496 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2497 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2498 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2499 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2500 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2501 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2502 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //change 250Mhz -> 297Mhz
2503
2504 //Enable Fifo and select input source
2505 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1919); //selct clock from Rx;
2506
2507 #if 0
2508 if (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7A) & 0x00C0) //for HDMI 2.0 timing bypass mode
2509 {
2510 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, BIT0); //tmds clock div 2;
2511 }
2512 #endif
2513
2514 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x000E, 0x0004); //[1:0]: Lane 0 to fifo; [2]: enable
2515 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x000E, 0x0005); //[1:0]: Lane 1 to fifo; [2]: enable
2516 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x000E, 0x0006); //[1:0]: Lane 2 to fifo; [2]: enable
2517 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x000E, 0x0007); //[1:0]: Lane 3 to fifo; [2]: enable
2518
2519 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1000, 0x1000); //bit repetition HW mode;
2520
2521 //synthesizer setting //TBD
2522 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x0001, 0x0001);
2523 //ssc_set = 0x140000
2524 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, 0x0000); //ssc_set [15..0]
2525 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x00FF, 0x0014);//ssc_set [7..0]
2526
2527 #if 0 //with SSC clock
2528 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, ssc_step);
2529 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3000, ssc_span);
2530 #else //without SSC clock
2531 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, 0x0000);
2532 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3FFF, 0x0000);
2533 #endif
2534
2535 //ATOP setting
2536 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00); //[9]:en_clk_pixel;[11]:en_clk_tmds;[13..15]:en_data_out
2537 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0x0000); //[11..0]: disable power down;[15:12]:pre-emphasis
2538 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x007F, 0x000F); //[3:0]:rterm turn off;[6:4]:disable power down
2539 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x2001); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2540 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0200); //[9] hdmi20 hw config mode;
2541 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7E, 0x0200, 0x0200); //[9]: freq range tolerance up direction;
2542 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_60, 0x0001, 0x0001); //[0]: freq range reset follow rx big change;
2543 }
2544 else
2545 {
2546 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2547 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2548 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2549 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2550 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2551 }
2552
2553 return TRUE;
2554
2555 #endif
2556 }
2557
2558
2559 /// @brief This routine will disable TMDS clock, data, and DDC... bypass mode
2560 /// @return None
2561 //------------------------------------------------------------------------------
MHal_HDMITx_Disable_RxBypass(void)2562 MS_BOOL MHal_HDMITx_Disable_RxBypass(void)
2563 {
2564 #if 1
2565 return FALSE;
2566 #else
2567 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2568 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2569 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2570 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2571 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2572
2573 return TRUE;
2574 #endif
2575 }
2576
2577
2578 //------------------------------------------------------------------------------
2579 /// @brief This routine will set GPIO pin for HPD
2580 /// @param[in] u8pin: GPIO0 ~ 12
2581 /// @return None
2582 //------------------------------------------------------------------------------
MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)2583 void MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)
2584 {
2585 printf("_gHPDGpioPin = 0x%X\r\n", u8pin);
2586 _gHPDGpioPin = u8pin;
2587 }
2588
2589 //------------------------------------------------------------------------------
2590 /// @brief This routine return CHIP capability of DVI mode
2591 /// @return TRUE, FALSE
2592 //------------------------------------------------------------------------------
MHal_HDMITx_IsSupportDVIMode(void)2593 MS_BOOL MHal_HDMITx_IsSupportDVIMode(void)
2594 {
2595 return TRUE;
2596 }
2597
2598 // ************* For customer NDS **************//
2599
MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process,MsHDMITX_AVI_CONTENT_TYPE content_type,MS_U16 * data)2600 void MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process, MsHDMITX_AVI_CONTENT_TYPE content_type, MS_U16 *data)
2601 {
2602 MS_U16 tmp_value=0;
2603
2604 if (IS_STOP_PKT(packet_process)) // Stop sending packet
2605 {
2606 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000); // Stop AVI packet
2607 }
2608 else
2609 {
2610 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0080, 0x80); // EIA version 2
2611 switch(content_type)
2612 {
2613 case E_HDMITX_AVI_PIXEL_FROMAT:
2614 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0060, *data);
2615 break;
2616 case E_HDMITX_AVI_ASPECT_RATIO:
2617 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x3F1F, *data);
2618 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0003, *(data+1));
2619 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_4_0C, 0xFFFF, *(data+2));
2620 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_5_0D, 0xFFFF, *(data+3));
2621 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_6_0E, 0xFFFF, *(data+4));
2622 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0xFFFF, *(data+5));
2623 break;
2624 case E_HDMITX_AVI_COLORIMETRY:
2625 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xC000, *data);
2626 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0030, *(data+1));
2627 break;
2628 default:
2629 break;
2630 }
2631
2632 tmp_value = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME); // Checksum
2633 // cyclic packet
2634 if (IS_CYCLIC_PKT(packet_process))
2635 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ( (tmp_value<<8) | (HDMITX_PACKET_AVI_FCNT<<3) | 0x0005)); // send AVI packet
2636 // single packet
2637 else
2638 {
2639 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (tmp_value<<8) | 0x0001);
2640 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1<<E_HDMITX_ACT_AVI_CMD);
2641 }
2642 }
2643 }
2644
2645 //wilson@kano
2646 //**************************************************************************
2647 // [Function Name]:
2648 // MHal_HDMITx_SetGCPParameter()
2649 // [Description]:
2650 // setting General Control packet attribute
2651 // [Arguments]:
2652 // [stGC_PktPara] stPktPara
2653 // [Return]:
2654 // void
2655 //
2656 //**************************************************************************
MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)2657 void MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)
2658 {
2659 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enAVMute = stPktPara.enAVMute;
2660 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enColorDepInfo = stPktPara.enColorDepInfo;
2661 }
2662
2663 //**************************************************************************
2664 // [Function Name]:
2665 // MHal_HDMITx_SetPktAttribute()
2666 // [Description]:
2667 // configure settings to corresponding packet
2668 // [Arguments]:
2669 // [MsHDMITX_PACKET_TYPE] enPktType
2670 // [MS_BOOL] bEnUserDef
2671 // [MS_U8] u8FrmCntNum
2672 // [MsHDMITX_PACKET_PROCESS] enPktCtrl
2673 // [Return]:
2674 // void
2675 //
2676 //**************************************************************************
MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType,MS_BOOL bEnUserDef,MS_U8 u8FrmCntNum,MsHDMITX_PACKET_PROCESS enPktCtrl)2677 void MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType, MS_BOOL bEnUserDef, MS_U8 u8FrmCntNum, MsHDMITX_PACKET_PROCESS enPktCtrl)
2678 {
2679 if (enPktType & 0x80) //infoframe packet type
2680 {
2681 gbInfoFrmPktList[enPktType & (~0x80)].EnableUserDef = bEnUserDef;
2682 gbInfoFrmPktList[enPktType & (~0x80)].FrmCntNum = u8FrmCntNum;
2683 gbInfoFrmPktList[enPktType & (~0x80)].enPktCtrl = enPktCtrl;
2684 }
2685 else
2686 {
2687 gbGeneralPktList[enPktType].EnableUserDef = bEnUserDef;
2688 gbGeneralPktList[enPktType].FrmCntNum = u8FrmCntNum;
2689 gbGeneralPktList[enPktType].enPktCtrl = enPktCtrl;
2690 }
2691 }
2692
2693 //**************************************************************************
2694 // [Function Name]:
2695 // MHal_HDMITx_SetAVIInfoParameter()
2696 // [Description]:
2697 // Assign content to AVI Infoframe packet
2698 // [Arguments]:
2699 // [stAVIInfo_PktPara] stPktPara
2700 // [Return]:
2701 // void
2702 //
2703 //**************************************************************************
MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)2704 void MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)
2705 {
2706 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.A0Value = stPktPara.A0Value;
2707 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enableAFDoverWrite = stPktPara.enableAFDoverWrite;
2708 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorFmt = stPktPara.enColorFmt;
2709 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorimetry = stPktPara.enColorimetry;
2710 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enExtColorimetry = stPktPara.enExtColorimetry;
2711 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enYCCQuantRange = stPktPara.enYCCQuantRange;
2712 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enVidTiming = stPktPara.enVidTiming;
2713 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAFDRatio = stPktPara.enAFDRatio;
2714 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enScanInfo = stPktPara.enScanInfo;
2715 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAspectRatio = stPktPara.enAspectRatio;
2716 }
2717
2718 //**************************************************************************
2719 // [Function Name]:
2720 // MHal_HDMITx_SetVSInfoParameter()
2721 // [Description]:
2722 // Assign content to VendorSpecific Infoframe packet
2723 // [Arguments]:
2724 // [stVSInfo_PktPara] stPketPara
2725 // [Return]:
2726 // void
2727 //
2728 //**************************************************************************
MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)2729 void MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)
2730 {
2731 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en3DStruct = stPktPara.en3DStruct;
2732 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en4k2kVIC = stPktPara.en4k2kVIC;
2733 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.enVSFmt = stPktPara.enVSFmt;
2734 }
2735
2736 //**************************************************************************
2737 // [Function Name]:
2738 // MHal_HDMITx_SetVSInfoParameter()
2739 // [Description]:
2740 // Assign content to VendorSpecific Infoframe packet
2741 // [Arguments]:
2742 // [stVSInfo_PktPara] stPketPara
2743 // [Return]:
2744 // void
2745 //
2746 //**************************************************************************
MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)2747 void MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)
2748 {
2749 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudChCnt = stPktPara.enAudChCnt;
2750 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudType = stPktPara.enAudType;
2751 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudFreq = stPktPara.enAudFreq;
2752 }
2753
2754 //**************************************************************************
2755 // [Function Name]:
2756 // MHal_HDMITx_SendPacket()
2757 // [Description]:
2758 // configure packet content and process according to user define or defalut setting
2759 // [Arguments]:
2760 // [MsHDMITX_PACKET_TYPE] enPktType
2761 // [Return]:
2762 // void
2763 //
2764 //**************************************************************************
MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType,MsHDMITX_PACKET_PROCESS packet_process)2765 void MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType, MsHDMITX_PACKET_PROCESS packet_process)
2766 {
2767 if (enPktType & 0x80) //info frame packet
2768 {
2769 MS_U8 ucInfoPktType = enPktType & (~0x80);
2770 MS_U8 ucChkSum = 0;
2771
2772 gbInfoFrmPktList[ucInfoPktType].enPktCtrl = packet_process;
2773
2774 switch (enPktType)
2775 {
2776 case E_HDMITX_VS_INFOFRAME:
2777 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2778 {
2779 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, 0x0005, 0x0000);
2780 }
2781 else
2782 {
2783 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2784 {
2785 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2786
2787 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2788 {
2789 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2790 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2791 }
2792 else
2793 {
2794 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2795 }
2796 }
2797 else
2798 {
2799 //fill IEEE HDMI tag
2800 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27, 0xFFFF, 0x0C03);
2801
2802 //check content
2803 if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_3D)
2804 {
2805 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_3D << 13); // video format
2806 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en3DStruct) << 4); // 3D structure
2807 }
2808 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_4k_2k)
2809 {
2810 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_4k_2k << 13); // video format
2811 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en4k2kVIC)); // 4k2k vic
2812 }
2813 else
2814 {
2815 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, 0); // video format
2816 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, 0);
2817 }
2818
2819 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2820
2821 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2822 {
2823 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2824 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2825 }
2826 else
2827 {
2828 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum << 8) | (HDMITX_PACKET_VS_FCNT << 3) | 0x0005));
2829 }
2830 }
2831 }
2832 break;
2833
2834 case E_HDMITX_AVI_INFOFRAME:
2835 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2836 {
2837 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000);
2838 }
2839 else
2840 {
2841 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2842 {
2843 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
2844
2845 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2846 {
2847 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
2848 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
2849 }
2850 else
2851 {
2852 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2853 }
2854 }
2855 else
2856 {
2857 MS_U8 ucPktVal = 0;
2858
2859 //Y2, Y1, Y0: RGB, YCbCr 422, 444, 420
2860 ucPktVal = (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt << 5);// | 0x10;
2861 //A0 field
2862 ucPktVal |= ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.A0Value == 0x01) ? 0x10 : 0x00);
2863 //S1, S0 field
2864 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enScanInfo);
2865
2866 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x00FF, (MS_U16)ucPktVal); //MDrv_WriteByte(REG_HDMITX_09_L, ucPktVal);
2867
2868 //C1, C0, M1, M0
2869 if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2870 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p))
2871 {
2872 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2873 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio << 4);
2874 }
2875 else
2876 {
2877 //HD timing is always 16:9
2878 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2879 }
2880
2881 //R3, R2, R1, R0: active porting aspect ration
2882 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enableAFDoverWrite == TRUE)
2883 {
2884 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAFDRatio & 0x0F);
2885 }
2886
2887 //ucPktVal |= ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry == 0) ? 0 : 0xC0; //set [C1, C0] = [1, 1]
2888
2889 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorimetry != E_HDMITX_COLORIMETRY_MAX)
2890 {
2891 ucPktVal = (ucPktVal & 0x3F) | ( ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorimetry & 0x03) << 6);
2892 }
2893
2894 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xFF00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_09_H, ucPktVal);
2895
2896 //EC0, EC1, EC2
2897 ucPktVal = (MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry;
2898 ucPktVal = (ucPktVal > 6) ? 6 : ucPktVal; //BT2020 RGB & BT2020 YCbCr share same value 6; 7 is reserved;
2899 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0070, ucPktVal << 4); //MDrv_WriteByteMask(REG_HDMITX_0A_L, ucPktVal << 4, 0x70);
2900
2901 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_RGB444)
2902 {
2903 //Q1, Q0
2904 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2905 {
2906 ucPktVal = 1;
2907 }
2908 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2909 {
2910 ucPktVal = 2;
2911 }
2912 else
2913 {
2914 ucPktVal = 0;
2915 }
2916
2917 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, ucPktVal << 2);
2918 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, 0x00);
2919 }
2920 else
2921 {
2922 //YQ1, YQ0
2923 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2924 {
2925 ucPktVal = 0;
2926 }
2927 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2928 {
2929 ucPktVal = 1;
2930 }
2931 else
2932 {
2933 ucPktVal = 3;
2934 }
2935
2936 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, 0x00);
2937 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, ucPktVal << 6);
2938 }
2939
2940 //VIC code: VIC code shoud +1 if aspect ration is 16:9
2941 ucPktVal = HDMITX_AviVicTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2942
2943 if (((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2944 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p)) &&
2945 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_16_9))
2946 {
2947 ucPktVal += 1;
2948 }
2949 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_21_9)
2950 {
2951 MS_U8 AR21_9MappingTbl[14][2] = {
2952 {60, 65},
2953 {61, 66},
2954 {62, 67},
2955 {19, 68},
2956 { 4, 69},
2957 {41, 70},
2958 {47, 71},
2959 {32, 72},
2960 {33, 73},
2961 {34, 74},
2962 {31, 75},
2963 {16, 76},
2964 {64, 77},
2965 {63, 78}
2966 };
2967
2968 if ((ucPktVal >= 93) && (ucPktVal <= 97))//3840*2160p@24 ~ 3840*2160@60
2969 {
2970 ucPktVal += 10;
2971 }
2972 else if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_3840x2160p_24Hz) &&\
2973 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_3840x2160p_30Hz))
2974 {
2975 ucPktVal += (103 + (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming - E_HDMITX_RES_3840x2160p_24Hz));
2976 }
2977 else if ((ucPktVal > 78) && (ucPktVal <= 92))
2978 {
2979 //do nothing;
2980 }
2981 else
2982 {
2983 MS_U8 i = 0;
2984 MS_BOOL bValidVIC = FALSE;
2985
2986 for ( i = 0; i < 14; i++ )
2987 {
2988 if (AR21_9MappingTbl[i][0] == ucPktVal)
2989 {
2990 ucPktVal = AR21_9MappingTbl[i][1];
2991 bValidVIC = TRUE;
2992 break;
2993 }
2994 }
2995
2996 if (!bValidVIC)
2997 {
2998 printf("%s :: Invalid VIC Code for 21:9 Aspect Ratio!!!\r\n", __FUNCTION__);
2999 }
3000 }
3001 }
3002
3003 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x7F00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_0A_H, (ucPktVal & 0x7F));
3004
3005 //check repetition
3006 if ((HDMITxVideoModeTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) &&
3007 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576i))
3008 {
3009 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0001); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x01, 0x0F);
3010 }
3011 else
3012 {
3013 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x00, 0x0F);
3014 }
3015
3016 //YQ1, YQ0
3017 //MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, (MS_U8)(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange << 6));
3018
3019 //AVI version
3020 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0x0300, (MS_U16)(HDMITX_AVI_INFO_PKT_VER << 8));
3021 //MDrv_WriteByteMask(REG_HDMITX_0F_H, HDMITX_AVI_INFO_PKT_VER, 0x03);
3022
3023 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
3024
3025 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3026 {
3027 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
3028 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
3029 }
3030 else
3031 {
3032 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3) | 0x0005));
3033 //MDrv_Write2Byte(REG_HDMITX_10_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3));
3034 }
3035 }
3036 }
3037 break;
3038
3039 case E_HDMITX_SPD_INFOFRAME:
3040 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
3041 {
3042 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, 0x0005, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_22_L, 0x00, 0x05);
3043 }
3044 else
3045 {
3046 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
3047 {
3048 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
3049
3050 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3051 {
3052 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
3053 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
3054 }
3055 else
3056 {
3057 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
3058 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3));
3059 }
3060 }
3061 else
3062 {
3063 MS_U8 i = 0;
3064 MS_U8 ucPktVal = 0;
3065
3066 for (i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN + 1) >> 1); i++)
3067 {
3068 if (i < 4) // vendor name
3069 {
3070 ucPktVal = (HDMITX_VendorName[2*i+1]<<8) | HDMITX_VendorName[2*i];
3071 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+i, 0x7F7F, ucPktVal);
3072 }
3073 else if ((i >= 4) && (i < 12)) // product description
3074 {
3075 ucPktVal = (HDMITX_ProductName[2*(i-4)+1]<<8) | HDMITX_ProductName[2*(i-4)];
3076 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_5_19+(i-4), 0x7F7F, ucPktVal);
3077 }
3078 else // source device information
3079 {
3080 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_13_21, 0x00FF, HDMITX_PACKET_SPD_SDI);
3081 }
3082 }
3083
3084 #if 0
3085 for ( i = 0; i < (HDMITX_SPD_INFO_PKT_LEN - 1); i++ )
3086 {
3087 if ( i < 8 )
3088 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_VendorName[i]);
3089 else
3090 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_ProductName[i-8]);
3091 }
3092
3093 MDrv_WriteByte(REG_HDMITX_21_L, 0x01); //SPD infoframe, byte25: source information: 0x01 = Digital STB
3094 #endif
3095
3096 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
3097
3098 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3099 {
3100 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
3101 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
3102 }
3103 else
3104 {
3105 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3) | 0x0005));
3106 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3));
3107 }
3108 }
3109 }
3110
3111 break;
3112
3113 case E_HDMITX_AUDIO_INFOFRAME:
3114 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
3115 {
3116 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, 0x0005, 0x0000);
3117 }
3118 else
3119 {
3120 // Modified for HDMI CTS test -
3121 // - Audio Coding Type (CT3~CT0) is 0x0 then continue else then FAIL
3122 // - Sampling Frequency (SF2~ SF0) is zero then continue else then FAIL.
3123 // - Sample Size (SS1~ SS0) is zero then continue else then FAIL.
3124 //tmp_value = (gHDMITxInfo.output_audio_frequncy << 10) | 0x11; // audio sampling frequency, PCM and 2 channel.
3125 //MHal_HDMITx_Mask_Write(REG_HDMITX_BANK1, REG_PKT_AUD_1_11, 0x1FFF, tmp_value);
3126
3127 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt == E_HDMITX_AUDIO_CH_2) // 2-channel
3128 {
3129 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_2 - 1) & 0x07); // 2 channels
3130 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0); // Channel allocation
3131 }
3132 else //8- channel
3133 {
3134 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_8 - 1)&0x07); // 8 channels
3135 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0x1F00); // Channel allocation
3136 }
3137 //clear LFEP value
3138 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_3_13, 0x0001, 0x0000); //Fix LFEP defalut value in Kappa.
3139
3140 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AUDIO_INFOFRAME);
3141
3142 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3143 {
3144 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, (ucChkSum << 8) | 0x0001);
3145 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AUD_CMD);
3146 }
3147 else
3148 {
3149 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
3150 {
3151 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
3152 }
3153 else
3154 {
3155 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (HDMITX_PACKET_AUD_FCNT << 3) | 0x0005));
3156 }
3157 }
3158 }
3159
3160 //NOTE:: Kano move channel status from 0x00 to 0x0A
3161 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == FALSE)
3162 {
3163 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudType == E_HDMITX_AUDIO_PCM) ? 0 : BIT1)); // [1]: PCM / non-PCM
3164 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudFreq].CH_Status3 << 8) | (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
3165 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
3166 }
3167 // Audio sampling frequency
3168 // 1 1 0 0 32 kHz
3169 // 0 0 0 0 44.1 kHz
3170 // 0 0 0 1 88.2 kHz
3171 // 0 0 1 1 176.4 kHz
3172 // 0 1 0 0 48 kHz
3173 // 0 1 0 1 96 kHz
3174 // 0 1 1 1 192 kHz
3175 // 1 0 0 1 768 kHz
3176 break;
3177
3178 case E_HDMITX_MPEG_INFOFRAME:
3179 //TBD
3180 break;
3181
3182 case E_HDMITX_HDR_INFOFRAME:
3183 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
3184 {
3185 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000);
3186 }
3187 else
3188 {
3189 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
3190 {
3191 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
3192
3193 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3194 {
3195 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
3196 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
3197 }
3198 else
3199 {
3200 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
3201 }
3202 }
3203 else
3204 {
3205 //TBD
3206 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
3207
3208 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3209 {
3210 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
3211 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
3212 }
3213 else
3214 {
3215 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCNT << 3) | 0x0005));
3216 }
3217
3218 }
3219 }
3220 break;
3221
3222 default:
3223 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
3224 break;
3225 }
3226 }
3227 else //general packet
3228 {
3229 gbGeneralPktList[enPktType].enPktCtrl = packet_process;
3230
3231 switch (enPktType)
3232 {
3233 case E_HDMITX_NULL_PACKET:
3234 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
3235 {
3236 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x0005, 0x0000);
3237 }
3238 else
3239 {
3240 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3241 {
3242 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, 0x0001);
3243 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_NUL_CMD);
3244 }
3245 else
3246 {
3247 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3248 {
3249 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 3) |0x0005) );
3250 }
3251 else
3252 {
3253 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((HDMITX_PACKET_NULL_FCNT << 3) |0x0005) );
3254 }
3255 }
3256 }
3257 break;
3258
3259 case E_HDMITX_ACR_PACKET:
3260 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
3261 {
3262 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x000F, 0x0008);
3263 }
3264 else
3265 {
3266 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3267 {
3268 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, 0x0009);
3269 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACR_CMD);
3270 }
3271 else //cyclic
3272 {
3273 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3274 {
3275 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 4) |0x05));
3276 }
3277 else
3278 {
3279 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((HDMITX_PACKET_ACR_FCNT << 4) |0x05));
3280 }
3281 }
3282 }
3283 break;
3284
3285 case E_HDMITX_AS_PACKET:
3286 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
3287 {
3288 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable audio FIFO, [0]:audio FIFO flush
3289 }
3290 else
3291 {
3292 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT7); // [7]: enable audio FIFO, [0]:audio FIFO not flush
3293 }
3294 break;
3295
3296 case E_HDMITX_GC_PACKET:
3297 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
3298 {
3299 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x000F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | 0x0000);
3300 }
3301 else
3302 {
3303 //fill color depth information
3304 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC12_04, 0x010F, gbGeneralPktList[enPktType].PktPara.GCPktPara.enColorDepInfo); // [8]: default phase = 0, [3:0]: Color depth
3305
3306 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3307 {
3308 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1)| 0x21); // [6]: 0, DC and non-DC info send together
3309 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_GCP_CMD);
3310 //MDrv_WriteByteMask(REG_HDMITX_03_L, 0x21, 0x7F);
3311 }
3312 else //cyclic
3313 {
3314 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3315 {
3316 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (gbGeneralPktList[enPktType].FrmCntNum << 4) | 0x29));
3317 }
3318 else
3319 {
3320 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (HDMITX_PACKET_GC_FCNT << 4) | 0x29));
3321 }
3322 }
3323 }
3324 break;
3325
3326 case E_HDMITX_ACP_PACKET:
3327 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
3328 {
3329 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0005, 0x0000);
3330 }
3331 else
3332 {
3333 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_0_38, 0xFFFF, 0x0000); //acp type is 0x00
3334
3335 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3336 {
3337 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0001);
3338 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACP_CMD);
3339 }
3340 else //cyclic
3341 {
3342 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3343 {
3344 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
3345 }
3346 else
3347 {
3348 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, (HDMITX_PACKET_ACP_FCNT | 0x0005));
3349 }
3350 }
3351 }
3352 break;
3353
3354 case E_HDMITX_ISRC1_PACKET:
3355 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
3356 {
3357 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
3358 }
3359 else
3360 {
3361 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3362 {
3363 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0001);
3364 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
3365 }
3366 else //cyclic
3367 {
3368 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3369 {
3370 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005)); }
3371 else
3372 {
3373 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
3374 }
3375 }
3376 }
3377 break;
3378
3379 case E_HDMITX_ISRC2_PACKET:
3380 //check ISRC cnt value
3381 if (MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51) & 0x8000)
3382 {
3383 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
3384 {
3385 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
3386 }
3387 else
3388 {
3389 MS_U8 u8ISRCCntVal = 0x80;
3390
3391 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3392 {
3393 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, (u8ISRCCntVal << 8) | 0x0001 ); // 0x80: ISRC_CONT = 1, ISRC1 & ISRC2
3394 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
3395 }
3396 else //cyclic
3397 {
3398 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3399 {
3400 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
3401 }
3402 else
3403 {
3404 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
3405 }
3406 }
3407 }
3408 }
3409 break;
3410
3411 case E_HDMITX_DSD_PACKET:
3412 //TBD
3413 break;
3414
3415 case E_HDMITX_HBR_PACKET:
3416 //TBD
3417 break;
3418
3419 case E_HDMITX_GM_PACKET:
3420 //TBD
3421 break;
3422
3423 default:
3424 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
3425 break;
3426 }
3427 }
3428 }
3429
MHal_HDMITx_EnableSSC(MS_BOOL bEnable,MS_U32 uiTMDSCLK)3430 void MHal_HDMITx_EnableSSC(MS_BOOL bEnable, MS_U32 uiTMDSCLK)
3431 {
3432 //Maxim does not implement SSC yet.
3433 #if 0
3434 #define HDMITX_MPLL_CLK 432 //432MHz
3435 #define HDMITX_SSC_CLK 30 //30KHz
3436 #define HDMITX_SSC_DEVIATION 1 // 0.1%
3437 #define HDMITX_SSC_DEVIATION_DIVIDER 1000
3438 #define HDMITX_SSC_THREAD_LEVEL1 150 ///1080p 8bits
3439 #define HDMITX_SSC_THREAD_LEVEL2 300 ///4K30 8bits
3440 #define HDMITX_SSC_SPAN_REG REG_HDMITxPHY_CONFIG_06
3441 #define HDMITX_SSC_STEP_REG REG_HDMITxPHY_CONFIG_07
3442 #define HDMITX_SSC_SUB_DIVIDER_REG REG_HDMITxPHY_CONFIG_01
3443
3444 MS_U32 ub2x19times = 524288;// 2^ 19
3445 MS_U32 dSYNCLK = 1;
3446 MS_U32 ub432MHz = HDMITX_MPLL_CLK;
3447 MS_U32 ubSSCClk = HDMITX_SSC_CLK;
3448 MS_U32 dSSc_Deviation= HDMITX_SSC_DEVIATION;
3449 MS_U32 ubSYNSet = 0;
3450 MS_U32 dSSC_Span = 0;
3451 MS_U32 dSSC_Step = 0;
3452 MS_U32 dPixel_Clk = 0;
3453
3454 if(!bEnable)
3455 {
3456 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, 0 );//Span
3457 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, 0);//Step
3458 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0 );//Sub-Divider
3459 return;
3460 }
3461
3462 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02);
3463 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16);
3464
3465 if(ubSYNSet != 0)
3466 dSYNCLK = ((ub432MHz*ub2x19times)/ubSYNSet);
3467
3468 if(ubSSCClk != 0)
3469 dSSC_Span = (dSYNCLK * 250) / (ubSSCClk); //Span = SYN_CLK_KHz / (SSC_CLK_KHz * 4)
3470
3471 if( (dSSC_Span != 0) && (HDMITX_SSC_DEVIATION_DIVIDER != 0) )
3472 dSSC_Step = (((ubSYNSet/ dSSC_Span)/HDMITX_SSC_DEVIATION_DIVIDER) * dSSc_Deviation) ; //Step = SYN_SET * deviation / Span
3473
3474 printf("ubSYNSet=%x, dSYNCLK=%d, dSSC_Span=%d, dSSC_Step=%d\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dSSC_Step);
3475
3476 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, ( ((int)dSSC_Span) & 0x3FFF) );//Span
3477 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, ( ((int)dSSC_Step) & 0xFFFF) );//Step
3478
3479 //Read tmds clock
3480 #if 0
3481 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_20, 0x3F, 0x3F);
3482 dPixel_Clk = ((MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_21) << 1) * 12 / 128);
3483 #else
3484 dPixel_Clk = uiTMDSCLK;
3485 #endif
3486 printf("dPixel_Clk=%d\r\n", dPixel_Clk);
3487
3488 if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL1)
3489 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x0000 );//Sub-Divider
3490 else if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL2)
3491 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x1000 );//Sub-Divider
3492 else
3493 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x3000 );//Sub-Divider
3494
3495 #endif
3496 }
3497
MHal_HDMITx_GetPixelClk_ByTiming(MsHDMITX_VIDEO_TIMING idx,MsHDMITX_VIDEO_COLOR_FORMAT color_fmt,MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth)3498 MS_U32 MHal_HDMITx_GetPixelClk_ByTiming(MsHDMITX_VIDEO_TIMING idx, MsHDMITX_VIDEO_COLOR_FORMAT color_fmt, MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth)
3499 {
3500 MS_U32 dwTMDSDataRate = 0;
3501 MS_U8 ubBitNum = 8;
3502
3503 switch(color_depth)
3504 {
3505 case E_HDMITX_VIDEO_CD_NoID:
3506 case E_HDMITX_VIDEO_CD_24Bits:
3507 {
3508 ubBitNum = 8;
3509 }
3510 break;
3511
3512 case E_HDMITX_VIDEO_CD_30Bits:
3513 {
3514 ubBitNum = 10;
3515 }
3516 break;
3517
3518 case E_HDMITX_VIDEO_CD_36Bits:
3519 {
3520 ubBitNum = 12;
3521 }
3522 break;
3523
3524 case E_HDMITX_VIDEO_CD_48Bits:
3525 {
3526 ubBitNum = 16;
3527 }
3528 break;
3529
3530 default:
3531 {
3532 ubBitNum = 8;
3533 }
3534 break;
3535 }
3536
3537 dwTMDSDataRate = (HDMITxVideoModeTbl[idx].pixel_clk/1000) * ubBitNum / 8;
3538
3539 if(color_fmt == E_HDMITX_VIDEO_COLOR_YUV420)
3540 dwTMDSDataRate = dwTMDSDataRate/2;
3541
3542 //printf("Time_ID = %d, C_FMT = %d, C_DEP = %d, PXL_CLK = %d\r\n", idx, color_fmt, color_depth, dwTMDSDataRate);
3543 return dwTMDSDataRate;
3544 }
3545
MHal_HDMITx_GetMaxPixelClk(void)3546 MS_U32 MHal_HDMITx_GetMaxPixelClk(void)
3547 {
3548 return HDMITX_MAX_PIXEL_CLK/1000;
3549 }
3550