1 //<MStar Software>
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #define MHAL_HDMITX_C
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 // Common Definition
101 #ifdef MSOS_TYPE_LINUX_KERNEL
102 #include <linux/string.h>
103 #else
104 #include <string.h>
105 #endif
106
107 #include "MsCommon.h"
108
109 // Internal Definition
110 #include "regHDMITx.h"
111 #include "halHDMIUtilTx.h"
112 #include "halHDMITx.h"
113 #include "drvHDMITx.h"
114
115 // External Definition
116 #include "drvGPIO.h"
117 #include "drvSYS.h"
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126
127 #define GENERAL_PKT_NUM 0x0BU //wilson@kano
128 #define INFOFRM_PKT_NUM 0x08U //for HDR packet ID = 0x87; 0x06U //wilson@kano
129
130
131 #define HDMITX_VS_INFO_PKT_VER 0x01U
132 #define HDMITX_VS_INFO_PKT_LEN 0x1BU
133
134 #define HDMITX_AVI_INFO_PKT_VER 0x02U
135 #define HDMITX_AVI_INFO_PKT_LEN 0x0DU
136
137 #define HDMITX_SPD_INFO_PKT_VER 0x01U
138 #define HDMITX_SPD_INFO_PKT_LEN 0x19U
139
140 #define HDMITX_AUD_INFO_PKT_VER 0x01U
141 #define HDMITX_AUD_INFO_PKT_LEN 0x0AU
142
143 #define HDMITX_HDR_INFO_PKT_VER 0x01U
144 #define HDMITX_HDR_INFO_PKT_LEN 0x1BU //wilson@kano: temp solution
145
146
147
148 #define IS_STOP_PKT(_X_) ( (_X_ & E_HDMITX_STOP_PACKET) ? 1 : 0 )
149 #define IS_CYCLIC_PKT(_X_) ( (_X_ & E_HDMITX_CYCLIC_PACKET) ? 1 : 0 )
150
151 // HDMI packet cyclic frame count
152 #define HDMITX_PACKET_NULL_FCNT 0U ///< 0 ~ 31
153 #define HDMITX_PACKET_ACR_FCNT 0U ///< 0 ~ 15
154 #define HDMITX_PACKET_GC_FCNT 0U ///< 0 ~ 1
155 #define HDMITX_PACKET_ACP_FCNT 15U ///< 0 ~ 31
156 #define HDMITX_PACKET_ISRC_FCNT 15U ///< 0 ~ 31
157
158 #define HDMITX_PACKET_VS_FCNT 0U ///< 0 ~ 31
159 #define HDMITX_PACKET_AVI_FCNT 0U ///< 0 ~ 31
160 #define HDMITX_PACKET_SPD_FCNT 1U ///< 0 ~ 31
161 #define HDMITX_PACKET_AUD_FCNT 0U ///< 0 ~ 31
162 #define HDMITX_PACKET_HDR_FCNT 0U
163
164 #define HDMITX_PACKET_SPD_SDI 1U // Digital STB
165 #define HDMITX_CSC_SUPPORT_R2Y 1U
166
167 #define HDMITX_MAX_PIXEL_CLK 597000000 //Max cupported pixel clock
168
169 //-------------------------------------------------------------------------------------------------
170 // Local Structures
171 //-------------------------------------------------------------------------------------------------
172
173 //*********************//
174 // Video //
175 //*********************//
176
177 typedef struct
178 {
179 MDrv_HDMITx_VIDEO_MODE i_p_mode; // interlace / progressive mode
180 MDrv_HDMITx_VIDEO_POLARITY h_polarity; // Hsync polarity
181 MDrv_HDMITx_VIDEO_POLARITY v_polarity; // Vsync polarity
182 MS_U16 vs_width; // Vsync pulse width
183 MS_U16 vs_bporch; // Vsync back-porch
184 MS_U16 vde_width; // Vde active width
185 MS_U16 vs_delayline; // Vsync line delay
186 MS_U16 vs_delaypixel; // Vsync pixel delay
187 MS_U16 hs_width; // Hsync pulse width
188 MS_U16 hs_bporch; // Hsync back-porch
189 MS_U16 hde_width; // Hde active width
190 MS_U16 hs_delay; // Hsync delay
191 MS_U16 vtotal; // Vsync total
192 MS_U16 htotal; // Hsync total
193 MS_U16 frame_rate; // Frame Rate
194 MS_U32 pixel_clk; //pixel clock
195 } MDrv_HDMITx_VIDEO_MODE_INFO_TYPE;
196
197 //*********************//
198 // Packet //
199 //*********************//
200
201 typedef enum
202 {
203 E_HDMITX_ACT_GCP_CMD = 0,
204 E_HDMITX_ACT_ACR_CMD = 1,
205 E_HDMITX_ACT_AVI_CMD = 2,
206 E_HDMITX_ACT_AUD_CMD = 3,
207 E_HDMITX_ACT_SPD_CMD = 4,
208 E_HDMITX_ACT_MPG_CMD = 5,
209 E_HDMITX_ACT_VSP_CMD = 6,
210 E_HDMITX_ACT_NUL_CMD = 7,
211 E_HDMITX_ACT_ACP_CMD = 8,
212 E_HDMITX_ACT_ISRC_CMD = 9,
213 E_HDMITX_ACT_GCP_DC_CMD = 10, // GCP with non-zero CD
214 E_HDMITX_ACT_GMP_CMD = 11, // Gamut Metadata packet
215 } MDrvHDMITX_PKTS_ACT_CMD;
216
217 typedef struct PKT
218 {
219 MS_BOOL User_Define;
220 MsHDMITX_PACKET_PROCESS Define_Process;
221 MS_U8 Define_FCnt;
222 }PKT_Behavior;
223 //*********************//
224 // Audio //
225 //*********************//
226 typedef struct
227 {
228 MS_U8 CH_Status3;
229 MS_U32 NcodeValue;
230 } MDrv_HDMITx_AUDIO_FREQ_TYPE;
231
232 //-------------------------------------------------------------------------------------------------
233 // Global Variables
234 //-------------------------------------------------------------------------------------------------
235 MS_U8 gDivider = 0x00;
236 MS_BOOL gDivFlag = FALSE;
237 static MS_U8 gu8ChipVerNum = 0x00;
238 MS_BOOL g_bSupportSCDC = FALSE;
239
240 stHDMITx_PKT_ATTRIBUTE gbGeneralPktList[GENERAL_PKT_NUM]; //wilson@kano
241 stHDMITx_PKT_ATTRIBUTE gbInfoFrmPktList[INFOFRM_PKT_NUM]; //wilson@kano
242
243 // User defined packet behavior
244 PKT_Behavior NULL_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
245 PKT_Behavior ACR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
246 PKT_Behavior AS_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
247 PKT_Behavior GC_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
248 PKT_Behavior ACP_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
249 PKT_Behavior ISRC1_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
250 PKT_Behavior ISRC2_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
251 PKT_Behavior DSD_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
252 PKT_Behavior HBR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
253 PKT_Behavior GM_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
254
255 PKT_Behavior VS_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
256 PKT_Behavior AVI_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
257 PKT_Behavior SPD_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
258 PKT_Behavior AUDIO_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
259 PKT_Behavior MPEG_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
260 //-------------------------------------------------------------------------------------------------
261 // Local Variables
262 //-------------------------------------------------------------------------------------------------
263
264 //*********************//
265 // Video //
266 //*********************//
267
268 // It should be mapped with MsHDMITX_VIDEO_TIMING structure in drvHDMITx.h
269 MDrv_HDMITx_VIDEO_MODE_INFO_TYPE HDMITxVideoModeTbl[E_HDMITX_RES_MAX]=
270 {
271 //IorPMode; PolarityH; PolarityV; VSW; VbckP; VDe; VSDel; VSDelP; HSW; HbckP; HDe; HSDel; VSTotal; HSTotal;
272 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0002, 0x0021, 0x01E0, 0x000A, 0, 0x0060, 0x0030, 0x0280, 0x0010, 0x020D, 0x0320, 60, 25175000}, // 0: 640x480p
273 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x000F, 0x01E0, 0x0004, 0, 0x007C, 0x0072, 0x05A0, 0x0026, 0x020D, 0x06B4, 60, 27000000}, // 1: 720x480i
274 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x0013, 0x0240, 0x0002, 0, 0x007E, 0x008A, 0x05A0, 0x0018, 0x0271, 0x06C0, 50, 27000000}, // 2: 720x576i
275 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0006, 0x001E, 0x01E0, 0x0009, 0, 0x003E, 0x003C, 0x02D0, 0x0010, 0x020D, 0x035A, 60, 27000000}, // 3: 720x480p
276 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0005, 0x0027, 0x0240, 0x0005, 0, 0x0040, 0x0044, 0x02D0, 0x000C, 0x0271, 0x0360, 50, 27000000}, // 4: 720x576p
277 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x02EE, 0x07BC, 50, 74250000}, // 5: 1280x720p_50Hz
278 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x02EE, 0x0672, 60, 74250000}, // 6: 1280x720p_60Hz
279 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 50, 74250000}, // 7: 1920x1080i_50Hz
280 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 60, 74250000}, // 8: 1920x1080i_60Hz
281 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x0465, 0x0ABE, 24, 74250000}, // 9: 1920x1080p_24Hz
282 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 25, 74250000}, // 10: 1920x1080p_25Hz
283 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 30, 74250000}, // 11: 1920x1080p_30Hz
284 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 50, 148500000}, // 12: 1920x1080p_50Hz
285 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 60, 148500000}, // 13: 1920x1080p_60Hz
286 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x089D, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x08CA, 0x0ABE, 24, 148500000}, // 14: 1920x2205p_24Hz //3D: 1920x1080p_24Hz x2
287 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x05DC, 0x07BC, 50, 148500000}, // 15: 1280x1470p_50Hz //3D: 1280x720_50Hz x2
288 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x05DC, 0x0672, 60, 148500000}, // 16: 1280x1470p_60Hz //3D: 1280x720_60Hz x2
289
290 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x04FC, 0x08CA, 0x157C, 24, 297000000}, // 17:93: 3840x2160p_24Hz
291 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0, 25, 297000000}, // 18:94: 3840x2160p_25Hz
292 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130, 30, 297000000}, // 19:95: 3840x2160p_30Hz
293 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0, 50, 594000000}, // 20:96: 3840x2160p_50Hz
294 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130, 60, 594000000}, // 21:97: 3840x2160p_60Hz
295
296 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x1000, 0x03FC, 0x08CA, 0x157C, 24, 297000000}, // 22:98: 4096x2160p_24Hz
297 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0, 25, 297000000}, // 23:99: 4096x2160p_25Hz
298 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130, 30, 297000000}, // 24:100: 4096x2160p_30Hz
299 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0, 50, 594000000}, // 25:101: 4096x2160p_50Hz
300 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130, 60, 594000000}, // 26:102: 4096x2160p_60Hz
301
302 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0003, 0x002E, 0x04B0, 0x0001, 0, 0x00C0, 0x0130, 0x0640, 0x0040, 0x04E2, 0x0870, 60, 162000000}, // 27: 1600x1200p_60Hz
303 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0006, 0x0019, 0x0384, 0x0003, 0, 0x0098, 0x00E8, 0x05A0, 0x0050, 0x03A6, 0x0770, 60, 106500000}, // 28: 1440x900p_60Hz
304 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0003, 0x0026, 0x0400, 0x0001, 0, 0x0070, 0x00F8, 0x0500, 0x0030, 0x042A, 0x0698, 60, 108000000}, // 29: 1280x1024p_60Hz
305 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0006, 0x001D, 0x0300, 0x0003, 0, 0x0088, 0x00A0, 0x0400, 0x0024, 0x0326, 0x0540, 60, 65000000}, // 30: 1024x768p_60Hz
306 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
307 };
308
309 //atop setting
310 stHDMITx_ATOP_SETTING HDMITxVideoAtopSetting[HDMITX_COLOR_DEPTH_TYPE_NUM][E_HDMITX_RES_MAX] =
311 {
312 //color depth = 8bit
313 {
314 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
315 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
316 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
317 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
318 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
319 // 74Mhz
320 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
321 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
322 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
323 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
324 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
325 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
326 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
327 // 148Mhz
328 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 12: 1920x1080p_50Hz
329 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 13: 1920x1080p_60Hz
330 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 14: 1920x2205p_24Hz
331 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 15: 1280x1470p_50Hz
332 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 16: 1280x1470p_60Hz
333 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
334 // 300Mhz
335 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
336 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
337 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
338 // 600Mhz
339 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
340 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
341 // 300Mhz
342 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
343 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
344 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
345 // 600Mhz
346 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
347 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
348
349 // 150MHz
350 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x2AAAAA}, // 27: 1600x1200p_60Hz
351 // 106.5MHz
352 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x40EB71}, // 28: 1440x900p_60Hz
353 // 108MHz
354 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 29: 1280x1024p_60Hz
355 // 65MHz
356 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x352B52}, // 30: 1024x768p_60Hz
357 },
358
359 //color depth = 10 bit
360 {
361 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 0: 640x480p
362 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 1: 720x480i
363 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 2: 720x576i
364 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 3: 720x480p
365 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 4: 720x576p
366 // 74Mhz
367 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 5: 1280x720p_50Hz
368 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 6: 1280x720p_60Hz
369 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 7: 1920x1080i_50Hz
370 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x25460A}, // 8: 1920x1080i_60Hz
371 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 9: 1920x1080p_24Hz
372 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 10: 1920x1080p_25Hz
373 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 11: 1920x1080p_30Hz
374 // 148Mhz
375 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 12: 1920x1080p_50Hz
376 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 13: 1920x1080p_60Hz
377 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 14: 1920x2205p_24Hz
378 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 15: 1280x1470p_50Hz
379 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 16: 1280x1470p_60Hz
380 // the following is 4k2k timing list, if not support, default is 3840x2160p@3
381
382 // 300Mhz
383 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 17:93: 3840x2160p_24Hz
384 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 18:94: 3840x2160p_25Hz
385 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 19:95: 3840x2160p_30Hz
386 // 600Mhz ==> not support !!!
387 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 20:96: 3840x2160p_50Hz
388 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 21:97: 3840x2160p_60Hz
389 // 300Mhz
390 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 22:98: 4096x2160p_24Hz
391 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 23:99: 4096x2160p_25Hz
392 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 24:100: 4096x2160p_30Hz
393 // 600Mhz ==> not support !!!
394 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 25:101: 4096x2160p_50Hz
395 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 26:102: 4096x2160p_60Hz
396
397 // 150MHz
398 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x222222}, // 27: 1600x1200p_60Hz
399 // 106.5MHz
400 //{0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x33EBCE}, // 28: 1440x900p_60Hz
401 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x33EF8D},
402 // 108MHz
403 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 29: 1280x1024p_60Hz
404 // 65MHz
405 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x2A890E}, // 30: 1024x768p_60Hz
406 },
407
408 //color depth = 12 bit
409 {
410 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 0: 640x480p
411 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 1: 720x480i
412 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 2: 720x576i
413 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 3: 720x480p
414 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 4: 720x576p
415 // 74Mhz
416 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 5: 1280x720p_50Hz
417 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 6: 1280x720p_60Hz
418 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 7: 1920x1080i_50Hz
419 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F0FB3}, // 8: 1920x1080i_60Hz
420 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 9: 1920x1080p_24Hz
421 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 10: 1920x1080p_25Hz
422 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 11: 1920x1080p_30Hz
423 // 148Mhz
424 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 12: 1920x1080p_50Hz
425 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 13: 1920x1080p_60Hz
426 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 14: 1920x2205p_24Hz
427 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 15: 1280x1470p_50Hz
428 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 16: 1280x1470p_60Hz
429 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
430
431 // 300Mhz
432 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 17:93: 3840x2160p_24Hz
433 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 18:94: 3840x2160p_25Hz
434 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 19:95: 3840x2160p_30Hz
435 // 600Mhz ==> not support !!!
436 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 20:96: 3840x2160p_50Hz
437 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 21:97: 3840x2160p_60Hz
438 // 300Mhz
439 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 22:98: 4096x2160p_24Hz
440 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 23:99: 4096x2160p_25Hz
441 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 24:100: 4096x2160p_30Hz
442 // 600Mhz ==> not support !!!
443 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 25:101: 4096x2160p_50Hz
444 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 26:102: 4096x2160p_60Hz
445
446 // 150MHz
447 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x04, 0x1C71C7}, // 27: 1600x1200p_60Hz
448 // 106.5MHz
449 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x2B47A0}, // 28: 1440x900p_60Hz
450 // 108MHz
451 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x2AAAAA}, // 29: 1280x1024p_60Hz
452 // 65MHz
453 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x237237}, // 30: 1024x768p_60Hz
454 },
455
456 //color depth = 16 bit
457 {
458 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
459 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
460 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
461 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
462 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
463 // 74Mhz
464 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
465 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
466 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
467 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
468 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
469 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
470 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
471 // 148Mhz
472 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 12: 1920x1080p_50Hz
473 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 13: 1920x1080p_60Hz
474 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 14: 1920x2205p_24Hz
475 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 15: 1280x1470p_50Hz
476 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 16: 1280x1470p_60Hz
477 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
478
479 // 300Mhz
480 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
481 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
482 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
483 // 600Mhz ==> Not support !!!
484 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
485 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
486 // 300Mhz
487 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
488 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
489 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
490 // 600Mhz ==> Not support !!!
491 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
492 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
493
494 // 150MHz
495 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x04, 0x2AAAAA}, // 27: 1600x1200p_60Hz
496 // 106.5MHz
497 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x40EB71}, // 28: 1440x900p_60Hz
498 // 108MHz
499 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x400000}, // 29: 1280x1024p_60Hz
500 // 65MHz
501 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x352B52}, // 30: 1024x768p_60Hz
502 },
503 };
504
505 //*********************//
506 // Audio //
507 //*********************//
508
509 MSTHDMITX_REG_TYPE HDMITxAudioOnTbl[] =
510 {
511 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enable audio FIFO, [2]:enable CTS Gen, [1]: automatically block start, [0]: audio FIFO not flush
512 };
513
514 MSTHDMITX_REG_TYPE HDMITxAudioOffTbl[] =
515 {
516 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
517 };
518
519 MSTHDMITX_REG_TYPE HDMITxAudioInitTbl[] =
520 {
521 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
522 };
523
524 MDrv_HDMITx_AUDIO_FREQ_TYPE TxAudioFreqTbl[E_HDMITX_AUDIO_FREQ_MAX_NUM] =
525 {
526 {0x02, 0x001800}, // No signal, set to 48 KHz
527 {0x03, 0x001000}, // 0 ~(32)~ 38 KHz, 4096
528 {0x00, 0x001880}, // 38 ~(44.1)~ 46 KHz, 6272
529 {0x02, 0x001800}, // 46 ~(48)~ 60 KHz, 6144
530 {0x08, 0x003100}, // 60 ~(88.2)~ 92 KHz, 12544
531 {0x0a, 0x003000}, // 92 ~(96)~ 140 KHz, 12288
532 {0x0c, 0x006200}, // 140 ~(176.4)~ 180 KHz, 25088
533 {0x0e, 0x006000}, // 180 ~(192)~ ~~ KHz, 24576
534 };
535
536 //*********************//
537 // Packet //
538 //*********************//
539
540 MS_U8 HDMITX_AviCmrTbl[E_HDMITX_RES_MAX] =
541 {
542 0x48, 0x48, 0x48, 0x48, 0x48, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, // SDTV C=01(601),M=00(no data) ,R=1000(same)
543 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0x48,
544 0xA8, 0x48, 0x48,
545 };
546
547 MS_U8 HDMITX_AviVicTbl[E_HDMITX_RES_MAX] =
548 {
549 1, 6, 21, 2, 17, 19, 4, 20, 5, 32, 33, 34, 31, 16, // SDTV 480i60,576i50,480p60,576p50,720p50,720p60,1080i50,1080i60,1080p24,1080p25,1080p30, 1080p50, 1080p60
550 32, 19, 4, 0, 0, 0, 96, 97, 0, 99, 100, 101, 102, 0,
551 0, 0, 0,
552 };
553
554 MS_U8 HDMITX_VendorName[8] =
555 {
556 "MStar "
557 };
558
559 MS_U8 HDMITX_ProductName[16] =
560 {
561 "HDMI Tx Demo",
562 };
563
564 MS_U8 _gHPDGpioPin = 0;
565
566 //-------------------------------------------------------------------------------------------------
567 // Debug Functions
568 //-------------------------------------------------------------------------------------------------
569
570 #ifdef MS_DEBUG
571 #define DBG_HDMITX(_f) (_f)
572 #else
573 #define DBG_HDMITX(_f)
574 #endif
575
576 //-------------------------------------------------------------------------------------------------
577 // Local Functions
578 //-------------------------------------------------------------------------------------------------
579
580
581 //-------------------------------------------------------------------------------------------------
582 // Global Functions
583 //-------------------------------------------------------------------------------------------------
584 /*********************************************************************/
585 /* */
586 /* HDCP22 Relative */
587 /* */
588 /*********************************************************************/
MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)589 void MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)
590 {
591 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x11, bEnable ? 0x11 : 0x00); // bit 0: enable hdcp22; bit 4: enable EESS
592 if (bEnable)
593 {
594 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x02); //reset hdcp22 FSM
595 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x00);
596 }
597 }
598
MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)599 void MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)
600 {
601 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x04, bEnable ? 0x04 : 0x00); //bit 2: authentication pass
602 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x08, bEnable ? 0x08 : 0x00); //bit 3: enable hdcp22 to issue encryption enable signal
603 }
604
MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 * pu8Riv,MS_U8 * pu8KsXORLC128)605 void MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 *pu8Riv, MS_U8 *pu8KsXORLC128)
606 {
607 #define DEF_HDCP2CIPHER_DBG 0
608 #define SIZE_OF_KSXORLC128 16
609 #define SIZE_OF_RIV 8
610
611 MS_U8 cnt = 0;
612
613 #if (DEF_HDCP2CIPHER_DBG == 1)
614 printf("Ks^LC128:\r\n");
615 for ( cnt = 0; cnt < SIZE_OF_KSXORLC128; cnt++ )
616 {
617 printf("0x%02X ", *(pu8KsXORLC128 + cnt));
618 }
619 printf("\r\n");
620
621 printf("Riv:\r\n");
622 for ( cnt = 0; cnt < SIZE_OF_RIV; cnt++ )
623 {
624 printf("0x%02X ", *(pu8Riv + cnt));
625 }
626 printf("\r\n");
627 #endif
628
629 #undef DEF_HDCP2CIPHER_DBG
630 //MHal_HDMITx_Mask_Write(0x172F00, 0x01, 0x0020, 0x0020); //reverse order of cihper key
631 //MHal_HDMITx_Mask_Write(0x172B00, 0x01, 0x8000, 0x0000); //disable hdcp 1.4 module
632
633 for ( cnt = 0; cnt < (SIZE_OF_KSXORLC128>>1); cnt++)
634 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x60 + (SIZE_OF_KSXORLC128 >> 1) - 1 - cnt, *(pu8KsXORLC128 + cnt*2 + 1)|(*(pu8KsXORLC128 + cnt*2)<<8));
635
636 for ( cnt = 0; cnt < (SIZE_OF_RIV>>1); cnt++)
637 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x68 + (SIZE_OF_RIV >> 1) - 1 - cnt, *(pu8Riv + cnt*2 + 1)|(*(pu8Riv + cnt*2)<<8));
638 }
639
Mhal_HDMITx_SetSCDCCapability(MS_BOOL bFlag)640 void Mhal_HDMITx_SetSCDCCapability(MS_BOOL bFlag)
641 {
642 g_bSupportSCDC = bFlag;
643 }
644
MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)645 void MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)
646 {
647 gu8ChipVerNum = u8ChipVer;
648 }
649
650 // HPD: GPIO_PM[11] -> external interrupt[11], register 0x000E00[14]
651 // DVI disconnet: must power down clock termination resistor: TM_REG[0] = 1, TM_REG[16:15] = 00, TM_REG[35:34] = 00.
652 // Interrupt helper functoins
653 //------------------------------------------------------------------------------
654 /// @brief Disable interrupt
655 /// @param[in] u32Int interrupter value
656 /// @return None
657 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Disable(MS_U32 u32Int)658 void MHal_HDMITx_Int_Disable(MS_U32 u32Int)
659 {
660 //MS_U16 u16reg_val = 0;
661
662 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int);
663 // [9]: mask FIQ, [8]: mask IRQ
664 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) );
665
666 #if 0 // K1 HPD pin doesn't have interrupt function
667 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
668 {
669 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
670 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank
671 {
672 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask
673 }
674 }
675 #endif
676 }
677
678 //------------------------------------------------------------------------------
679 /// @brief Enable interrupt
680 /// @param[in] u32Int interrupter value
681 /// @return None
682 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Enable(MS_U32 u32Int)683 void MHal_HDMITx_Int_Enable(MS_U32 u32Int)
684 {
685 //MS_U16 u16reg_val = 0;
686
687 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int);
688 // [9]: mask FIQ, [8]: unmask IRQ
689 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 );
690
691 #if 0 // K1 HPD pin doesn't have interrupt function
692 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
693 {
694 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
695 if(u32Int & E_HDMITX_IRQ_12)
696 {
697 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_PM output disable
698 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask
699 }
700 }
701 #endif
702 }
703
704 //------------------------------------------------------------------------------
705 /// @brief MHal_HDMITx_Int_Clear
706 /// @param[in] u32Int interrupter value
707 /// @return None
708 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Clear(MS_U32 u32Int)709 void MHal_HDMITx_Int_Clear(MS_U32 u32Int)
710 {
711 //MS_U16 u16reg_val = 0;
712
713 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int);
714 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16));
715
716 #if 0 // K1 HPD pin doesn't have interrupt function
717 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
718 {
719 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
720 if(u32Int & E_HDMITX_IRQ_12)
721 {
722 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val);
723 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0);
724 }
725 }
726 #endif
727 }
728
729 //------------------------------------------------------------------------------
730 /// @brief MHal_HDMITx_Int_Status
731 /// @param[in] u32Int interrupter value
732 /// @return None
733 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Status(void)734 MS_U32 MHal_HDMITx_Int_Status(void)
735 {
736 //MS_U16 u16reg_val = 0;
737 MS_U32 reg_value=0;
738
739 reg_value |= MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E);
740 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16);
741
742 #if 0 // K1 HPD pin doesn't have interrupt function
743 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4
744 {
745 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
746 reg_value = ((MHal_HDMITxPM_Read(PMBK_PMSLEEP_REG_BASE, 0x0A) & u16reg_val) ? (reg_value|E_HDMITX_IRQ_12):(reg_value&(~E_HDMITX_IRQ_12)));
747 }
748 #endif
749 return reg_value;
750 }
751
752
753 //------------------------------------------------------------------------------
754 /// @brief This routine is to get HDMI receiver DVI clock and HPD status.
755 /// @return MsHDMITX_RX_STATUS
756 //------------------------------------------------------------------------------
MHal_HDMITx_GetRXStatus(void)757 MsHDMITX_RX_STATUS MHal_HDMITx_GetRXStatus(void)
758 {
759 MS_BOOL dviclock_s, hpd_s = FALSE;
760 MsHDMITX_RX_STATUS state;
761
762 dviclock_s = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F) & BIT0 ? FALSE : TRUE;
763
764 hpd_s = mdrv_gpio_get_level(_gHPDGpioPin);
765
766 if((dviclock_s == FALSE) && (hpd_s == FALSE))
767 state = E_HDMITX_DVIClock_L_HPD_L;
768 else if((dviclock_s == FALSE) && (hpd_s == TRUE))
769 state = E_HDMITX_DVIClock_L_HPD_H;
770 else if((dviclock_s == TRUE) && (hpd_s == FALSE))
771 state = E_HDMITX_DVIClock_H_HPD_L;
772 else
773 state = E_HDMITX_DVIClock_H_HPD_H;
774
775 return state;
776 }
777
778
779 //------------------------------------------------------------------------------
780 /// @brief MHal_HDMITX_SetHDCPConfig
781 /// @param[in] u32Int HDCP mode
782 /// @return None
783 //------------------------------------------------------------------------------
MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)784 void MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)
785 {
786 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8);
787 }
788
789
790 //------------------------------------------------------------------------------
791 /// @brief MHal_HDMITX_GetM02Bytes
792 /// @param[in] u16Int index
793 /// @return M0 2 bytes
794 //------------------------------------------------------------------------------
MHal_HDMITX_GetM02Bytes(MS_U16 idx)795 MS_U16 MHal_HDMITX_GetM02Bytes(MS_U16 idx)
796 {
797 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx));
798 }
799
800
801 //------------------------------------------------------------------------------
802 /// @brief MHal_HDMITx_InitSeq
803 /// @param[in] None
804 /// @return None
805 //------------------------------------------------------------------------------
MHal_HDMITx_InitSeq(void)806 void MHal_HDMITx_InitSeq(void)
807 {
808 MHal_HDMITx_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, 0); // enable clk_hdmi_tx_p
809
810 //set at mboot
811 //MHal_HDMITx_Mask_Write(0x101E00, 0x0B, BIT12, BIT12); //enable hdmitx DDC
812
813 //MAC setting
814 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1C, 0x0000);
815 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1D, 0x0000);
816 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1E, 0xFFFF);
817 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1F, 0x0000);
818
819 //sw reset modules
820 if(MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E) & 0xE800)
821 {
822 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
823 }
824 else
825 {
826 //disable power down
827 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
828 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
829 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
830 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0017);
831 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0000);
832 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x001F);
833 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x0000);
834 }
835
836 //MHal_HDMITx_Write(HDMITX_REG_BASE, REG_HPLL_LOCK_CNT_53, 0x0300); // HPLL lock counter
837
838 //enable PHY setting
839 //[0]:enable synth clock; [4]:enable synth clock to a top; [8]:enable tmds clock; [12]: enable atop 40 bit clock
840 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101, 0x1101);
841 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
842 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00);
843
844 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F, 0x0010, 0x0010); //reg_atop_nodie_en_disc
845
846 //disable power down
847 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
848 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, 0x0000);
849
850 //rterm set by Mboot according to data of EFUSE, rterm 50 Ohm
851 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x01F0, 0x0000);
852
853 //txpll input div 1
854 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x03F3, 0x0051);
855
856 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3D, 0x030F, 0x0003); //REG_TXPLL_SEL_CLKIN, REG_TXPLL_ICP_ICTRL
857 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0003); //REG_ICTRL_PREDRV_MAIN_CLK
858 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0000); //REG_ICTRL_PREDRV_MAIN_CLK
859 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x003F, 0x0010); //REG_ICTRL_DRV_MAIN_CLK
860
861 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_32, 0x3F3F, 0x0000);
862 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_36, 0x3F3F, 0x0000);
863 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_37, 0x3F3F, 0x0000);
864
865 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
866
867 //lane fifo setting
868 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x0007, 0x0004);
869 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x0007, 0x0005);
870 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x0007, 0x0006);
871 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x0007, 0x0007);
872
873 //timing field regen enable (due to scaler can't guarantee field signal and even/odd frame is asynchronize)
874 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x0010, 0x0010);
875
876 //for U02: QD980 CTS compatibility issue
877 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x8000, 0x8000);
878
879 }
880
881 //------------------------------------------------------------------------------
882 /// @brief This routine is the initialization for Video module.
883 /// @return None
884 //------------------------------------------------------------------------------
MHal_HDMITx_VideoInit(void)885 void MHal_HDMITx_VideoInit(void)
886 {
887 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, BIT4, BIT4); //enable video engine fifo r/w pointer
888 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_12, 0x000F, BIT3); // [3]: manual mode of pixel-repetition enable
889 }
890
891 //------------------------------------------------------------------------------
892 /// @brief This routine is the initialization for Audio module.
893 /// @return None
894 //------------------------------------------------------------------------------
MHal_HDMITx_AudioInit(void)895 void MHal_HDMITx_AudioInit(void)
896 {
897 int num;
898
899 num = sizeof(HDMITxAudioInitTbl) / sizeof(MSTHDMITX_REG_TYPE);
900 MHal_HDMITx_RegsTbl_Write(HDMITxAudioInitTbl, num);
901 }
902
903
904 //------------------------------------------------------------------------------
905 /// @brief This routine turn on/off HDMI PLL
906 /// @return None
907 //------------------------------------------------------------------------------
MHal_HDMITx_PLLOnOff(MS_BOOL bflag)908 void MHal_HDMITx_PLLOnOff(MS_BOOL bflag)
909 {
910 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, bflag ? 0x0000 : 0x0010);
911 }
912
913
MHal_HDMITx_PKT_User_Define_Clear(void)914 void MHal_HDMITx_PKT_User_Define_Clear(void)
915 {
916 MS_U8 i = 0;
917
918 for ( i = 0; i < GENERAL_PKT_NUM; i++ )
919 {
920 gbGeneralPktList[i].EnableUserDef = FALSE;
921 gbGeneralPktList[i].FrmCntNum = 0x00;
922 gbGeneralPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
923 memset(&gbGeneralPktList[i].PktPara, 0x00, sizeof(gbGeneralPktList[i].PktPara));
924 }
925
926 for ( i = 0; i < INFOFRM_PKT_NUM; i++ )
927 {
928 gbInfoFrmPktList[i].EnableUserDef = FALSE;
929 gbInfoFrmPktList[i].FrmCntNum = 0x00;
930 gbInfoFrmPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
931 memset(&gbInfoFrmPktList[i].PktPara, 0x00, sizeof(gbInfoFrmPktList[i].PktPara));
932 }
933 }
934
MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type,MS_BOOL def_flag,MsHDMITX_PACKET_PROCESS def_process,MS_U8 def_fcnt)935 void MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type, MS_BOOL def_flag,
936 MsHDMITX_PACKET_PROCESS def_process, MS_U8 def_fcnt)
937 {
938 if (packet_type & 0x80) //infoframe packet type
939 {
940 gbInfoFrmPktList[packet_type & (~0x80)].EnableUserDef = def_flag;
941 gbInfoFrmPktList[packet_type & (~0x80)].FrmCntNum = def_fcnt;
942 gbInfoFrmPktList[packet_type & (~0x80)].enPktCtrl = def_process;
943 }
944 else
945 {
946 gbGeneralPktList[packet_type].EnableUserDef = def_flag;
947 gbGeneralPktList[packet_type].FrmCntNum = def_fcnt;
948 gbGeneralPktList[packet_type].enPktCtrl = def_process;
949 }
950 }
951
MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type,MS_U8 * data,MS_U8 length)952 MS_BOOL MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type, MS_U8* data, MS_U8 length)
953 {
954 MS_BOOL bRet = TRUE;
955 MS_U8 i, j, *ptr;
956 ptr = data;
957
958 switch(packet_type)
959 {
960 case E_HDMITX_VS_INFOFRAME:
961 for (i=0; i < length; i++)
962 {
963 j = i>>1;
964
965 if ((REG_PKT_VS_1_27+j > REG_PKT_VS_14_34) || ((REG_PKT_VS_1_27+j == REG_PKT_VS_14_34) && (i % 2 == 1)))
966 {
967 //Packet over size, last VS packet PB register is REG_PKT_VS_14_34[7:0]
968 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
969 break;
970 }
971
972 if((i%2)==0)
973 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0x00FF, *(ptr+i));
974 else
975 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0xFF00, (*(ptr+i))<<8);
976 }
977 break;
978 case E_HDMITX_SPD_INFOFRAME:
979 for(i=0;i<length;i++)
980 {
981 j = i>>1;
982
983 if((REG_PKT_SPD_1_15+j > REG_PKT_SPD_13_21) || ((REG_PKT_SPD_1_15+j == REG_PKT_SPD_13_21) && (i % 2 == 1)))
984 {
985 //Packet over size, last SPD packet PB register is REG_PKT_SPD_13_21[7:0]
986 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
987 break;
988 }
989
990 if((i%2)==0)
991 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0x00FF, *(ptr+i));
992 else
993 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0xFF00, (*(ptr+i))<<8);
994 }
995 break;
996
997 case E_HDMITX_AVI_INFOFRAME:
998 for ( i = 0; i < length; i++ )
999 {
1000 j = i >> 1;
1001
1002 if (((REG_PKT_AVI_1_09 + j) > REG_PKT_AVI_7_0F) || (((REG_PKT_AVI_1_09 + j) == REG_PKT_AVI_7_0F) && (i % 2 == 1)))
1003 {
1004 DBG_HDMITX(printf("AVI packet over size, length = %d \n", length));
1005 break;
1006 }
1007
1008 if ((i % 2) == 0)
1009 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + j, 0x00FF, *(ptr+i));
1010 else
1011 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + j, 0xFF00, *(ptr+i) << 8);
1012 }
1013 break;
1014
1015 //wilson@kano HDR packet
1016 case E_HDMITX_HDR_INFOFRAME:
1017 //first 3 bytes will follow spec, (1) type code (2) version (3) length, and reamins will be content
1018 length = (length > (HDMITX_HDR_INFO_PKT_LEN + 3)) ? (HDMITX_HDR_INFO_PKT_LEN + 3) : length;
1019 //fill length and version
1020 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F,(*(ptr+2) << 8) | *(ptr+1));
1021
1022 if (length >= 3)
1023 {
1024 for ( i = 0; i < (length-3); i++ )
1025 {
1026 j = i >> 1;
1027
1028 if ( ((REG_HDMI_2_CONFIG_10 + j) > REG_HDMI_2_CONFIG_1D) || (((REG_HDMI_2_CONFIG_10 + j) == REG_HDMI_2_CONFIG_1D) && (i % 2 == 1)) )
1029 {
1030 DBG_HDMITX(printf("HDR packet over size, length = %d \n", length));
1031 break;
1032 }
1033
1034 if ((i % 2) == 0)
1035 {
1036 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0x00FF, *(ptr+i+3));
1037 }
1038 else
1039 {
1040 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0xFF00, (*(ptr+i+3))<<8);
1041 }
1042 }
1043 }
1044 break;
1045
1046 case E_HDMITX_AUDIO_INFOFRAME:
1047 {
1048 //total length should be 192 bits *2 = 384 bits = 48 bytes;
1049
1050 length = (length < ((192>>3)<<1) ) ? length : ((192>>3)<<1);
1051
1052 for ( i = 0; i < length; i++ )
1053 {
1054 j = i >> 1;
1055
1056 if ((i % 2) == 0)
1057 {
1058 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0x00FF, *(ptr+i));
1059 }
1060 else
1061 {
1062 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0xFF00, (*(ptr+i) << 8));
1063 }
1064 }
1065 }
1066 break;
1067
1068 default:
1069 i = 0;
1070 j = 0;
1071 bRet = FALSE;
1072 DBG_HDMITX(printf("Not implemented, packet type = %u\n", packet_type));
1073 break;
1074 }
1075
1076 return bRet;
1077 }
1078
1079 //------------------------------------------------------------------------------
1080 /// @brief This routine turn on/off HDMI Tx TMDS signal
1081 /// @param[in] bRB_Swap: R/B swap; bTMDS: TMDS flag
1082 /// @return None
1083 //------------------------------------------------------------------------------
MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap,MS_BOOL bTMDS)1084 void MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap, MS_BOOL bTMDS)
1085 {
1086 if(bRB_Swap) // R/B channel swap
1087 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, BIT13);
1088 else
1089 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, 0);
1090
1091 //reg_atop_en_data_out[13..15]: Enable data channel data output
1092 if (bTMDS == TRUE)
1093 {
1094 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
1095 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0xE800);
1096 //TBD: turn off tmds clock
1097
1098 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo
1099 MsOS_DelayTask(10);
1100 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000);
1101 }
1102 else
1103 {
1104 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
1105 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0x0000);
1106 //TBD: turn off tmds clock
1107 }
1108 }
1109
1110 //------------------------------------------------------------------------------
1111 /// @brief This routine return on/off status of HDMI Tx TMDS signal
1112 /// @return On/Off
1113 //------------------------------------------------------------------------------
MHal_HDMITx_GetTMDSStatus(void)1114 MS_U32 MHal_HDMITx_GetTMDSStatus(void)
1115 {
1116 MS_U16 usTMDSOutput = 0;
1117 MS_U16 usTMDSPD = 0;
1118 MS_U32 uiTMDSOn = 0;
1119
1120 usTMDSOutput = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E);
1121 usTMDSPD = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39);
1122
1123 if( ((usTMDSOutput&0xE800) == 0xE800) && ((usTMDSPD &0x0FFF) == 0x0000) )
1124 {
1125 uiTMDSOn = TRUE;
1126 }
1127 else
1128 {
1129 uiTMDSOn = FALSE;
1130 }
1131
1132 return uiTMDSOn;
1133 }
1134
1135 /// @brief This routine turn on/off HDMI Tx video output
1136 /// @param[in] bVideo: Video flag; bCSC: CSC flag, b709format = BT.709-5
1137 /// @return None
1138 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo,MS_BOOL bCSC,MS_BOOL b709format)1139 void MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo, MS_BOOL bCSC, MS_BOOL b709format)
1140 {
1141 if (bVideo == TRUE)
1142 {
1143 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0, 0x0000); // disable test pattern
1144 }
1145 else
1146 {
1147 MS_U8 i = 0x00;
1148
1149 DBG_HDMITX(printf("MDrv_HDMITx_SetVideoOnOff: csc flag= %d \n", bCSC));
1150
1151 // enable test pattern
1152 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3A, 0x0000);
1153 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3B, 0x0000);
1154 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3C, 0x03FF); // whole-blue
1155 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0|BIT1, BIT0|BIT1);
1156
1157 for ( i = 0; i < 6; i++ )
1158 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3D + i, 0x0000);
1159 }
1160 }
1161
1162 //------------------------------------------------------------------------------
1163 /// @brief This routine sets video color formatt
1164 /// @param[in] bCSC: CSC flag, YUV422 12 bit, b709format = BT.709-5
1165 /// @return None
1166 //------------------------------------------------------------------------------
MHal_HDMITx_SetColorFormat(MS_BOOL bCSC,MS_BOOL bHdmi422b12,MS_BOOL b709format)1167 void MHal_HDMITx_SetColorFormat(MS_BOOL bCSC, MS_BOOL bHdmi422b12, MS_BOOL b709format)
1168 {
1169 if (bCSC) // YUV -> RGB
1170 {
1171 DBG_HDMITX(printf("YUV -> RGB \n"));
1172 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, BIT0); //bypass
1173 }
1174 else // bypass
1175 {
1176 DBG_HDMITX(printf("bypass YUV -> RGB \n"));
1177 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, 0x00); //bypass
1178 }
1179
1180 // YUV422 12 bits output
1181 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, bHdmi422b12 ? BIT15 : 0x00);
1182 }
1183
1184 //------------------------------------------------------------------------------
1185 /// @brief This routine get CSC capability
1186 /// @param[in]
1187 /// @return False : not support R2Y. Ture : ok.
1188 //------------------------------------------------------------------------------
MHal_HDMITx_CSC_Support_R2Y(void * pDatatIn)1189 MS_BOOL MHal_HDMITx_CSC_Support_R2Y(void* pDatatIn)
1190 {
1191 pDatatIn = pDatatIn;
1192 return HDMITX_CSC_SUPPORT_R2Y;
1193 }
1194
1195 //------------------------------------------------------------------------------
1196 /// @brief This routine sets color domain and color range transform
1197 /// @param[in]
1198 /// @return False : not support this command. Ture : ok.
1199 //------------------------------------------------------------------------------
MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor,MsHDMITX_VIDEO_COLOR_FORMAT outcolor,MsHDMITX_YCC_QUANT_RANGE inrange,MsHDMITX_YCC_QUANT_RANGE outrange)1200 MS_BOOL MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor, MsHDMITX_VIDEO_COLOR_FORMAT outcolor, MsHDMITX_YCC_QUANT_RANGE inrange, MsHDMITX_YCC_QUANT_RANGE outrange)
1201 {
1202 MS_BOOL bReturn = FALSE;
1203
1204 if( (incolor == outcolor) && (inrange == outrange) )
1205 {
1206 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1207 bReturn = TRUE;
1208 DBG_HDMITX(printf("Input equals output \n"));
1209 }
1210 else if(incolor == E_HDMITX_VIDEO_COLOR_RGB444)
1211 {
1212 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LR
1213 {
1214 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1215 { //LR -> LY
1216 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1217 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x020C);
1218 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E24);
1219 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD0);
1220 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1221 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1222 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1223 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F88);
1224 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E6C);
1225 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x020C);
1226 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1227 bReturn = TRUE;
1228 DBG_HDMITX(printf("LR->LY! \n"));
1229 }
1230 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1231 { //LR -> FY
1232 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0CB0);
1233 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0256);
1234 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1DE1);
1235 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FC9);
1236 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00FE);
1237 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0357);
1238 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0056);
1239 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F77);
1240 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E33);
1241 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0256);
1242 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1243 bReturn = TRUE;
1244 DBG_HDMITX(printf("LR->FY! \n"));
1245 }
1246 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_FULL))
1247 { //LR -> FR
1248 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0C10);
1249 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1250 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1251 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1252 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1253 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1254 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1255 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1256 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1257 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1258 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1259 bReturn = TRUE;
1260 DBG_HDMITX(printf("LR->FR! \n"));
1261 }
1262 else
1263 {
1264 DBG_HDMITX(printf("LR->LR! \n"));
1265 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1266 DBG_HDMITX(printf("In/Out Same Color! \n"));
1267 bReturn = TRUE;
1268 }
1269
1270 }
1271 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FR
1272 {
1273 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1274 { //FR -> LY
1275 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00E0);
1276 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x01C0);
1277 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E69);
1278 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD7);
1279 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00BA);
1280 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0273);
1281 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x003F);
1282 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F99);
1283 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1EA6);
1284 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x01C0);
1285 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1286 bReturn = TRUE;
1287 DBG_HDMITX(printf("FR->LY! \n"));
1288 }
1289 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1290 { //FR -> FY
1291 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1292 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0200);
1293 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E2F);
1294 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD1);
1295 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1296 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1297 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1298 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F8B);
1299 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E75);
1300 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0200);
1301 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1302 bReturn = TRUE;
1303 DBG_HDMITX(printf("FR->FY! \n"));
1304 }
1305 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1306 { //FR -> LR
1307 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x5040);
1308 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0381);
1309 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1310 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1311 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1312 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1313 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1314 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1315 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1316 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0381);
1317 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1318 bReturn = TRUE;
1319 DBG_HDMITX(printf("FR->LR! \n"));
1320 }
1321 else
1322 {
1323 DBG_HDMITX(printf("FR->FR! \n"));
1324 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1325 DBG_HDMITX(printf("In/Out Same Color! \n"));
1326 bReturn = TRUE;
1327 }
1328 }
1329 else
1330 {
1331 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1332 DBG_HDMITX(printf("Not Support This! \n"));
1333 }
1334 }
1335 else if((incolor == E_HDMITX_VIDEO_COLOR_YUV444) || (incolor == E_HDMITX_VIDEO_COLOR_YUV422))
1336 {
1337 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LY
1338 {
1339 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1340 {//LY->FR
1341 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x001A);
1342 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0731);
1343 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x04AC);
1344 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1345 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1DDD);
1346 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1347 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F25);
1348 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1349 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x04AC);
1350 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0879);
1351 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1352 bReturn = TRUE;
1353 DBG_HDMITX(printf("LY->FR! \n"));
1354 }
1355 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1356 {//LY->LR
1357 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1358 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0629);
1359 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1360 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1361 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E2B);
1362 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1363 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F44);
1364 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1365 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1366 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0742);
1367 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1368 bReturn = TRUE;
1369 DBG_HDMITX(printf("May over range! \n"));
1370 DBG_HDMITX(printf("LY->LR! \n"));
1371 }
1372 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1373 {//LY->FY
1374 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00BA);
1375 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0491);
1376 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1377 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1378 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1379 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1380 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1381 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1382 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1383 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0491);
1384 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1385 bReturn = TRUE;
1386 DBG_HDMITX(printf("LY->FY! \n"));
1387 }
1388 else
1389 {
1390 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1391 DBG_HDMITX(printf("In/Out Same Color! \n"));
1392 DBG_HDMITX(printf("LY->LY! \n"));
1393 bReturn = TRUE;
1394 }
1395
1396 }
1397 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FY
1398 {
1399 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1400 {//FY->FR
1401 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1402 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x064D);
1403 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1404 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1405 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E21);
1406 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1407 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F40);
1408 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1409 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1410 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x076C);
1411 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1412 bReturn = TRUE;
1413 DBG_HDMITX(printf("FY->FR! \n"));
1414 }
1415 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1416 {//FY->LR
1417 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x504A);
1418 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0565);
1419 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x036D);
1420 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1421 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E66);
1422 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1423 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F5C);
1424 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1425 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x036D);
1426 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x065B);
1427 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1428 bReturn = TRUE;
1429 DBG_HDMITX(printf("FY->LR! \n"));
1430 }
1431 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1432 {//FY->LY
1433 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00EA);
1434 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1435 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1436 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1437 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1438 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1439 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1440 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1441 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1442 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1443 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1444 bReturn = TRUE;
1445 DBG_HDMITX(printf("FY->LY! \n"));
1446 }
1447 else
1448 {
1449 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1450 DBG_HDMITX(printf("In/Out Same Color! \n"));
1451 DBG_HDMITX(printf("FY->FY! \n"));
1452 bReturn = TRUE;
1453 }
1454 }
1455 else
1456 {
1457 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1458 DBG_HDMITX(printf("Not Support This! \n"));
1459 }
1460 }
1461 else
1462 {
1463 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1464 DBG_HDMITX(printf("Not Support This! \n"));
1465 }
1466
1467 //if((bReturn == TRUE) && (outcolor == E_HDMITX_VIDEO_COLOR_YUV422))
1468 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, (outcolor == E_HDMITX_VIDEO_COLOR_YUV422) ? BIT15 : 0);
1469
1470 return bReturn;
1471 }
1472
1473 //------------------------------------------------------------------------------
1474 /// @brief This routine will set or stop all HDMI packet generation
1475 /// @param[in] bflag True: Enable packet gen, False : Disable packet gen
1476 /// @return None
1477 //------------------------------------------------------------------------------
MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)1478 void MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)
1479 {
1480 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT2, bflag ? BIT2:0);
1481 }
1482
1483 //------------------------------------------------------------------------------
1484 /// @brief This routine sets HDMI/DVI mode
1485 /// @param[in] bflag
1486 /// @return None
1487 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDMImode(MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)1488 void MHal_HDMITx_SetHDMImode(MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)
1489 {
1490 MS_U8 ucRegVal = 0x00;
1491
1492 DBG_HDMITX(printf("[%s][%d]HDMI mode = %d, Color Depth = %d \n", __FUNCTION__, __LINE__, bflag, bflag));
1493
1494 if (bflag) // HDMI mode
1495 {
1496 switch(cd_val)
1497 {
1498 case E_HDMITX_VIDEO_CD_NoID:
1499 case E_HDMITX_VIDEO_CD_24Bits:
1500 default:
1501 ucRegVal = 0x00;
1502 break;
1503
1504 case E_HDMITX_VIDEO_CD_30Bits:
1505 ucRegVal = 0x40;
1506 break;
1507
1508 case E_HDMITX_VIDEO_CD_36Bits:
1509 ucRegVal = 0x80;
1510 break;
1511
1512 case E_HDMITX_VIDEO_CD_48Bits:
1513 ucRegVal = 0xC0;
1514 break;
1515 }
1516
1517 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, ucRegVal|BIT2); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1518 }
1519 else // DVI
1520 {
1521 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, BIT0); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1522 }
1523 }
1524
1525
1526 //------------------------------------------------------------------------------
1527 /// @brief This routine sets audio on/off
1528 /// @param[in] bflag
1529 /// @return None
1530 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)1531 void MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)
1532 {
1533 MS_U8 num;
1534
1535 if(bflag) // audio on
1536 {
1537 num = sizeof(HDMITxAudioOnTbl)/sizeof(MSTHDMITX_REG_TYPE);
1538 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOnTbl, num);
1539 }
1540 else // audio off
1541 {
1542 num = sizeof(HDMITxAudioOffTbl)/sizeof(MSTHDMITX_REG_TYPE);
1543 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOffTbl, num);
1544 }
1545 }
1546
1547 //------------------------------------------------------------------------------
1548 /// @brief This routine sets audio sampling freq.
1549 /// @return None
1550 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,MsHDMITX_AUDIO_CHANNEL_COUNT achidx,MsHDMITX_AUDIO_CODING_TYPE actidx)1551 void MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,
1552 MsHDMITX_AUDIO_CHANNEL_COUNT achidx, MsHDMITX_AUDIO_CODING_TYPE actidx
1553 )
1554 {
1555 // HDMI audio channel setting
1556 if(achidx == E_HDMITX_AUDIO_CH_2) // 2 channels
1557 {
1558 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5]: audio FIFO depth ch1234, [4]=1'b0: 2 channels
1559 }
1560 else // 8 channels
1561 {
1562 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels
1563 }
1564
1565 // Audio channel status
1566 #if 1 //NOTE:: kano: move channel status from address 0x00 to address 0x0A
1567 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1568 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[afidx].CH_Status3 << 8) | (achidx << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
1569 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
1570 #else
1571 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_00, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1572 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_01, 0);
1573 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_02, (achidx<<4)); // [7:4]: audio channel count
1574 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS3_03, TxAudioFreqTbl[afidx].CH_Status3); // [3:0]: audio sampling frequncy
1575 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS4_04, 0);
1576 #endif
1577 // ACR N code
1578 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_2_06, 0x0F00, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000));
1579 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_3_07, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1580
1581 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_61, 0x000F, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000) >> 8);
1582 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_60, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1583 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x0100, 0x0100); //enable cts * 2
1584 }
1585
1586 //------------------------------------------------------------------------------
1587 /// @brief This routine sets audio source format.
1588 /// @return None
1589 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)1590 void MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)
1591 {
1592 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8);
1593 }
1594
1595 //------------------------------------------------------------------------------
1596 /// @brief This routine Get Audio CTS value
1597 /// @return CTS
1598 //------------------------------------------------------------------------------
MHal_HDMITx_GetAudioCTS(void)1599 MS_U32 MHal_HDMITx_GetAudioCTS(void)
1600 {
1601 MS_U32 ret;
1602
1603 ret = ((MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_2_06) & 0x000F) << 16) | MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_1_05);
1604 return ret;
1605 }
1606
1607 //------------------------------------------------------------------------------
1608 /// @brief This routine Mute Audio FIFO
1609 /// @param[in] bflag: True: mute audio, False: unmute audio
1610 /// @return None
1611 //------------------------------------------------------------------------------
MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)1612 void MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)
1613 {
1614 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag);
1615 }
1616
1617 //------------------------------------------------------------------------------
1618 /// @brief This routine sets HDMI Tx HDCP encryption On/Off
1619 /// @return None
1620 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag,MS_BOOL hdmi_flag)1621 void MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag, MS_BOOL hdmi_flag)
1622 {
1623 if(hdcp_flag) // HDCP on
1624 {
1625 if (hdmi_flag) // HDMI EESS
1626 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400);
1627 else // DVI OESS
1628 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000);
1629 // HDCP encryption
1630 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008);
1631 }
1632 else // HDCP off
1633 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000);
1634 }
1635
1636 //------------------------------------------------------------------------------
1637 /// @brief This routine calculate check sum of infoframes.
1638 /// @param[in] packet_type packet type
1639 /// @return checksum
1640 //------------------------------------------------------------------------------
MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)1641 MS_U8 MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)
1642 {
1643 MS_U8 ucSumVal = 0;
1644 MS_U8 i = 0;
1645 MS_U8 j = 0;
1646 MS_U16 wRegVal = 0;
1647
1648 switch (packet_type)
1649 {
1650 case E_HDMITX_VS_INFOFRAME:
1651 ucSumVal += (E_HDMITX_VS_INFOFRAME + HDMITX_VS_INFO_PKT_VER + HDMITX_VS_INFO_PKT_LEN);
1652
1653 for ( i = 0; i < (HDMITX_VS_INFO_PKT_LEN + 1) >> 1; i++ )
1654 {
1655 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_VS_1_27 + i);
1656
1657 for ( j = 0; j < 2; j++ )
1658 {
1659 if ((i == 13) && (j==1))
1660 {
1661 ucSumVal += 0x00;
1662 }
1663 else
1664 {
1665 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1666 }
1667 }
1668 }
1669 break;
1670
1671 case E_HDMITX_AVI_INFOFRAME:
1672 ucSumVal += (E_HDMITX_AVI_INFOFRAME + HDMITX_AVI_INFO_PKT_VER + HDMITX_AVI_INFO_PKT_LEN);
1673
1674 for ( i = 0; i < ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1); i++ )
1675 {
1676 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + i);
1677
1678 for ( j = 0; j < 2; j++ )
1679 {
1680 if ((i == 1) && (j == 0)) // SC[1:0]
1681 {
1682 ucSumVal += (HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)(wRegVal & 0x00FF) & 0x03);
1683 }
1684 else if ((i == 1) && (j == 1)) // VIC[6:0]
1685 {
1686 ucSumVal += ((HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)((wRegVal & 0xFF00) >> 8) & 0x7F) : 0x00);
1687 }
1688 else if ((i == 2) && (j == 0)) // PR[3:0]
1689 {
1690 ucSumVal += (MS_U8)(wRegVal & 0x00FF); //bit 4:7 used for HDR; //ucSumVal += ((MS_U8)(wRegVal & 0x00FF) & 0x0F);
1691 }
1692 #if 0 //not resevered byte anymore; should be counted
1693 else if ((i == 2) && (j == 1)) // reserved
1694 {
1695 ucSumVal += 0x00;
1696 }
1697 #endif
1698 else if (( i == ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1) - 1)&&(j == 1))
1699 {
1700 ucSumVal += 0x00;
1701 }
1702 else
1703 {
1704 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1705 }
1706 }
1707 }
1708 break;
1709
1710 case E_HDMITX_SPD_INFOFRAME:
1711 ucSumVal += (E_HDMITX_SPD_INFOFRAME + HDMITX_SPD_INFO_PKT_VER + HDMITX_SPD_INFO_PKT_LEN);
1712
1713 for ( i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN+ 1) >> 1); i++ )
1714 {
1715 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_SPD_1_15 + i);
1716
1717 for ( j = 0; j < 2; j++ )
1718 {
1719 if ((i == 12) && (j == 0))
1720 {
1721 ucSumVal += (MS_U8)(wRegVal & 0x00FF);
1722 }
1723 else if ((i == 12) && (j == 1)) //reserved
1724 {
1725 ucSumVal += 0x00;
1726 }
1727 else
1728 {
1729 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1730 }
1731 }
1732 }
1733 break;
1734
1735 case E_HDMITX_AUDIO_INFOFRAME:
1736 ucSumVal += (E_HDMITX_AUDIO_INFOFRAME + HDMITX_AUD_INFO_PKT_VER + HDMITX_AUD_INFO_PKT_LEN);
1737
1738 for ( i = 0; i < (((HDMITX_AUD_INFO_PKT_LEN >> 1) + 1) >> 1); i++ )
1739 {
1740 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AUD_1_11 + i);
1741
1742 if (i == 1)
1743 {
1744 for ( j = 0; j < 2; j++ )
1745 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1746 }
1747
1748 if (i == 0)
1749 {
1750 for ( j = 0; j < 2; j++ )
1751 ucSumVal += ( (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xF7) : (((MS_U8)(wRegVal & 0xFF00) >> 8) & 0x1F));
1752 }
1753
1754 if (i == 2)
1755 {
1756 for ( j = 0; j < 2; j++ )
1757 ucSumVal += ((j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xFB) : 0x00);
1758 }
1759 }
1760 break;
1761
1762 case E_HDMITX_MPEG_INFOFRAME:
1763 //TBD
1764 break;
1765
1766 case E_HDMITX_HDR_INFOFRAME:
1767 {
1768 MS_U8 u8PktLen = 0x00;
1769
1770 u8PktLen = (MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0xFF00) >> 8;
1771 ucSumVal += (E_HDMITX_HDR_INFOFRAME + (MS_U8)(MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0x00FF) + u8PktLen);
1772
1773 for ( i = 0; i < ((u8PktLen + 1) >> 1); i++ )
1774 {
1775 wRegVal = MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_10 + i);
1776
1777 for ( j = 0; j < 2; j++ )
1778 {
1779 if ((i == 0x0D) && (j % 2 == 0x00))
1780 ucSumVal += (j % 2 == 0) ? (MS_U8)(wRegVal & 0x00FF) : 0x00;
1781 else
1782 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1783 }
1784 }
1785 }
1786 break;
1787
1788 default:
1789 break;
1790 }
1791
1792 return (MS_U8)((~ucSumVal) + 0x01);
1793
1794 }
1795
1796 //------------------------------------------------------------------------------
1797 /// @brief This routine sets video output mode (color/repetition/regen)
1798 /// @param[in] idx: gHDMITxInfo.output_video_timing
1799 /// @return None
1800 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx,MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val,MsHDMITX_ANALOG_TUNING * pInfo,MS_U8 ubSSCEn)1801 void MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx, MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val, MsHDMITX_ANALOG_TUNING *pInfo, MS_U8 ubSSCEn)
1802 {
1803 //MS_U16 reg_value=0;
1804 MS_U8 ucCDIdx = 0;
1805 MS_U16 wHfront = 0;
1806 MS_U16 wVfront = 0;
1807 MS_BOOL bIsHDMI20 = FALSE;
1808 MS_BOOL bIs420Fmt = FALSE;
1809 MS_BOOL bIsRPMode = FALSE;
1810 MS_U32 uiTMDSCLK = 0;
1811
1812 //wilson@kano:TBD
1813 printf("video idx = 0x%X, color depth = 0x%X\r\n", idx, cd_val);
1814 // Deep color FIFO reset
1815 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, BIT10);
1816 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, 0);
1817 MsOS_DelayTask(10);
1818
1819 // Interlace mode
1820 if (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE)
1821 {
1822 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x005F);
1823 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x4000); //reg_interlace_mode_sel
1824 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2
1825 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0004); // PG interlace enable
1826 }
1827 else
1828 {
1829 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x004E);
1830 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x0000); //reg_interlace_mode_sel
1831 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0000); //video clock div 2
1832 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0000); // PG interlace disable
1833 }
1834
1835 #if 0
1836 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt != E_HDMITX_VIDEO_COLOR_YUV420) &&
1837 (
1838 (idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || \
1839 (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz) || \
1840 (
1841 (
1842 (idx == E_HDMITX_RES_1280x1470p_60Hz) || \
1843 (idx == E_HDMITX_RES_3840x2160p_24Hz) || \
1844 (idx == E_HDMITX_RES_3840x2160p_25Hz) || \
1845 (idx == E_HDMITX_RES_3840x2160p_30Hz) || \
1846 (idx == E_HDMITX_RES_4096x2160p_24Hz) || \
1847 (idx == E_HDMITX_RES_4096x2160p_25Hz) || \
1848 (idx == E_HDMITX_RES_4096x2160p_30Hz)
1849
1850 ) &&
1851 (
1852 (cd_val != E_HDMITX_VIDEO_CD_24Bits) && (cd_val != E_HDMITX_VIDEO_CD_NoID)
1853 )
1854 )
1855 ))
1856 bIsHDMI20 = TRUE;
1857
1858 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420) &&
1859 ((idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz)) &&
1860 (cd_val != E_HDMITX_VIDEO_CD_24Bits) && (cd_val != E_HDMITX_VIDEO_CD_NoID))
1861 bIsHDMI20 = TRUE;
1862 #else
1863 #endif
1864
1865 if (g_bSupportSCDC == TRUE)
1866 {
1867 //for 2.0
1868 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0100, bIsHDMI20 ? 0x0100 : 0x00);
1869 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_52, BIT0, bIsHDMI20 ? BIT0 : 0x00);
1870
1871 //scdc
1872 if (bIsHDMI20 == TRUE)
1873 Mhal_HDMITx_SCDCSetTmdsConfig(TRUE, TRUE);
1874 else
1875 Mhal_HDMITx_SCDCSetTmdsConfig(FALSE, FALSE);
1876 }
1877 else
1878 {
1879 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0100, 0x00);
1880 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_52, BIT0, 0x00);
1881 }
1882
1883 uiTMDSCLK = MHal_HDMITx_GetPixelClk_ByTiming(idx, gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt, cd_val);
1884 uiTMDSCLK /= 1000;
1885
1886 #if 0
1887 if (gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420)
1888 {
1889 switch (idx)
1890 {
1891 case E_HDMITX_RES_3840x2160p_50Hz:
1892 idx = E_HDMITX_RES_3840x2160p_25Hz;
1893 break;
1894
1895 case E_HDMITX_RES_3840x2160p_60Hz:
1896 idx = E_HDMITX_RES_3840x2160p_30Hz;
1897 break;
1898
1899 case E_HDMITX_RES_4096x2160p_50Hz:
1900 idx = E_HDMITX_RES_4096x2160p_25Hz;
1901 break;
1902
1903 case E_HDMITX_RES_4096x2160p_60Hz:
1904 idx = E_HDMITX_RES_4096x2160p_30Hz;
1905 break;
1906
1907 default:
1908 printf("[HDMITX] Invalid Combination of Color Format & Video Timing, Keep Origional Timing Setting!!\r\n");
1909 break;
1910 }
1911
1912 bIs420Fmt = TRUE;
1913 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2 for 420
1914 }
1915 #else
1916 #endif
1917
1918 #if 0
1919 if((idx == E_HDMITX_RES_720x480i) || (idx == E_HDMITX_RES_720x576i))
1920 {
1921 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x008B);
1922
1923 bIsRPMode = TRUE;
1924 }
1925 else
1926 {
1927 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x00AC);
1928
1929 bIsRPMode = FALSE;
1930 }
1931 #else
1932 #endif
1933
1934 //enable H, VSync regen
1935 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x8001, 0x8001);
1936 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0002, HDMITxVideoModeTbl[idx].h_polarity ? 0x0002 : 0x0000);
1937 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0004, HDMITxVideoModeTbl[idx].v_polarity ? 0x0004 : 0x0000);
1938
1939 ucCDIdx = (cd_val == 0)? 0x00 : (cd_val - 4);
1940
1941 //deep color setting
1942 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00C0, ucCDIdx << 6);
1943
1944 //HDMITx phy clock
1945 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0xCC0C, 0x0000);
1946
1947 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
1948
1949 //sythesizer setting
1950 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, (MS_U16)(HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0000FFFF));
1951 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x0FFF, (MS_U16)((HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0FFF0000) >> 16));
1952
1953 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1003, 0x0000);
1954 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_26, 0x0100, 0x0000);
1955
1956 //atop
1957 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x0003, HDMITxVideoAtopSetting[ucCDIdx][idx].MUX_DIVSEL_POST);
1958 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0xC000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 14);
1959 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x3000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_PIXEL << 12);
1960
1961 #if 0
1962 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
1963 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
1964 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012);
1965 #else //RD suggestion
1966 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, 0x0000);
1967 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, 0x0000);
1968 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, 0x0000);
1969 #endif
1970
1971 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
1972 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
1973 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012);
1974
1975 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x000F, HDMITxVideoAtopSetting[ucCDIdx][idx].PD_RT);
1976
1977
1978 // Timing regeneration
1979 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT10|BIT13, 0x0000/*BIT10|BIT13*/); // 0: delay from DE end; 1: delay from end of h, v sync
1980
1981 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_02, HDMITxVideoModeTbl[idx].vs_width);
1982 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_05, HDMITxVideoModeTbl[idx].vs_delayline);
1983 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_06, HDMITxVideoModeTbl[idx].vs_delaypixel);
1984 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_07, HDMITxVideoModeTbl[idx].hs_width >> (bIs420Fmt ? 0x01 : 0x00));
1985 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_0A, HDMITxVideoModeTbl[idx].hs_delay >> (bIs420Fmt ? 0x01 : 0x00));
1986
1987 //for PG
1988 wHfront = HDMITxVideoModeTbl[idx].hs_delay;
1989 wVfront = HDMITxVideoModeTbl[idx].vs_delayline;
1990
1991 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0003, 0x0003);
1992 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hde_width/4 - 1) : (HDMITxVideoModeTbl[idx].hde_width/2 - 1));
1993 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, (bIs420Fmt||bIsRPMode) ?
1994 ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/4 - 1) : ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/2 - 1));
1995 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (bIs420Fmt||bIsRPMode) ? (wHfront/4 - 1) : (wHfront/2 - 1));
1996 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hs_width/4 - 1) : (HDMITxVideoModeTbl[idx].hs_width/2 - 1));
1997
1998 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_35, HDMITxVideoModeTbl[idx].vde_width - 1);
1999 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_36, (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) ?
2000 ((HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width)/2 - 1) : (HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width - 1));
2001 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_37, wVfront - 1);
2002 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_38, HDMITxVideoModeTbl[idx].vs_width - 1);
2003
2004 MHal_HDMITx_EnableSSC(ubSSCEn, uiTMDSCLK);
2005
2006 // fifo reset
2007 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0x0008);
2008 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0);
2009 }
2010
2011 //------------------------------------------------------------------------------
2012 /// @brief This routine will power on or off HDMITx clock (power saving)
2013 /// @param[in] bEnable: TRUE/FALSE
2014 /// @return None
2015 //------------------------------------------------------------------------------
MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)2016 void MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)
2017 {
2018 if (bEnable)
2019 {
2020 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, 0);
2021 }
2022 else
2023 {
2024 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, BIT0);
2025 }
2026 }
2027
2028
MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq,MS_BOOL bflag)2029 MS_BOOL MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq, MS_BOOL bflag)
2030 {
2031 //wilson@kano:TBD
2032 #if 0
2033 return FALSE;
2034 #else
2035 printf("[HDMITx] Bypass Mode = 0x%d\r\n", bflag);
2036 if (bflag == TRUE)
2037 {
2038 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, BIT0); //reg_atop_en_clko_vcodiv8_syn
2039
2040 //Note: change frequency tolerance if need
2041 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2042 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2043 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2044 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2045 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2046 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2047 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //change 250Mhz -> 297Mhz
2048
2049 //Enable Fifo and select input source
2050 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1919); //selct clock from Rx;
2051
2052 #if 0
2053 if (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7A) & 0x00C0) //for HDMI 2.0 timing bypass mode
2054 {
2055 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, BIT0); //tmds clock div 2;
2056 }
2057 #endif
2058
2059 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x000E, 0x0004); //[1:0]: Lane 0 to fifo; [2]: enable
2060 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x000E, 0x0005); //[1:0]: Lane 1 to fifo; [2]: enable
2061 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x000E, 0x0006); //[1:0]: Lane 2 to fifo; [2]: enable
2062 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x000E, 0x0007); //[1:0]: Lane 3 to fifo; [2]: enable
2063
2064 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1000, 0x1000); //bit repetition HW mode;
2065
2066 //synthesizer setting //TBD
2067 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x0001, 0x0001);
2068 //ssc_set = 0x140000
2069 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, 0x0000); //ssc_set [15..0]
2070 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x00FF, 0x0014);//ssc_set [7..0]
2071
2072 #if 0 //with SSC clock
2073 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, ssc_step);
2074 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3000, ssc_span);
2075 #else //without SSC clock
2076 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, 0x0000);
2077 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3FFF, 0x0000);
2078 #endif
2079
2080 //ATOP setting
2081 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00); //[9]:en_clk_pixel;[11]:en_clk_tmds;[13..15]:en_data_out
2082 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0x0000); //[11..0]: disable power down;[15:12]:pre-emphasis
2083 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x007F, 0x000F); //[3:0]:rterm turn off;[6:4]:disable power down
2084 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x2001); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2085 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0200); //[9] hdmi20 hw config mode;
2086 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7E, 0x0200, 0x0200); //[9]: freq range tolerance up direction;
2087 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_60, 0x0001, 0x0001); //[0]: freq range reset follow rx big change;
2088 }
2089 else
2090 {
2091 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2092 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2093 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2094 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2095 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2096 }
2097
2098 return TRUE;
2099
2100 #endif
2101 }
2102
2103
2104 /// @brief This routine will disable TMDS clock, data, and DDC... bypass mode
2105 /// @return None
2106 //------------------------------------------------------------------------------
MHal_HDMITx_Disable_RxBypass(void)2107 MS_BOOL MHal_HDMITx_Disable_RxBypass(void)
2108 {
2109 #if 0
2110 return FALSE;
2111 #else
2112 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2113 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2114 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2115 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2116 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2117
2118 return TRUE;
2119 #endif
2120 }
2121
2122
2123 //------------------------------------------------------------------------------
2124 /// @brief This routine will set GPIO pin for HPD
2125 /// @param[in] u8pin: GPIO0 ~ 12
2126 /// @return None
2127 //------------------------------------------------------------------------------
MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)2128 void MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)
2129 {
2130 printf("_gHPDGpioPin = 0x%X\r\n", u8pin);
2131 _gHPDGpioPin = u8pin;
2132 }
2133
2134 //------------------------------------------------------------------------------
2135 /// @brief This routine return CHIP capability of DVI mode
2136 /// @return TRUE, FALSE
2137 //------------------------------------------------------------------------------
MHal_HDMITx_IsSupportDVIMode(void)2138 MS_BOOL MHal_HDMITx_IsSupportDVIMode(void)
2139 {
2140 return TRUE;
2141 }
2142
2143 // ************* For customer NDS **************//
2144
MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process,MsHDMITX_AVI_CONTENT_TYPE content_type,MS_U16 * data)2145 void MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process, MsHDMITX_AVI_CONTENT_TYPE content_type, MS_U16 *data)
2146 {
2147 MS_U16 tmp_value=0;
2148
2149 if (IS_STOP_PKT(packet_process)) // Stop sending packet
2150 {
2151 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000); // Stop AVI packet
2152 }
2153 else
2154 {
2155 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0080, 0x80); // EIA version 2
2156 switch(content_type)
2157 {
2158 case E_HDMITX_AVI_PIXEL_FROMAT:
2159 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0060, *data);
2160 break;
2161 case E_HDMITX_AVI_ASPECT_RATIO:
2162 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x3F1F, *data);
2163 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0003, *(data+1));
2164 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_4_0C, 0xFFFF, *(data+2));
2165 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_5_0D, 0xFFFF, *(data+3));
2166 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_6_0E, 0xFFFF, *(data+4));
2167 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0xFFFF, *(data+5));
2168 break;
2169 case E_HDMITX_AVI_COLORIMETRY:
2170 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xC000, *data);
2171 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0030, *(data+1));
2172 break;
2173 default:
2174 break;
2175 }
2176
2177 tmp_value = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME); // Checksum
2178 // cyclic packet
2179 if (IS_CYCLIC_PKT(packet_process))
2180 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ( (tmp_value<<8) | (HDMITX_PACKET_AVI_FCNT<<3) | 0x0005)); // send AVI packet
2181 // single packet
2182 else
2183 {
2184 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (tmp_value<<8) | 0x0001);
2185 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1<<E_HDMITX_ACT_AVI_CMD);
2186 }
2187 }
2188 }
2189
2190 //wilson@kano
2191 //**************************************************************************
2192 // [Function Name]:
2193 // MHal_HDMITx_SetGCPParameter()
2194 // [Description]:
2195 // setting General Control packet attribute
2196 // [Arguments]:
2197 // [stGC_PktPara] stPktPara
2198 // [Return]:
2199 // void
2200 //
2201 //**************************************************************************
MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)2202 void MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)
2203 {
2204 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enAVMute = stPktPara.enAVMute;
2205 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enColorDepInfo = stPktPara.enColorDepInfo;
2206 }
2207
2208 //**************************************************************************
2209 // [Function Name]:
2210 // MHal_HDMITx_SetPktAttribute()
2211 // [Description]:
2212 // configure settings to corresponding packet
2213 // [Arguments]:
2214 // [MsHDMITX_PACKET_TYPE] enPktType
2215 // [MS_BOOL] bEnUserDef
2216 // [MS_U8] u8FrmCntNum
2217 // [MsHDMITX_PACKET_PROCESS] enPktCtrl
2218 // [Return]:
2219 // void
2220 //
2221 //**************************************************************************
MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType,MS_BOOL bEnUserDef,MS_U8 u8FrmCntNum,MsHDMITX_PACKET_PROCESS enPktCtrl)2222 void MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType, MS_BOOL bEnUserDef, MS_U8 u8FrmCntNum, MsHDMITX_PACKET_PROCESS enPktCtrl)
2223 {
2224 if (enPktType & 0x80) //infoframe packet type
2225 {
2226 gbInfoFrmPktList[enPktType & (~0x80)].EnableUserDef = bEnUserDef;
2227 gbInfoFrmPktList[enPktType & (~0x80)].FrmCntNum = u8FrmCntNum;
2228 gbInfoFrmPktList[enPktType & (~0x80)].enPktCtrl = enPktCtrl;
2229 }
2230 else
2231 {
2232 gbGeneralPktList[enPktType].EnableUserDef = bEnUserDef;
2233 gbGeneralPktList[enPktType].FrmCntNum = u8FrmCntNum;
2234 gbGeneralPktList[enPktType].enPktCtrl = enPktCtrl;
2235 }
2236 }
2237
2238 //**************************************************************************
2239 // [Function Name]:
2240 // MHal_HDMITx_SetAVIInfoParameter()
2241 // [Description]:
2242 // Assign content to AVI Infoframe packet
2243 // [Arguments]:
2244 // [stAVIInfo_PktPara] stPktPara
2245 // [Return]:
2246 // void
2247 //
2248 //**************************************************************************
MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)2249 void MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)
2250 {
2251 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.A0Value = stPktPara.A0Value;
2252 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enableAFDoverWrite = stPktPara.enableAFDoverWrite;
2253 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorFmt = stPktPara.enColorFmt;
2254 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorimetry = stPktPara.enColorimetry;
2255 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enExtColorimetry = stPktPara.enExtColorimetry;
2256 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enYCCQuantRange = stPktPara.enYCCQuantRange;
2257 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enVidTiming = stPktPara.enVidTiming;
2258 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAFDRatio = stPktPara.enAFDRatio;
2259 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enScanInfo = stPktPara.enScanInfo;
2260 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAspectRatio = stPktPara.enAspectRatio;
2261 }
2262
2263 //**************************************************************************
2264 // [Function Name]:
2265 // MHal_HDMITx_SetVSInfoParameter()
2266 // [Description]:
2267 // Assign content to VendorSpecific Infoframe packet
2268 // [Arguments]:
2269 // [stVSInfo_PktPara] stPketPara
2270 // [Return]:
2271 // void
2272 //
2273 //**************************************************************************
MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)2274 void MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)
2275 {
2276 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en3DStruct = stPktPara.en3DStruct;
2277 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en4k2kVIC = stPktPara.en4k2kVIC;
2278 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.enVSFmt = stPktPara.enVSFmt;
2279 }
2280
2281 //**************************************************************************
2282 // [Function Name]:
2283 // MHal_HDMITx_SetVSInfoParameter()
2284 // [Description]:
2285 // Assign content to VendorSpecific Infoframe packet
2286 // [Arguments]:
2287 // [stVSInfo_PktPara] stPketPara
2288 // [Return]:
2289 // void
2290 //
2291 //**************************************************************************
MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)2292 void MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)
2293 {
2294 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudChCnt = stPktPara.enAudChCnt;
2295 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudType = stPktPara.enAudType;
2296 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudFreq = stPktPara.enAudFreq;
2297 }
2298
2299 //**************************************************************************
2300 // [Function Name]:
2301 // MHal_HDMITx_SendPacket()
2302 // [Description]:
2303 // configure packet content and process according to user define or defalut setting
2304 // [Arguments]:
2305 // [MsHDMITX_PACKET_TYPE] enPktType
2306 // [Return]:
2307 // void
2308 //
2309 //**************************************************************************
MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType,MsHDMITX_PACKET_PROCESS packet_process)2310 void MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType, MsHDMITX_PACKET_PROCESS packet_process)
2311 {
2312 if (enPktType & 0x80) //info frame packet
2313 {
2314 MS_U8 ucInfoPktType = enPktType & (~0x80);
2315 MS_U8 ucChkSum = 0;
2316
2317 gbInfoFrmPktList[ucInfoPktType].enPktCtrl = packet_process;
2318
2319 switch (enPktType)
2320 {
2321 case E_HDMITX_VS_INFOFRAME:
2322 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2323 {
2324 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, 0x0005, 0x0000);
2325 }
2326 else
2327 {
2328 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2329 {
2330 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2331
2332 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2333 {
2334 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2335 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2336 }
2337 else
2338 {
2339 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2340 }
2341 }
2342 else
2343 {
2344 //fill IEEE HDMI tag
2345 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27, 0xFFFF, 0x0C03);
2346
2347 //check content
2348 if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_3D)
2349 {
2350 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_3D << 13); // video format
2351 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en3DStruct) << 4); // 3D structure
2352 }
2353 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_4k_2k)
2354 {
2355 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_4k_2k << 13); // video format
2356 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en4k2kVIC)); // 4k2k vic
2357 }
2358 else
2359 {
2360 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, 0); // video format
2361 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, 0);
2362 }
2363
2364 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2365
2366 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2367 {
2368 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2369 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2370 }
2371 else
2372 {
2373 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum << 8) | (HDMITX_PACKET_VS_FCNT << 3) | 0x0005));
2374 }
2375 }
2376 }
2377 break;
2378
2379 case E_HDMITX_AVI_INFOFRAME:
2380 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2381 {
2382 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000);
2383 }
2384 else
2385 {
2386 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2387 {
2388 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
2389
2390 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2391 {
2392 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
2393 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
2394 }
2395 else
2396 {
2397 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2398 }
2399 }
2400 else
2401 {
2402 MS_U8 ucPktVal = 0;
2403
2404 //Y2, Y1, Y0: RGB, YCbCr 422, 444, 420
2405 ucPktVal = (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt << 5);// | 0x10;
2406 //A0 field
2407 ucPktVal |= ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.A0Value == 0x01) ? 0x10 : 0x00);
2408 //S1, S0 field
2409 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enScanInfo);
2410
2411 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x00FF, (MS_U16)ucPktVal); //MDrv_WriteByte(REG_HDMITX_09_L, ucPktVal);
2412
2413 #if 0
2414 //C1, C0, M1, M0
2415 if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2416 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p))
2417 {
2418 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2419 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio << 4);
2420 }
2421 else
2422 {
2423 //HD timing is always 16:9
2424 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2425 }
2426 #else
2427 {
2428 //HD timing is always 16:9
2429 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2430 }
2431 #endif
2432
2433 //R3, R2, R1, R0: active porting aspect ration
2434 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enableAFDoverWrite == TRUE)
2435 {
2436 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAFDRatio & 0x0F);
2437 }
2438
2439 //ucPktVal |= ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry == 0) ? 0 : 0xC0; //set [C1, C0] = [1, 1]
2440
2441 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorimetry != E_HDMITX_COLORIMETRY_MAX)
2442 {
2443 ucPktVal = (ucPktVal & 0x3F) | ( ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorimetry & 0x03) << 6);
2444 }
2445
2446 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xFF00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_09_H, ucPktVal);
2447
2448 //EC0, EC1, EC2
2449 ucPktVal = (MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry;
2450 ucPktVal = (ucPktVal > 6) ? 6 : ucPktVal; //BT2020 RGB & BT2020 YCbCr share same value 6; 7 is reserved;
2451 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0070, ucPktVal << 4); //MDrv_WriteByteMask(REG_HDMITX_0A_L, ucPktVal << 4, 0x70);
2452
2453 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_RGB444)
2454 {
2455 //Q1, Q0
2456 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2457 {
2458 ucPktVal = 1;
2459 }
2460 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2461 {
2462 ucPktVal = 2;
2463 }
2464 else
2465 {
2466 ucPktVal = 0;
2467 }
2468
2469 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, ucPktVal << 2);
2470 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, 0x00);
2471 }
2472 else
2473 {
2474 //YQ1, YQ0
2475 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2476 {
2477 ucPktVal = 0;
2478 }
2479 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2480 {
2481 ucPktVal = 1;
2482 }
2483 else
2484 {
2485 ucPktVal = 3;
2486 }
2487
2488 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, 0x00);
2489 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, ucPktVal << 6);
2490 }
2491
2492 //VIC code: VIC code shoud +1 if aspect ration is 16:9
2493 ucPktVal = HDMITX_AviVicTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2494
2495 #if 0
2496 if (((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2497 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p)) &&
2498 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_16_9))
2499 {
2500 ucPktVal += 1;
2501 }
2502 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_21_9)
2503 {
2504 MS_U8 AR21_9MappingTbl[14][2] = {
2505 {60, 65},
2506 {61, 66},
2507 {62, 67},
2508 {19, 68},
2509 { 4, 69},
2510 {41, 70},
2511 {47, 71},
2512 {32, 72},
2513 {33, 73},
2514 {34, 74},
2515 {31, 75},
2516 {16, 76},
2517 {64, 77},
2518 {63, 78}
2519 };
2520
2521 if ((ucPktVal >= 93) && (ucPktVal <= 97))//3840*2160p@24 ~ 3840*2160@60
2522 {
2523 ucPktVal += 10;
2524 }
2525 else if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_3840x2160p_24Hz) &&\
2526 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_3840x2160p_30Hz))
2527 {
2528 ucPktVal += (103 + (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming - E_HDMITX_RES_3840x2160p_24Hz));
2529 }
2530 else if ((ucPktVal > 78) && (ucPktVal <= 92))
2531 {
2532 //do nothing;
2533 }
2534 else
2535 {
2536 MS_U8 i = 0;
2537 MS_BOOL bValidVIC = FALSE;
2538
2539 for ( i = 0; i < 14; i++ )
2540 {
2541 if (AR21_9MappingTbl[i][0] == ucPktVal)
2542 {
2543 ucPktVal = AR21_9MappingTbl[i][1];
2544 bValidVIC = TRUE;
2545 break;
2546 }
2547 }
2548
2549 if (!bValidVIC)
2550 {
2551 printf("%s :: Invalid VIC Code for 21:9 Aspect Ratio!!!\r\n", __FUNCTION__);
2552 }
2553 }
2554 }
2555 #else
2556 #endif
2557
2558 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x7F00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_0A_H, (ucPktVal & 0x7F));
2559
2560 //check repetition
2561 #if 0
2562 if ((HDMITxVideoModeTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) &&
2563 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576i))
2564 {
2565 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0001); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x01, 0x0F);
2566 }
2567 else
2568 {
2569 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x00, 0x0F);
2570 }
2571 #else
2572 {
2573 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x00, 0x0F);
2574 }
2575 #endif
2576
2577 //YQ1, YQ0
2578 //MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, (MS_U8)(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange << 6));
2579
2580 //AVI version
2581 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0x0300, (MS_U16)(HDMITX_AVI_INFO_PKT_VER << 8));
2582 //MDrv_WriteByteMask(REG_HDMITX_0F_H, HDMITX_AVI_INFO_PKT_VER, 0x03);
2583
2584 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
2585
2586 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2587 {
2588 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
2589 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
2590 }
2591 else
2592 {
2593 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3) | 0x0005));
2594 //MDrv_Write2Byte(REG_HDMITX_10_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3));
2595 }
2596 }
2597 }
2598 break;
2599
2600 case E_HDMITX_SPD_INFOFRAME:
2601 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2602 {
2603 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, 0x0005, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_22_L, 0x00, 0x05);
2604 }
2605 else
2606 {
2607 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2608 {
2609 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
2610
2611 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2612 {
2613 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
2614 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
2615 }
2616 else
2617 {
2618 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2619 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3));
2620 }
2621 }
2622 else
2623 {
2624 MS_U8 i = 0;
2625 MS_U8 ucPktVal = 0;
2626
2627 for (i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN + 1) >> 1); i++)
2628 {
2629 if (i < 4) // vendor name
2630 {
2631 ucPktVal = (HDMITX_VendorName[2*i+1]<<8) | HDMITX_VendorName[2*i];
2632 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+i, 0x7F7F, ucPktVal);
2633 }
2634 else if ((i >= 4) && (i < 12)) // product description
2635 {
2636 ucPktVal = (HDMITX_ProductName[2*(i-4)+1]<<8) | HDMITX_ProductName[2*(i-4)];
2637 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_5_19+(i-4), 0x7F7F, ucPktVal);
2638 }
2639 else // source device information
2640 {
2641 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_13_21, 0x00FF, HDMITX_PACKET_SPD_SDI);
2642 }
2643 }
2644
2645 #if 0
2646 for ( i = 0; i < (HDMITX_SPD_INFO_PKT_LEN - 1); i++ )
2647 {
2648 if ( i < 8 )
2649 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_VendorName[i]);
2650 else
2651 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_ProductName[i-8]);
2652 }
2653
2654 MDrv_WriteByte(REG_HDMITX_21_L, 0x01); //SPD infoframe, byte25: source information: 0x01 = Digital STB
2655 #endif
2656
2657 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
2658
2659 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2660 {
2661 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
2662 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
2663 }
2664 else
2665 {
2666 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3) | 0x0005));
2667 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3));
2668 }
2669 }
2670 }
2671
2672 break;
2673
2674 case E_HDMITX_AUDIO_INFOFRAME:
2675 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2676 {
2677 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, 0x0005, 0x0000);
2678 }
2679 else
2680 {
2681 // Modified for HDMI CTS test -
2682 // - Audio Coding Type (CT3~CT0) is 0x0 then continue else then FAIL
2683 // - Sampling Frequency (SF2~ SF0) is zero then continue else then FAIL.
2684 // - Sample Size (SS1~ SS0) is zero then continue else then FAIL.
2685 //tmp_value = (gHDMITxInfo.output_audio_frequncy << 10) | 0x11; // audio sampling frequency, PCM and 2 channel.
2686 //MHal_HDMITx_Mask_Write(REG_HDMITX_BANK1, REG_PKT_AUD_1_11, 0x1FFF, tmp_value);
2687
2688 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt == E_HDMITX_AUDIO_CH_2) // 2-channel
2689 {
2690 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_2 - 1) & 0x07); // 2 channels
2691 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0); // Channel allocation
2692 }
2693 else //8- channel
2694 {
2695 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_8 - 1)&0x07); // 8 channels
2696 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0x1F00); // Channel allocation
2697 }
2698 //clear LFEP value
2699 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_3_13, 0x0001, 0x0000); //Fix LFEP defalut value in Kappa.
2700
2701 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AUDIO_INFOFRAME);
2702
2703 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2704 {
2705 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, (ucChkSum << 8) | 0x0001);
2706 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AUD_CMD);
2707 }
2708 else
2709 {
2710 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2711 {
2712 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2713 }
2714 else
2715 {
2716 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (HDMITX_PACKET_AUD_FCNT << 3) | 0x0005));
2717 }
2718 }
2719 }
2720
2721 //NOTE:: Kano move channel status from 0x00 to 0x0A
2722 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == FALSE)
2723 {
2724 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudType == E_HDMITX_AUDIO_PCM) ? 0 : BIT1)); // [1]: PCM / non-PCM
2725 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudFreq].CH_Status3 << 8) | (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
2726 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
2727 }
2728 // Audio sampling frequency
2729 // 1 1 0 0 32 kHz
2730 // 0 0 0 0 44.1 kHz
2731 // 0 0 0 1 88.2 kHz
2732 // 0 0 1 1 176.4 kHz
2733 // 0 1 0 0 48 kHz
2734 // 0 1 0 1 96 kHz
2735 // 0 1 1 1 192 kHz
2736 // 1 0 0 1 768 kHz
2737 break;
2738
2739 case E_HDMITX_MPEG_INFOFRAME:
2740 //TBD
2741 break;
2742
2743 case E_HDMITX_HDR_INFOFRAME:
2744 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2745 {
2746 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000);
2747 }
2748 else
2749 {
2750 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2751 {
2752 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
2753
2754 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2755 {
2756 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
2757 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
2758 }
2759 else
2760 {
2761 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2762 }
2763 }
2764 else
2765 {
2766 //TBD
2767 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
2768
2769 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2770 {
2771 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
2772 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
2773 }
2774 else
2775 {
2776 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCNT << 3) | 0x0005));
2777 }
2778
2779 }
2780 }
2781 break;
2782
2783 default:
2784 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
2785 break;
2786 }
2787 }
2788 else //general packet
2789 {
2790 gbGeneralPktList[enPktType].enPktCtrl = packet_process;
2791
2792 switch (enPktType)
2793 {
2794 case E_HDMITX_NULL_PACKET:
2795 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2796 {
2797 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x0005, 0x0000);
2798 }
2799 else
2800 {
2801 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2802 {
2803 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, 0x0001);
2804 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_NUL_CMD);
2805 }
2806 else
2807 {
2808 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2809 {
2810 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 3) |0x0005) );
2811 }
2812 else
2813 {
2814 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((HDMITX_PACKET_NULL_FCNT << 3) |0x0005) );
2815 }
2816 }
2817 }
2818 break;
2819
2820 case E_HDMITX_ACR_PACKET:
2821 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2822 {
2823 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x000F, 0x0008);
2824 }
2825 else
2826 {
2827 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2828 {
2829 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, 0x0009);
2830 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACR_CMD);
2831 }
2832 else //cyclic
2833 {
2834 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2835 {
2836 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 4) |0x05));
2837 }
2838 else
2839 {
2840 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((HDMITX_PACKET_ACR_FCNT << 4) |0x05));
2841 }
2842 }
2843 }
2844 break;
2845
2846 case E_HDMITX_AS_PACKET:
2847 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2848 {
2849 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable audio FIFO, [0]:audio FIFO flush
2850 }
2851 else
2852 {
2853 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT7); // [7]: enable audio FIFO, [0]:audio FIFO not flush
2854 }
2855 break;
2856
2857 case E_HDMITX_GC_PACKET:
2858 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2859 {
2860 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x000F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | 0x0000);
2861 }
2862 else
2863 {
2864 //fill color depth information
2865 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC12_04, 0x010F, gbGeneralPktList[enPktType].PktPara.GCPktPara.enColorDepInfo); // [8]: default phase = 0, [3:0]: Color depth
2866
2867 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2868 {
2869 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1)| 0x21); // [6]: 0, DC and non-DC info send together
2870 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_GCP_CMD);
2871 //MDrv_WriteByteMask(REG_HDMITX_03_L, 0x21, 0x7F);
2872 }
2873 else //cyclic
2874 {
2875 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2876 {
2877 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (gbGeneralPktList[enPktType].FrmCntNum << 4) | 0x29));
2878 }
2879 else
2880 {
2881 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (HDMITX_PACKET_GC_FCNT << 4) | 0x29));
2882 }
2883 }
2884 }
2885 break;
2886
2887 case E_HDMITX_ACP_PACKET:
2888 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2889 {
2890 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0005, 0x0000);
2891 }
2892 else
2893 {
2894 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_0_38, 0xFFFF, 0x0000); //acp type is 0x00
2895
2896 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2897 {
2898 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0001);
2899 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACP_CMD);
2900 }
2901 else //cyclic
2902 {
2903 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2904 {
2905 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
2906 }
2907 else
2908 {
2909 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, (HDMITX_PACKET_ACP_FCNT | 0x0005));
2910 }
2911 }
2912 }
2913 break;
2914
2915 case E_HDMITX_ISRC1_PACKET:
2916 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2917 {
2918 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
2919 }
2920 else
2921 {
2922 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2923 {
2924 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0001);
2925 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
2926 }
2927 else //cyclic
2928 {
2929 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2930 {
2931 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005)); }
2932 else
2933 {
2934 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
2935 }
2936 }
2937 }
2938 break;
2939
2940 case E_HDMITX_ISRC2_PACKET:
2941 //check ISRC cnt value
2942 if (MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51) & 0x8000)
2943 {
2944 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2945 {
2946 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
2947 }
2948 else
2949 {
2950 MS_U8 u8ISRCCntVal = 0x80;
2951
2952 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2953 {
2954 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, (u8ISRCCntVal << 8) | 0x0001 ); // 0x80: ISRC_CONT = 1, ISRC1 & ISRC2
2955 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
2956 }
2957 else //cyclic
2958 {
2959 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2960 {
2961 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
2962 }
2963 else
2964 {
2965 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
2966 }
2967 }
2968 }
2969 }
2970 break;
2971
2972 case E_HDMITX_DSD_PACKET:
2973 //TBD
2974 break;
2975
2976 case E_HDMITX_HBR_PACKET:
2977 //TBD
2978 break;
2979
2980 case E_HDMITX_GM_PACKET:
2981 //TBD
2982 break;
2983
2984 default:
2985 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
2986 break;
2987 }
2988 }
2989 }
2990
MHal_HDMITx_EnableSSC(MS_BOOL bEnable,MS_U32 uiTMDSCLK)2991 void MHal_HDMITx_EnableSSC(MS_BOOL bEnable, MS_U32 uiTMDSCLK)
2992 {
2993 //K6Lite does not implement SSC yet.
2994 #if 0
2995 #define HDMITX_MPLL_CLK 432 //432MHz
2996 #define HDMITX_SSC_CLK 30 //30KHz
2997 #define HDMITX_SSC_DEVIATION 1 // 0.1%
2998 #define HDMITX_SSC_DEVIATION_DIVIDER 1000
2999 #define HDMITX_SSC_THREAD_LEVEL1 150 ///1080p 8bits
3000 #define HDMITX_SSC_THREAD_LEVEL2 300 ///4K30 8bits
3001 #define HDMITX_SSC_SPAN_REG REG_HDMITxPHY_CONFIG_06
3002 #define HDMITX_SSC_STEP_REG REG_HDMITxPHY_CONFIG_07
3003 #define HDMITX_SSC_SUB_DIVIDER_REG REG_HDMITxPHY_CONFIG_01
3004
3005 MS_U32 ub2x19times = 524288;// 2^ 19
3006 MS_U32 dSYNCLK = 1;
3007 MS_U32 ub432MHz = HDMITX_MPLL_CLK;
3008 MS_U32 ubSSCClk = HDMITX_SSC_CLK;
3009 MS_U32 dSSc_Deviation= HDMITX_SSC_DEVIATION;
3010 MS_U32 ubSYNSet = 0;
3011 MS_U32 dSSC_Span = 0;
3012 MS_U32 dSSC_Step = 0;
3013 MS_U32 dPixel_Clk = 0;
3014
3015 if(!bEnable)
3016 {
3017 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, 0 );//Span
3018 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, 0);//Step
3019 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0 );//Sub-Divider
3020 return;
3021 }
3022
3023 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02);
3024 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16);
3025
3026 if(ubSYNSet != 0)
3027 dSYNCLK = ((ub432MHz*ub2x19times)/ubSYNSet);
3028
3029 if(ubSSCClk != 0)
3030 dSSC_Span = (dSYNCLK * 250) / (ubSSCClk); //Span = SYN_CLK_KHz / (SSC_CLK_KHz * 4)
3031
3032 if( (dSSC_Span != 0) && (HDMITX_SSC_DEVIATION_DIVIDER != 0) )
3033 dSSC_Step = (((ubSYNSet/ dSSC_Span)/HDMITX_SSC_DEVIATION_DIVIDER) * dSSc_Deviation) ; //Step = SYN_SET * deviation / Span
3034
3035 printf("ubSYNSet=%x, dSYNCLK=%d, dSSC_Span=%d, dSSC_Step=%d\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dSSC_Step);
3036
3037 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, ( ((int)dSSC_Span) & 0x3FFF) );//Span
3038 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, ( ((int)dSSC_Step) & 0xFFFF) );//Step
3039
3040 //Read tmds clock
3041 #if 0
3042 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_20, 0x3F, 0x3F);
3043 dPixel_Clk = ((MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_21) << 1) * 12 / 128);
3044 #else
3045 dPixel_Clk = uiTMDSCLK;
3046 #endif
3047 printf("dPixel_Clk=%d\r\n", dPixel_Clk);
3048
3049 if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL1)
3050 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x0000 );//Sub-Divider
3051 else if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL2)
3052 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x1000 );//Sub-Divider
3053 else
3054 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x3000 );//Sub-Divider
3055
3056 #endif
3057 }
3058
MHal_HDMITx_GetPixelClk_ByTiming(MsHDMITX_VIDEO_TIMING idx,MsHDMITX_VIDEO_COLOR_FORMAT color_fmt,MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth)3059 MS_U32 MHal_HDMITx_GetPixelClk_ByTiming(MsHDMITX_VIDEO_TIMING idx, MsHDMITX_VIDEO_COLOR_FORMAT color_fmt, MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth)
3060 {
3061 MS_U32 dwTMDSDataRate = 0;
3062 MS_U8 ubBitNum = 8;
3063
3064 switch(color_depth)
3065 {
3066 case E_HDMITX_VIDEO_CD_NoID:
3067 case E_HDMITX_VIDEO_CD_24Bits:
3068 {
3069 ubBitNum = 8;
3070 }
3071 break;
3072
3073 case E_HDMITX_VIDEO_CD_30Bits:
3074 {
3075 ubBitNum = 10;
3076 }
3077 break;
3078
3079 case E_HDMITX_VIDEO_CD_36Bits:
3080 {
3081 ubBitNum = 12;
3082 }
3083 break;
3084
3085 case E_HDMITX_VIDEO_CD_48Bits:
3086 {
3087 ubBitNum = 16;
3088 }
3089 break;
3090
3091 default:
3092 {
3093 ubBitNum = 8;
3094 }
3095 break;
3096 }
3097
3098 dwTMDSDataRate = (HDMITxVideoModeTbl[idx].pixel_clk/1000) * ubBitNum / 8;
3099
3100 if(color_fmt == E_HDMITX_VIDEO_COLOR_YUV420)
3101 dwTMDSDataRate = dwTMDSDataRate/2;
3102
3103 //printf("Time_ID = %d, C_FMT = %d, C_DEP = %d, PXL_CLK = %d\r\n", idx, color_fmt, color_depth, dwTMDSDataRate);
3104 return dwTMDSDataRate;
3105 }
3106
MHal_HDMITx_GetMaxPixelClk(void)3107 MS_U32 MHal_HDMITx_GetMaxPixelClk(void)
3108 {
3109 return HDMITX_MAX_PIXEL_CLK/1000;
3110 }
3111
MHal_HDMITx_SetVideoInfoByCustomer(MsHDMITX_VIDEO_TIMING idx,stHDMITX_TIMING_INFO_BY_CUSTOMER stTimingInfo)3112 void MHal_HDMITx_SetVideoInfoByCustomer(MsHDMITX_VIDEO_TIMING idx, stHDMITX_TIMING_INFO_BY_CUSTOMER stTimingInfo)
3113 {
3114
3115 HDMITxVideoModeTbl[idx].i_p_mode = stTimingInfo.i_p_mode;
3116 HDMITxVideoModeTbl[idx].h_polarity = stTimingInfo.h_polarity;
3117 HDMITxVideoModeTbl[idx].v_polarity = stTimingInfo.v_polarity;
3118 HDMITxVideoModeTbl[idx].vs_width = stTimingInfo.vs_width;
3119 HDMITxVideoModeTbl[idx].vs_bporch = stTimingInfo.vs_bporch;
3120 HDMITxVideoModeTbl[idx].vde_width = stTimingInfo.vde_width;
3121 HDMITxVideoModeTbl[idx].hs_width = stTimingInfo.hs_width;
3122 HDMITxVideoModeTbl[idx].hs_bporch = stTimingInfo.hs_bporch;
3123 HDMITxVideoModeTbl[idx].hde_width = stTimingInfo.hde_width;
3124 HDMITxVideoModeTbl[idx].vtotal = stTimingInfo.vtotal;
3125 HDMITxVideoModeTbl[idx].htotal = stTimingInfo.htotal;
3126 HDMITxVideoModeTbl[idx].vs_delayline = stTimingInfo.vs_delayline;
3127 HDMITxVideoModeTbl[idx].vs_delaypixel = stTimingInfo.vs_delaypixel;
3128 HDMITxVideoModeTbl[idx].hs_delay = stTimingInfo.hs_delay;
3129
3130 printf("Video idx : %d\r\n",idx);
3131 printf("VSync : %X\r\n",HDMITxVideoModeTbl[idx].vs_width);
3132 printf("VBporch : %X\r\n",HDMITxVideoModeTbl[idx].vs_bporch);
3133 printf("VDE : %X\r\n",HDMITxVideoModeTbl[idx].vde_width);
3134 printf("HSync : %X\r\n",HDMITxVideoModeTbl[idx].hs_width);
3135 printf("HBporch : %X\r\n",HDMITxVideoModeTbl[idx].hs_bporch);
3136 printf("HDE : %X\r\n",HDMITxVideoModeTbl[idx].hde_width);
3137 printf("VTotal : %X\r\n",HDMITxVideoModeTbl[idx].vtotal);
3138 printf("HTotal : %X\r\n",HDMITxVideoModeTbl[idx].htotal);
3139 printf("i_p_mode : %X\r\n",HDMITxVideoModeTbl[idx].i_p_mode);
3140 printf("h_polarity : %X\r\n",HDMITxVideoModeTbl[idx].h_polarity);
3141 printf("v_polarity : %X\r\n",HDMITxVideoModeTbl[idx].v_polarity);
3142 printf("vs_delayline : %X\r\n",HDMITxVideoModeTbl[idx].vs_delayline);
3143 printf("vs_delaypixel : %X\r\n",HDMITxVideoModeTbl[idx].vs_delaypixel);
3144 printf("hs_delay : %X\r\n",HDMITxVideoModeTbl[idx].hs_delay);
3145 }
3146
3147
3148
3149