1 //<MStar Software>
2 //******************************************************************************
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #define MHAL_HDMITX_C
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 // Common Definition
101 #ifdef MSOS_TYPE_LINUX_KERNEL
102 #include <linux/string.h>
103 #else
104 #include <string.h>
105 #endif
106
107 #include "MsCommon.h"
108
109 // Internal Definition
110 #include "regHDMITx.h"
111 #include "halHDMIUtilTx.h"
112 #include "halHDMITx.h"
113 #include "drvHDMITx.h"
114
115 // External Definition
116 #include "drvGPIO.h"
117 #include "drvSYS.h"
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126
127 #define GENERAL_PKT_NUM 0x0BU //wilson@kano
128 #define INFOFRM_PKT_NUM 0x08U //for HDR packet ID = 0x87; 0x06U //wilson@kano
129
130
131 #define HDMITX_VS_INFO_PKT_VER 0x01U
132 #define HDMITX_VS_INFO_PKT_LEN 0x1BU
133
134 #define HDMITX_AVI_INFO_PKT_VER 0x02U
135 #define HDMITX_AVI_INFO_PKT_LEN 0x0DU
136
137 #define HDMITX_SPD_INFO_PKT_VER 0x01U
138 #define HDMITX_SPD_INFO_PKT_LEN 0x19U
139
140 #define HDMITX_AUD_INFO_PKT_VER 0x01U
141 #define HDMITX_AUD_INFO_PKT_LEN 0x0AU
142
143 #define HDMITX_HDR_INFO_PKT_VER 0x01U
144 #define HDMITX_HDR_INFO_PKT_LEN 0x1BU //wilson@kano: temp solution
145
146
147
148 #define IS_STOP_PKT(_X_) ( (_X_ & E_HDMITX_STOP_PACKET) ? 1 : 0 )
149 #define IS_CYCLIC_PKT(_X_) ( (_X_ & E_HDMITX_CYCLIC_PACKET) ? 1 : 0 )
150
151 // HDMI packet cyclic frame count
152 #define HDMITX_PACKET_NULL_FCNT 0U ///< 0 ~ 31
153 #define HDMITX_PACKET_ACR_FCNT 0U ///< 0 ~ 15
154 #define HDMITX_PACKET_GC_FCNT 0U ///< 0 ~ 1
155 #define HDMITX_PACKET_ACP_FCNT 15U ///< 0 ~ 31
156 #define HDMITX_PACKET_ISRC_FCNT 15U ///< 0 ~ 31
157
158 #define HDMITX_PACKET_VS_FCNT 0U ///< 0 ~ 31
159 #define HDMITX_PACKET_AVI_FCNT 0U ///< 0 ~ 31
160 #define HDMITX_PACKET_SPD_FCNT 1U ///< 0 ~ 31
161 #define HDMITX_PACKET_AUD_FCNT 0U ///< 0 ~ 31
162 #define HDMITX_PACKET_HDR_FCNT 0U
163
164 #define HDMITX_PACKET_SPD_SDI 1U // Digital STB
165 #define HDMITX_CSC_SUPPORT_R2Y 1U
166 #define HDMITX_SUPPORT_P2I 1U
167 #define HDMITX_SUPPORT_444TO420 1U
168
169 //-------------------------------------------------------------------------------------------------
170 // Local Structures
171 //-------------------------------------------------------------------------------------------------
172
173 //*********************//
174 // Video //
175 //*********************//
176
177 typedef enum
178 {
179 E_HDMITX_VIDEO_INTERLACE_MODE = 0,
180 E_HDMITX_VIDEO_PROGRESSIVE_MODE = 1,
181 } MDrv_HDMITx_VIDEO_MODE;
182
183 typedef enum
184 {
185 E_HDMITX_VIDEO_POLARITY_HIGH = 0,
186 E_HDMITX_VIDEO_POLARITY_LOW = 1,
187 } MDrv_HDMITx_VIDEO_POLARITY;
188
189 typedef struct
190 {
191 MDrv_HDMITx_VIDEO_MODE i_p_mode; // interlace / progressive mode
192 MDrv_HDMITx_VIDEO_POLARITY h_polarity; // Hsync polarity
193 MDrv_HDMITx_VIDEO_POLARITY v_polarity; // Vsync polarity
194 MS_U16 vs_width; // Vsync pulse width
195 MS_U16 vs_bporch; // Vsync back-porch
196 MS_U16 vde_width; // Vde active width
197 MS_U16 vs_delayline; // Vsync line delay
198 MS_U16 vs_delaypixel; // Vsync pixel delay
199 MS_U16 hs_width; // Hsync pulse width
200 MS_U16 hs_bporch; // Hsync back-porch
201 MS_U16 hde_width; // Hde active width
202 MS_U16 hs_delay; // Hsync delay
203 MS_U16 vtotal; // Vsync total
204 MS_U16 htotal; // Hsync total
205 } MDrv_HDMITx_VIDEO_MODE_INFO_TYPE;
206
207 //*********************//
208 // Packet //
209 //*********************//
210
211 typedef enum
212 {
213 E_HDMITX_ACT_GCP_CMD = 0,
214 E_HDMITX_ACT_ACR_CMD = 1,
215 E_HDMITX_ACT_AVI_CMD = 2,
216 E_HDMITX_ACT_AUD_CMD = 3,
217 E_HDMITX_ACT_SPD_CMD = 4,
218 E_HDMITX_ACT_MPG_CMD = 5,
219 E_HDMITX_ACT_VSP_CMD = 6,
220 E_HDMITX_ACT_NUL_CMD = 7,
221 E_HDMITX_ACT_ACP_CMD = 8,
222 E_HDMITX_ACT_ISRC_CMD = 9,
223 E_HDMITX_ACT_GCP_DC_CMD = 10, // GCP with non-zero CD
224 E_HDMITX_ACT_GMP_CMD = 11, // Gamut Metadata packet
225 } MDrvHDMITX_PKTS_ACT_CMD;
226
227 typedef struct PKT
228 {
229 MS_BOOL User_Define;
230 MsHDMITX_PACKET_PROCESS Define_Process;
231 MS_U8 Define_FCnt;
232 }PKT_Behavior;
233 //*********************//
234 // Audio //
235 //*********************//
236 typedef struct
237 {
238 MS_U8 CH_Status3;
239 MS_U32 NcodeValue;
240 } MDrv_HDMITx_AUDIO_FREQ_TYPE;
241
242 //-------------------------------------------------------------------------------------------------
243 // Global Variables
244 //-------------------------------------------------------------------------------------------------
245 MS_U8 gDivider = 0x00;
246 MS_BOOL gDivFlag = FALSE;
247 static MS_U8 gu8ChipVerNum = 0x00;
248
249 stHDMITx_PKT_ATTRIBUTE gbGeneralPktList[GENERAL_PKT_NUM]; //wilson@kano
250 stHDMITx_PKT_ATTRIBUTE gbInfoFrmPktList[INFOFRM_PKT_NUM]; //wilson@kano
251
252 // User defined packet behavior
253 PKT_Behavior NULL_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
254 PKT_Behavior ACR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
255 PKT_Behavior AS_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
256 PKT_Behavior GC_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
257 PKT_Behavior ACP_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
258 PKT_Behavior ISRC1_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
259 PKT_Behavior ISRC2_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
260 PKT_Behavior DSD_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
261 PKT_Behavior HBR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
262 PKT_Behavior GM_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
263
264 PKT_Behavior VS_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
265 PKT_Behavior AVI_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
266 PKT_Behavior SPD_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
267 PKT_Behavior AUDIO_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
268 PKT_Behavior MPEG_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
269 //-------------------------------------------------------------------------------------------------
270 // Local Variables
271 //-------------------------------------------------------------------------------------------------
272
273 //*********************//
274 // Video //
275 //*********************//
276
277 // It should be mapped with MsHDMITX_VIDEO_TIMING structure in drvHDMITx.h
278 MDrv_HDMITx_VIDEO_MODE_INFO_TYPE HDMITxVideoModeTbl[E_HDMITX_RES_MAX]=
279 {
280 //IorPMode; PolarityH; PolarityV; VSW; VbckP; VDe; VSDel; VSDelP; HSW; HbckP; HDe; HSDel; VSTotal; HSTotal;
281 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0002, 0x0021, 0x01E0, 0x000A, 0, 0x0060, 0x0030, 0x0280, 0x0010, 0x020D, 0x0320}, // 0: 640x480p
282 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x000F, 0x01E0, 0x0004, 0, 0x007C, 0x0072, 0x05A0, 0x0026, 0x020D, 0x06B4}, // 1: 720x480i
283 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x0013, 0x0240, 0x0002, 0, 0x007E, 0x008A, 0x05A0, 0x0018, 0x0271, 0x06C0}, // 2: 720x576i
284 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0006, 0x001E, 0x01E0, 0x0009, 0, 0x003E, 0x003C, 0x02D0, 0x0010, 0x020D, 0x035A}, // 3: 720x480p
285 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0005, 0x0027, 0x0240, 0x0005, 0, 0x0040, 0x0044, 0x02D0, 0x000C, 0x0271, 0x0360}, // 4: 720x576p
286 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x02EE, 0x07BC}, // 5: 1280x720p_50Hz
287 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x02EE, 0x0672}, // 6: 1280x720p_60Hz
288 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50}, // 7: 1920x1080i_50Hz
289 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898}, // 8: 1920x1080i_60Hz
290 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x0465, 0x0ABE}, // 9: 1920x1080p_24Hz
291 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50}, // 10: 1920x1080p_25Hz
292 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898}, // 11: 1920x1080p_30Hz
293 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50}, // 12: 1920x1080p_50Hz
294 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898}, // 13: 1920x1080p_60Hz
295 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x089D, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x08CA, 0x0ABE}, // 14: 1920x2205p_24Hz
296 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x05DC, 0x07BC}, // 15: 1280x1470p_50Hz
297 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x05DC, 0x0672}, // 16: 1280x1470p_60Hz
298 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
299 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x04FC, 0x08CA, 0x157C}, // 17:93: 3840x2160p_24Hz
300 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0}, // 18:94: 3840x2160p_25Hz
301 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130}, // 19:95: 3840x2160p_30Hz
302 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0}, // 20:96: 3840x2160p_50Hz
303 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130}, // 21:97: 3840x2160p_60Hz
304
305 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x1000, 0x03FC, 0x08CA, 0x157C}, // 22:98: 4096x2160p_24Hz
306 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0}, // 23:99: 4096x2160p_25Hz
307 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130}, // 24:100: 4096x2160p_30Hz
308 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0}, // 25:101: 4096x2160p_50Hz
309 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130}, // 26:102: 4096x2160p_60Hz
310 };
311
312 //atop setting
313 stHDMITx_ATOP_SETTING HDMITxVideoAtopSetting[HDMITX_COLOR_DEPTH_TYPE_NUM][E_HDMITX_RES_MAX] =
314 {
315 //color depth = 8bit
316 {
317 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
318 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
319 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
320 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
321 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
322 // 74Mhz
323 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
324 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
325 #if (defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
326 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
327 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 8: 1920x1080i_60Hz
328 #else
329 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
330 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
331 #endif
332 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
333 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
334 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
335 // 148Mhz
336 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 12: 1920x1080p_50Hz
337 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 13: 1920x1080p_60Hz
338 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 14: 1920x2205p_24Hz
339 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 15: 1280x1470p_50Hz
340 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 16: 1280x1470p_60Hz
341 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
342 // 300Mhz
343 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
344 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
345 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
346 // 600Mhz
347 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
348 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
349 // 300Mhz
350 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
351 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
352 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
353 // 600Mhz
354 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
355 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
356 },
357
358 //color depth = 10 bit
359 {
360 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 0: 640x480p
361 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 1: 720x480i
362 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 2: 720x576i
363 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 3: 720x480p
364 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 4: 720x576p
365 // 74Mhz
366 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 5: 1280x720p_50Hz
367 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 6: 1280x720p_60Hz
368 #if (defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
369 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 7: 1920x1080i_50Hz
370 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 8: 1920x1080i_60Hz
371 #else
372 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 7: 1920x1080i_50Hz
373 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x25460A}, // 8: 1920x1080i_60Hz
374 #endif
375 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 9: 1920x1080p_24Hz
376 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 10: 1920x1080p_25Hz
377 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 11: 1920x1080p_30Hz
378 // 148Mhz
379 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 12: 1920x1080p_50Hz
380 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 13: 1920x1080p_60Hz
381 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 14: 1920x2205p_24Hz
382 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 15: 1280x1470p_50Hz
383 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 16: 1280x1470p_60Hz
384 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
385 // 300Mhz
386 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 17:93: 3840x2160p_24Hz
387 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 18:94: 3840x2160p_25Hz
388 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 19:95: 3840x2160p_30Hz
389 // 600Mhz ==> not support !!!
390 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 20:96: 3840x2160p_50Hz
391 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 21:97: 3840x2160p_60Hz
392 // 300Mhz
393 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 22:98: 4096x2160p_24Hz
394 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 23:99: 4096x2160p_25Hz
395 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 24:100: 4096x2160p_30Hz
396 // 600Mhz ==> not support !!!
397 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 25:101: 4096x2160p_50Hz
398 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 26:102: 4096x2160p_60Hz
399 },
400
401 //color depth = 12 bit
402 {
403 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 0: 640x480p
404 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 1: 720x480i
405 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 2: 720x576i
406 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 3: 720x480p
407 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 4: 720x576p
408 // 74Mhz
409 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 5: 1280x720p_50Hz
410 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 6: 1280x720p_60Hz
411 #if (defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
412 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 7: 1920x1080i_50Hz
413 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 8: 1920x1080i_60Hz
414 #else
415 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 7: 1920x1080i_50Hz
416 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F0FB3}, // 8: 1920x1080i_60Hz
417 #endif
418 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 9: 1920x1080p_24Hz
419 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 10: 1920x1080p_25Hz
420 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 11: 1920x1080p_30Hz
421 // 148Mhz
422 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 12: 1920x1080p_50Hz
423 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 13: 1920x1080p_60Hz
424 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 14: 1920x2205p_24Hz
425 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 15: 1280x1470p_50Hz
426 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 16: 1280x1470p_60Hz
427 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
428 // 300Mhz
429 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 17:93: 3840x2160p_24Hz
430 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 18:94: 3840x2160p_25Hz
431 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 19:95: 3840x2160p_30Hz
432 // 600Mhz ==> not support !!!
433 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 20:96: 3840x2160p_50Hz
434 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 21:97: 3840x2160p_60Hz
435 // 300Mhz
436 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 22:98: 4096x2160p_24Hz
437 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 23:99: 4096x2160p_25Hz
438 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 24:100: 4096x2160p_30Hz
439 // 600Mhz ==> not support !!!
440 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 25:101: 4096x2160p_50Hz
441 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 26:102: 4096x2160p_60Hz
442 },
443
444 //color depth = 16 bit
445 {
446 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
447 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
448 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
449 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
450 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
451 // 74Mhz
452 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
453 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
454 #if (defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
455 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 7: 1920x1080i_50Hz
456 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 8: 1920x1080i_60Hz
457 #else
458 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
459 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
460 #endif
461 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
462 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
463 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
464 // 148Mhz
465 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 12: 1920x1080p_50Hz
466 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 13: 1920x1080p_60Hz
467 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 14: 1920x2205p_24Hz
468 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 15: 1280x1470p_50Hz
469 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 16: 1280x1470p_60Hz
470 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
471 // 300Mhz
472 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
473 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
474 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
475 // 600Mhz ==> Not support !!!
476 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
477 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
478 // 300Mhz
479 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
480 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
481 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
482 // 600Mhz ==> Not support !!!
483 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
484 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
485 },
486 };
487
488 #if( defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1) )
489 //For Maxim 420 and Interlace Only HDMITXPHY_0x15[14:12]
490 MS_U8 HDMITxVideo_OTMDS_ODATA_Ratio[HDMITX_COLOR_DEPTH_TYPE_NUM][E_HDMITX_RES_MAX] =
491 {
492 //color depth = 8bit
493 {
494 0x03, // 0: 640x480p
495 0x03, // 1: 720x480i
496 0x03, // 2: 720x576i
497 0x03, // 3: 720x480p
498 0x03, // 4: 720x576p
499 // 74Mhz
500 0x02, // 5: 1280x720p_50Hz
501 0x02, // 6: 1280x720p_60Hz
502 0x02, // 7: 1920x1080i_50Hz
503 0x02, // 8: 1920x1080i_60Hz
504 0x02, // 9: 1920x1080p_24Hz
505 0x02, // 10: 1920x1080p_25Hz
506 0x02, // 11: 1920x1080p_30Hz
507 // 148Mhz
508 0x02, // 12: 1920x1080p_50Hz
509 0x02, // 13: 1920x1080p_60Hz
510 0x02, // 14: 1920x2205p_24Hz
511 0x02, // 15: 1280x1470p_50Hz
512 0x02, // 16: 1280x1470p_60Hz
513 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
514 // 300Mhz
515 0x02, // 17:93: 3840x2160p_24Hz
516 0x02, // 18:94: 3840x2160p_25Hz
517 0x02, // 19:95: 3840x2160p_30Hz
518 // 600Mhz
519 0x01, // 20:96: 3840x2160p_50Hz
520 0x01, // 21:97: 3840x2160p_60Hz
521 // 300Mhz
522 0x02, // 22:98: 4096x2160p_24Hz
523 0x02, // 23:99: 4096x2160p_25Hz
524 0x02, // 24:100: 4096x2160p_30Hz
525 // 600Mhz
526 0x01, // 25:101: 4096x2160p_50Hz
527 0x01, // 26:102: 4096x2160p_60Hz
528 },
529
530 //color depth = 10 bit
531 {
532 0x03, // 0: 640x480p
533 0x03, // 1: 720x480i
534 0x03, // 2: 720x576i
535 0x03, // 3: 720x480p
536 0x03, // 4: 720x576p
537 // 74Mhz
538 0x02, // 5: 1280x720p_50Hz
539 0x02, // 6: 1280x720p_60Hz
540 0x02, // 7: 1920x1080i_50Hz
541 0x02, // 8: 1920x1080i_60Hz
542 0x02, // 9: 1920x1080p_24Hz
543 0x02, // 10: 1920x1080p_25Hz
544 0x02, // 11: 1920x1080p_30Hz
545 // 148Mhz
546 0x02, // 12: 1920x1080p_50Hz
547 0x02, // 13: 1920x1080p_60Hz
548 0x02, // 14: 1920x2205p_24Hz
549 0x02, // 15: 1280x1470p_50Hz
550 0x02, // 16: 1280x1470p_60Hz
551 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
552 // 300Mhz
553 0x02, // 17:93: 3840x2160p_24Hz
554 0x02, // 18:94: 3840x2160p_25Hz
555 0x02, // 19:95: 3840x2160p_30Hz
556 // 600Mhz ==> not support !!!
557 0x00, // 20:96: 3840x2160p_50Hz
558 0x00, // 21:97: 3840x2160p_60Hz
559 // 300Mhz
560 0x02, // 22:98: 4096x2160p_24Hz
561 0x02, // 23:99: 4096x2160p_25Hz
562 0x02, // 24:100: 4096x2160p_30Hz
563 // 600Mhz ==> not support !!!
564 0x00, // 25:101: 4096x2160p_50Hz
565 0x00, // 26:102: 4096x2160p_60Hz
566 },
567
568 //color depth = 12 bit
569 {
570 0x03, // 0: 640x480p
571 0x03, // 1: 720x480i
572 0x03, // 2: 720x576i
573 0x03, // 3: 720x480p
574 0x03, // 4: 720x576p
575 // 74Mhz
576 0x02, // 5: 1280x720p_50Hz
577 0x02, // 6: 1280x720p_60Hz
578 0x02, // 7: 1920x1080i_50Hz
579 0x02, // 8: 1920x1080i_60Hz
580 0x02, // 9: 1920x1080p_24Hz
581 0x02, // 10: 1920x1080p_25Hz
582 0x02, // 11: 1920x1080p_30Hz
583 // 148Mhz
584 0x02, // 12: 1920x1080p_50Hz
585 0x02, // 13: 1920x1080p_60Hz
586 0x02, // 14: 1920x2205p_24Hz
587 0x02, // 15: 1280x1470p_50Hz
588 0x02, // 16: 1280x1470p_60Hz
589 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
590 // 300Mhz
591 0x02, // 17:93: 3840x2160p_24Hz
592 0x02, // 18:94: 3840x2160p_25Hz
593 0x02, // 19:95: 3840x2160p_30Hz
594 // 600Mhz ==> not support !!!
595 0x00, // 20:96: 3840x2160p_50Hz
596 0x00, // 21:97: 3840x2160p_60Hz
597 // 300Mhz
598 0x02, // 22:98: 4096x2160p_24Hz
599 0x02, // 23:99: 4096x2160p_25Hz
600 0x02, // 24:100: 4096x2160p_30Hz
601 // 600Mhz ==> not support !!!
602 0x00, // 25:101: 4096x2160p_50Hz
603 0x00, // 26:102: 4096x2160p_60Hz
604 },
605
606 //color depth = 16 bit
607 {
608 0x02, // 0: 640x480p
609 0x02, // 1: 720x480i
610 0x02, // 2: 720x576i
611 0x02, // 3: 720x480p
612 0x02, // 4: 720x576p
613 // 74Mhz
614 0x01, // 5: 1280x720p_50Hz
615 0x01, // 6: 1280x720p_60Hz
616 0x01, // 7: 1920x1080i_50Hz
617 0x01, // 8: 1920x1080i_60Hz
618 0x01, // 9: 1920x1080p_24Hz
619 0x01, // 10: 1920x1080p_25Hz
620 0x01, // 11: 1920x1080p_30Hz
621 // 148Mhz
622 0x01, // 12: 1920x1080p_50Hz
623 0x01, // 13: 1920x1080p_60Hz
624 0x01, // 14: 1920x2205p_24Hz
625 0x01, // 15: 1280x1470p_50Hz
626 0x01, // 16: 1280x1470p_60Hz
627 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
628 // 300Mhz
629 0x01, // 17:93: 3840x2160p_24Hz
630 0x01, // 18:94: 3840x2160p_25Hz
631 0x01, // 19:95: 3840x2160p_30Hz
632 // 600Mhz ==> Not support !!!
633 0x00, // 20:96: 3840x2160p_50Hz
634 0x00, // 21:97: 3840x2160p_60Hz
635 // 300Mhz
636 0x01, // 22:98: 4096x2160p_24Hz
637 0x01, // 23:99: 4096x2160p_25Hz
638 0x01, // 24:100: 4096x2160p_30Hz
639 // 600Mhz ==> Not support !!!
640 0x00, // 25:101: 4096x2160p_50Hz
641 0x00, // 26:102: 4096x2160p_60Hz
642 },
643 };
644 #endif
645
646 //*********************//
647 // Audio //
648 //*********************//
649
650 MSTHDMITX_REG_TYPE HDMITxAudioOnTbl[] =
651 {
652 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enable audio FIFO, [2]:enable CTS Gen, [1]: automatically block start, [0]: audio FIFO not flush
653 };
654
655 MSTHDMITX_REG_TYPE HDMITxAudioOffTbl[] =
656 {
657 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
658 };
659
660 MSTHDMITX_REG_TYPE HDMITxAudioInitTbl[] =
661 {
662 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
663 };
664
665 MDrv_HDMITx_AUDIO_FREQ_TYPE TxAudioFreqTbl[E_HDMITX_AUDIO_FREQ_MAX_NUM] =
666 {
667 {0x02, 0x001800}, // No signal, set to 48 KHz
668 {0x03, 0x001000}, // 0 ~(32)~ 38 KHz, 4096
669 {0x00, 0x001880}, // 38 ~(44.1)~ 46 KHz, 6272
670 {0x02, 0x001800}, // 46 ~(48)~ 60 KHz, 6144
671 {0x08, 0x003100}, // 60 ~(88.2)~ 92 KHz, 12544
672 {0x0a, 0x003000}, // 92 ~(96)~ 140 KHz, 12288
673 {0x0c, 0x006200}, // 140 ~(176.4)~ 180 KHz, 25088
674 {0x0e, 0x006000}, // 180 ~(192)~ ~~ KHz, 24576
675 };
676
677 //*********************//
678 // Packet //
679 //*********************//
680
681 MS_U8 HDMITX_AviCmrTbl[E_HDMITX_RES_MAX] =
682 {
683 0x48, 0x48, 0x48, 0x48, 0x48, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, // SDTV C=01(601),M=00(no data) ,R=1000(same)
684 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8,
685 };
686
687 MS_U8 HDMITX_AviVicTbl[E_HDMITX_RES_MAX] =
688 {
689 1, 6, 21, 2, 17, 19, 4, 20, 5, 32, 33, 34, 31, 16, // SDTV 480i60,576i50,480p60,576p50,720p50,720p60,1080i50,1080i60,1080p24,1080p25,1080p30, 1080p50, 1080p60
690 32, 19, 4, 0, 0, 0, 96, 97, 0, 99, 100, 101, 102,
691 };
692
693 MS_U8 HDMITX_VendorName[8] =
694 {
695 "MStar "
696 };
697
698 MS_U8 HDMITX_ProductName[16] =
699 {
700 "HDMI Tx Demo",
701 };
702
703 MS_U8 _gHPDGpioPin = 0;
704
705 //-------------------------------------------------------------------------------------------------
706 // Debug Functions
707 //-------------------------------------------------------------------------------------------------
708
709 #ifdef MS_DEBUG
710 #define DBG_HDMITX(_f) (_f)
711 #else
712 #define DBG_HDMITX(_f)
713 #endif
714
715 //-------------------------------------------------------------------------------------------------
716 // Local Functions
717 //-------------------------------------------------------------------------------------------------
718
719
720 //-------------------------------------------------------------------------------------------------
721 // Global Functions
722 //-------------------------------------------------------------------------------------------------
723 /*********************************************************************/
724 /* */
725 /* HDCP22 Relative */
726 /* */
727 /*********************************************************************/
MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)728 void MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)
729 {
730 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x11, bEnable ? 0x11 : 0x00); // bit 0: enable hdcp22; bit 4: enable EESS
731 if (bEnable)
732 {
733 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x02); //reset hdcp22 FSM
734 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x00);
735 }
736 }
737
MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)738 void MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)
739 {
740 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x04, bEnable ? 0x04 : 0x00); //bit 2: authentication pass
741 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x08, bEnable ? 0x08 : 0x00); //bit 3: enable hdcp22 to issue encryption enable signal
742 }
743
MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 * pu8Riv,MS_U8 * pu8KsXORLC128)744 void MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 *pu8Riv, MS_U8 *pu8KsXORLC128)
745 {
746 #define DEF_HDCP2CIPHER_DBG 0
747 #define SIZE_OF_KSXORLC128 16
748 #define SIZE_OF_RIV 8
749
750 MS_U8 cnt = 0;
751
752 #if (DEF_HDCP2CIPHER_DBG == 1)
753 printf("Ks^LC128:\r\n");
754 for ( cnt = 0; cnt < SIZE_OF_KSXORLC128; cnt++ )
755 {
756 printf("0x%02X ", *(pu8KsXORLC128 + cnt));
757 }
758 printf("\r\n");
759
760 printf("Riv:\r\n");
761 for ( cnt = 0; cnt < SIZE_OF_RIV; cnt++ )
762 {
763 printf("0x%02X ", *(pu8Riv + cnt));
764 }
765 printf("\r\n");
766 #endif
767
768 #undef DEF_HDCP2CIPHER_DBG
769 //MHal_HDMITx_Mask_Write(0x172F00, 0x01, 0x0020, 0x0020); //reverse order of cihper key
770 //MHal_HDMITx_Mask_Write(0x172B00, 0x01, 0x8000, 0x0000); //disable hdcp 1.4 module
771
772 for ( cnt = 0; cnt < (SIZE_OF_KSXORLC128>>1); cnt++)
773 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x60 + (SIZE_OF_KSXORLC128 >> 1) - 1 - cnt, *(pu8KsXORLC128 + cnt*2 + 1)|(*(pu8KsXORLC128 + cnt*2)<<8));
774
775 for ( cnt = 0; cnt < (SIZE_OF_RIV>>1); cnt++)
776 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x68 + (SIZE_OF_RIV >> 1) - 1 - cnt, *(pu8Riv + cnt*2 + 1)|(*(pu8Riv + cnt*2)<<8));
777 }
778
MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)779 void MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)
780 {
781 gu8ChipVerNum = u8ChipVer;
782 }
783
784 // HPD: GPIO_PM[11] -> external interrupt[11], register 0x000E00[14]
785 // DVI disconnet: must power down clock termination resistor: TM_REG[0] = 1, TM_REG[16:15] = 00, TM_REG[35:34] = 00.
786 // Interrupt helper functoins
787 //------------------------------------------------------------------------------
788 /// @brief Disable interrupt
789 /// @param[in] u32Int interrupter value
790 /// @return None
791 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Disable(MS_U32 u32Int)792 void MHal_HDMITx_Int_Disable(MS_U32 u32Int)
793 {
794 //MS_U16 u16reg_val = 0;
795
796 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int);
797 // [9]: mask FIQ, [8]: mask IRQ
798 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) );
799
800 #if 0 // K1 HPD pin doesn't have interrupt function
801 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
802 {
803 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
804 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank
805 {
806 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask
807 }
808 }
809 #endif
810 }
811
812 //------------------------------------------------------------------------------
813 /// @brief Enable interrupt
814 /// @param[in] u32Int interrupter value
815 /// @return None
816 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Enable(MS_U32 u32Int)817 void MHal_HDMITx_Int_Enable(MS_U32 u32Int)
818 {
819 //MS_U16 u16reg_val = 0;
820
821 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int);
822 // [9]: mask FIQ, [8]: unmask IRQ
823 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 );
824
825 #if 0 // K1 HPD pin doesn't have interrupt function
826 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
827 {
828 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
829 if(u32Int & E_HDMITX_IRQ_12)
830 {
831 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_PM output disable
832 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask
833 }
834 }
835 #endif
836 }
837
838 //------------------------------------------------------------------------------
839 /// @brief MHal_HDMITx_Int_Clear
840 /// @param[in] u32Int interrupter value
841 /// @return None
842 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Clear(MS_U32 u32Int)843 void MHal_HDMITx_Int_Clear(MS_U32 u32Int)
844 {
845 //MS_U16 u16reg_val = 0;
846
847 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int);
848 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16));
849
850 #if 0 // K1 HPD pin doesn't have interrupt function
851 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
852 {
853 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
854 if(u32Int & E_HDMITX_IRQ_12)
855 {
856 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val);
857 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0);
858 }
859 }
860 #endif
861 }
862
863 //------------------------------------------------------------------------------
864 /// @brief MHal_HDMITx_Int_Status
865 /// @param[in] u32Int interrupter value
866 /// @return None
867 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Status(void)868 MS_U32 MHal_HDMITx_Int_Status(void)
869 {
870 //MS_U16 u16reg_val = 0;
871 MS_U32 reg_value=0;
872
873 reg_value |= MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E);
874 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16);
875
876 #if 0 // K1 HPD pin doesn't have interrupt function
877 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4
878 {
879 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
880 reg_value = ((MHal_HDMITxPM_Read(PMBK_PMSLEEP_REG_BASE, 0x0A) & u16reg_val) ? (reg_value|E_HDMITX_IRQ_12):(reg_value&(~E_HDMITX_IRQ_12)));
881 }
882 #endif
883 return reg_value;
884 }
885
886
887 //------------------------------------------------------------------------------
888 /// @brief This routine is to get HDMI receiver DVI clock and HPD status.
889 /// @return MsHDMITX_RX_STATUS
890 //------------------------------------------------------------------------------
MHal_HDMITx_GetRXStatus(void)891 MsHDMITX_RX_STATUS MHal_HDMITx_GetRXStatus(void)
892 {
893 MS_BOOL dviclock_s, hpd_s = FALSE;
894 MsHDMITX_RX_STATUS state;
895
896 dviclock_s = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F) & BIT0 ? FALSE : TRUE;
897
898 hpd_s = mdrv_gpio_get_level(_gHPDGpioPin);
899
900 if((dviclock_s == FALSE) && (hpd_s == FALSE))
901 state = E_HDMITX_DVIClock_L_HPD_L;
902 else if((dviclock_s == FALSE) && (hpd_s == TRUE))
903 state = E_HDMITX_DVIClock_L_HPD_H;
904 else if((dviclock_s == TRUE) && (hpd_s == FALSE))
905 state = E_HDMITX_DVIClock_H_HPD_L;
906 else
907 state = E_HDMITX_DVIClock_H_HPD_H;
908
909 return state;
910 }
911
912
913 //------------------------------------------------------------------------------
914 /// @brief MHal_HDMITX_SetHDCPConfig
915 /// @param[in] u32Int HDCP mode
916 /// @return None
917 //------------------------------------------------------------------------------
MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)918 void MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)
919 {
920 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8);
921 }
922
923
924 //------------------------------------------------------------------------------
925 /// @brief MHal_HDMITX_GetM02Bytes
926 /// @param[in] u16Int index
927 /// @return M0 2 bytes
928 //------------------------------------------------------------------------------
MHal_HDMITX_GetM02Bytes(MS_U16 idx)929 MS_U16 MHal_HDMITX_GetM02Bytes(MS_U16 idx)
930 {
931 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx));
932 }
933
934
935 //------------------------------------------------------------------------------
936 /// @brief MHal_HDMITx_InitSeq
937 /// @param[in] None
938 /// @return None
939 //------------------------------------------------------------------------------
MHal_HDMITx_InitSeq(void)940 void MHal_HDMITx_InitSeq(void)
941 {
942 MHal_HDMITx_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, 0); // enable clk_hdmi_tx_p
943 MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x0010, 0x0010); //ODCLK source from HDMITx, MST253B Only
944
945 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_40, 0x0001, 0x0001);//MST253B Only
946 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3D, 0x0400, 0x0400);//MST253B Only
947 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_01, 0x0001, 0x0001);//MST253B Only
948 //MHal_HDMITx_Mask_Write(0x000E00U, 0x72U, 0x1000, 0x1000);//MST253B Only msdbg for HPD
949 //MHal_HDMITx_Mask_Write(0x101E00U, 0x6EU, 0x0004, 0x0004);//MST253B Only msdbg for DDC
950
951 //set at mboot
952 //MHal_HDMITx_Mask_Write(0x101E00, 0x0B, BIT12, BIT12); //enable hdmitx DDC
953
954 //MAC setting
955 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1C, 0x0000);
956 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1D, 0x0000);
957 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1E, 0xFFFF);
958 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1F, 0x0000);
959
960 //sw reset modules
961 if(MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E) & 0xE800)
962 {
963 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
964 }
965 else
966 {
967 //disable power down
968 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
969 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
970 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
971 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0017);
972 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0000);
973 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x001F);
974 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x0000);
975 }
976
977 //MHal_HDMITx_Write(HDMITX_REG_BASE, REG_HPLL_LOCK_CNT_53, 0x0300); // HPLL lock counter
978
979 //enable PHY setting
980 //[0]:enable synth clock; [4]:enable synth clock to a top; [8]:enable tmds clock; [12]: enable atop 40 bit clock
981 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101, 0x1101);
982 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
983 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00);
984
985 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F, 0x0010, 0x0010); //reg_atop_nodie_en_disc
986
987 //disable power down
988 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
989 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, 0x0000);
990
991 //rterm set by Mboot according to data of EFUSE, rterm 50 Ohm
992 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x01F0, 0x0000);
993
994 //txpll input div 1
995 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x03F3, 0x0051);
996
997 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3D, 0x030F, 0x0003); //REG_TXPLL_SEL_CLKIN, REG_TXPLL_ICP_ICTRL
998 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0003); //REG_ICTRL_PREDRV_MAIN_CLK
999 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0000); //REG_ICTRL_PREDRV_MAIN_CLK
1000 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x003F, 0x0010); //REG_ICTRL_DRV_MAIN_CLK
1001
1002 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_32, 0x3F3F, 0x0000);
1003 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_36, 0x3F3F, 0x0000);
1004 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_37, 0x3F3F, 0x0000);
1005
1006 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
1007
1008 //lane fifo setting
1009 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x0007, 0x0004);
1010 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x0007, 0x0005);
1011 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x0007, 0x0006);
1012 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x0007, 0x0007);
1013
1014 //timing field regen enable (due to scaler can't guarantee field signal and even/odd frame is asynchronize)
1015 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x0010, 0x0010);
1016
1017 //for U02: QD980 CTS compatibility issue
1018 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x8000, 0x8000);
1019
1020 }
1021
1022 //------------------------------------------------------------------------------
1023 /// @brief This routine is the initialization for Video module.
1024 /// @return None
1025 //------------------------------------------------------------------------------
MHal_HDMITx_VideoInit(void)1026 void MHal_HDMITx_VideoInit(void)
1027 {
1028 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, BIT4, BIT4); //enable video engine fifo r/w pointer
1029 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_12, 0x000F, BIT3); // [3]: manual mode of pixel-repetition enable
1030 }
1031
1032 //------------------------------------------------------------------------------
1033 /// @brief This routine is the initialization for Audio module.
1034 /// @return None
1035 //------------------------------------------------------------------------------
MHal_HDMITx_AudioInit(void)1036 void MHal_HDMITx_AudioInit(void)
1037 {
1038 int num;
1039
1040 num = sizeof(HDMITxAudioInitTbl) / sizeof(MSTHDMITX_REG_TYPE);
1041 MHal_HDMITx_RegsTbl_Write(HDMITxAudioInitTbl, num);
1042 }
1043
1044
1045 //------------------------------------------------------------------------------
1046 /// @brief This routine turn on/off HDMI PLL
1047 /// @return None
1048 //------------------------------------------------------------------------------
MHal_HDMITx_PLLOnOff(MS_BOOL bflag)1049 void MHal_HDMITx_PLLOnOff(MS_BOOL bflag)
1050 {
1051 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, bflag ? 0x0000 : 0x0010);
1052 }
1053
1054
MHal_HDMITx_PKT_User_Define_Clear(void)1055 void MHal_HDMITx_PKT_User_Define_Clear(void)
1056 {
1057 MS_U8 i = 0;
1058
1059 for ( i = 0; i < GENERAL_PKT_NUM; i++ )
1060 {
1061 gbGeneralPktList[i].EnableUserDef = FALSE;
1062 gbGeneralPktList[i].FrmCntNum = 0x00;
1063 gbGeneralPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
1064 memset(&gbGeneralPktList[i].PktPara, 0x00, sizeof(gbGeneralPktList[i].PktPara));
1065 }
1066
1067 for ( i = 0; i < INFOFRM_PKT_NUM; i++ )
1068 {
1069 gbInfoFrmPktList[i].EnableUserDef = FALSE;
1070 gbInfoFrmPktList[i].FrmCntNum = 0x00;
1071 gbInfoFrmPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
1072 memset(&gbInfoFrmPktList[i].PktPara, 0x00, sizeof(gbInfoFrmPktList[i].PktPara));
1073 }
1074 }
1075
MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type,MS_BOOL def_flag,MsHDMITX_PACKET_PROCESS def_process,MS_U8 def_fcnt)1076 void MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type, MS_BOOL def_flag,
1077 MsHDMITX_PACKET_PROCESS def_process, MS_U8 def_fcnt)
1078 {
1079 if (packet_type & 0x80) //infoframe packet type
1080 {
1081 gbInfoFrmPktList[packet_type & (~0x80)].EnableUserDef = def_flag;
1082 gbInfoFrmPktList[packet_type & (~0x80)].FrmCntNum = def_fcnt;
1083 gbInfoFrmPktList[packet_type & (~0x80)].enPktCtrl = def_process;
1084 }
1085 else
1086 {
1087 gbGeneralPktList[packet_type].EnableUserDef = def_flag;
1088 gbGeneralPktList[packet_type].FrmCntNum = def_fcnt;
1089 gbGeneralPktList[packet_type].enPktCtrl = def_process;
1090 }
1091 }
1092
MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type,MS_U8 * data,MS_U8 length)1093 MS_BOOL MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type, MS_U8* data, MS_U8 length)
1094 {
1095 MS_BOOL bRet = TRUE;
1096 MS_U8 i, j, *ptr;
1097 ptr = data;
1098
1099 switch(packet_type)
1100 {
1101 case E_HDMITX_VS_INFOFRAME:
1102 for (i=0; i < length; i++)
1103 {
1104 j = i>>1;
1105
1106 if ((REG_PKT_VS_1_27+j > REG_PKT_VS_14_34) || ((REG_PKT_VS_1_27+j == REG_PKT_VS_14_34) && (i % 2 == 1)))
1107 {
1108 //Packet over size, last VS packet PB register is REG_PKT_VS_14_34[7:0]
1109 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
1110 break;
1111 }
1112
1113 if((i%2)==0)
1114 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0x00FF, *(ptr+i));
1115 else
1116 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0xFF00, (*(ptr+i))<<8);
1117 }
1118 break;
1119 case E_HDMITX_SPD_INFOFRAME:
1120 for(i=0;i<length;i++)
1121 {
1122 j = i>>1;
1123
1124 if((REG_PKT_SPD_1_15+j > REG_PKT_SPD_13_21) || ((REG_PKT_SPD_1_15+j == REG_PKT_SPD_13_21) && (i % 2 == 1)))
1125 {
1126 //Packet over size, last SPD packet PB register is REG_PKT_SPD_13_21[7:0]
1127 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
1128 break;
1129 }
1130
1131 if((i%2)==0)
1132 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0x00FF, *(ptr+i));
1133 else
1134 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0xFF00, (*(ptr+i))<<8);
1135 }
1136 break;
1137
1138 case E_HDMITX_AVI_INFOFRAME:
1139 for ( i = 0; i < length; i++ )
1140 {
1141 j = i >> 1;
1142
1143 if (((REG_PKT_AVI_1_09 + j) > REG_PKT_AVI_7_0F) || (((REG_PKT_AVI_1_09 + j) == REG_PKT_AVI_7_0F) && (i % 2 == 1)))
1144 {
1145 DBG_HDMITX(printf("AVI packet over size, length = %d \n", length));
1146 break;
1147 }
1148
1149 if ((i % 2) == 0)
1150 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + j, 0x00FF, *(ptr+i));
1151 else
1152 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + j, 0xFF00, *(ptr+i) << 8);
1153 }
1154 break;
1155
1156 //wilson@kano HDR packet
1157 case E_HDMITX_HDR_INFOFRAME:
1158 //first 3 bytes will follow spec, (1) type code (2) version (3) length, and reamins will be content
1159 length = (length > (HDMITX_HDR_INFO_PKT_LEN + 3)) ? (HDMITX_HDR_INFO_PKT_LEN + 3) : length;
1160 //fill length and version
1161 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F,(*(ptr+2) << 8) | *(ptr+1));
1162
1163 if (length >= 3)
1164 {
1165 for ( i = 0; i < (length-3); i++ )
1166 {
1167 j = i >> 1;
1168
1169 if ( ((REG_HDMI_2_CONFIG_10 + j) > REG_HDMI_2_CONFIG_1D) || (((REG_HDMI_2_CONFIG_10 + j) == REG_HDMI_2_CONFIG_1D) && (i % 2 == 1)) )
1170 {
1171 DBG_HDMITX(printf("HDR packet over size, length = %d \n", length));
1172 break;
1173 }
1174
1175 if ((i % 2) == 0)
1176 {
1177 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0x00FF, *(ptr+i+3));
1178 }
1179 else
1180 {
1181 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0xFF00, (*(ptr+i+3))<<8);
1182 }
1183 }
1184 }
1185 break;
1186
1187 case E_HDMITX_AUDIO_INFOFRAME:
1188 {
1189 //total length should be 192 bits *2 = 384 bits = 48 bytes;
1190
1191 length = (length < ((192>>3)<<1) ) ? length : ((192>>3)<<1);
1192
1193 for ( i = 0; i < length; i++ )
1194 {
1195 j = i >> 1;
1196
1197 if ((i % 2) == 0)
1198 {
1199 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0x00FF, *(ptr+i));
1200 }
1201 else
1202 {
1203 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0xFF00, (*(ptr+i) << 8));
1204 }
1205 }
1206 }
1207 break;
1208
1209 default:
1210 i = 0;
1211 j = 0;
1212 bRet = FALSE;
1213 DBG_HDMITX(printf("Not implemented, packet type = %u\n", packet_type));
1214 break;
1215 }
1216
1217 return bRet;
1218 }
1219
1220 //------------------------------------------------------------------------------
1221 /// @brief This routine turn on/off HDMI Tx TMDS signal
1222 /// @param[in] bRB_Swap: R/B swap; bTMDS: TMDS flag
1223 /// @return None
1224 //------------------------------------------------------------------------------
MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap,MS_BOOL bTMDS)1225 void MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap, MS_BOOL bTMDS)
1226 {
1227 if(bRB_Swap) // R/B channel swap
1228 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, BIT13);
1229 else
1230 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, 0);
1231
1232 //reg_atop_en_data_out[13..15]: Enable data channel data output
1233 if (bTMDS == TRUE)
1234 {
1235 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
1236 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0xE800);
1237 //TBD: turn off tmds clock
1238
1239 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo
1240 MsOS_DelayTask(10);
1241 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000);
1242 }
1243 else
1244 {
1245 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
1246 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0x0000);
1247 //TBD: turn off tmds clock
1248 }
1249 }
1250
1251 //------------------------------------------------------------------------------
1252 /// @brief This routine turn on/off HDMI Tx video output
1253 /// @param[in] bVideo: Video flag; bCSC: CSC flag, b709format = BT.709-5
1254 /// @return None
1255 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo,MS_BOOL bCSC,MS_BOOL b709format)1256 void MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo, MS_BOOL bCSC, MS_BOOL b709format)
1257 {
1258 if (bVideo == TRUE)
1259 {
1260 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0, 0x0000); // disable test pattern
1261 }
1262 else
1263 {
1264 MS_U8 i = 0x00;
1265
1266 DBG_HDMITX(printf("MDrv_HDMITx_SetVideoOnOff: csc flag= %d \n", bCSC));
1267
1268 // enable test pattern
1269 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3A, 0x0000);
1270 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3B, 0x0000);
1271 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3C, 0x03FF); // whole-blue
1272 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0|BIT1, BIT0|BIT1);
1273
1274 for ( i = 0; i < 6; i++ )
1275 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3D + i, 0x0000);
1276 }
1277 }
1278
1279 //------------------------------------------------------------------------------
1280 /// @brief This routine sets video color formatt
1281 /// @param[in] bCSC: CSC flag, YUV422 12 bit, b709format = BT.709-5
1282 /// @return None
1283 //------------------------------------------------------------------------------
MHal_HDMITx_SetColorFormat(MS_BOOL bCSC,MS_BOOL bHdmi422b12,MS_BOOL b709format)1284 void MHal_HDMITx_SetColorFormat(MS_BOOL bCSC, MS_BOOL bHdmi422b12, MS_BOOL b709format)
1285 {
1286 if (bCSC) // YUV -> RGB
1287 {
1288 DBG_HDMITX(printf("YUV -> RGB \n"));
1289 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, BIT0); //bypass
1290 }
1291 else // bypass
1292 {
1293 DBG_HDMITX(printf("bypass YUV -> RGB \n"));
1294 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, 0x00); //bypass
1295 }
1296
1297 // YUV422 12 bits output
1298 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, bHdmi422b12 ? BIT15 : 0x00);
1299 }
1300
1301 //------------------------------------------------------------------------------
1302 /// @brief This routine get CSC capability
1303 /// @param[in]
1304 /// @return False : not support R2Y. Ture : ok.
1305 //------------------------------------------------------------------------------
MHal_HDMITx_CSC_Support_R2Y(void * pDatatIn)1306 MS_BOOL MHal_HDMITx_CSC_Support_R2Y(void* pDatatIn)
1307 {
1308 pDatatIn = pDatatIn;
1309 return HDMITX_CSC_SUPPORT_R2Y;
1310 }
1311
1312 //------------------------------------------------------------------------------
1313 /// @brief This routine sets color domain and color range transform
1314 /// @param[in]
1315 /// @return False : not support this command. Ture : ok.
1316 //------------------------------------------------------------------------------
MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor,MsHDMITX_VIDEO_COLOR_FORMAT outcolor,MsHDMITX_YCC_QUANT_RANGE inrange,MsHDMITX_YCC_QUANT_RANGE outrange)1317 MS_BOOL MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor, MsHDMITX_VIDEO_COLOR_FORMAT outcolor, MsHDMITX_YCC_QUANT_RANGE inrange, MsHDMITX_YCC_QUANT_RANGE outrange)
1318 {
1319 MS_BOOL bReturn = FALSE;
1320
1321 if(incolor == E_HDMITX_VIDEO_COLOR_RGB444)
1322 {
1323 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LR
1324 {
1325 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1326 { //LR -> LY
1327 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1328 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x020C);
1329 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E24);
1330 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD0);
1331 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1332 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1333 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1334 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F88);
1335 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E6C);
1336 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x020C);
1337 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1338 bReturn = TRUE;
1339 DBG_HDMITX(printf("LR->LY! \n"));
1340 }
1341 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1342 { //LR -> FY
1343 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0CB0);
1344 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0256);
1345 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1DE1);
1346 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FC9);
1347 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00FE);
1348 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0357);
1349 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0056);
1350 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F77);
1351 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E33);
1352 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0256);
1353 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1354 bReturn = TRUE;
1355 DBG_HDMITX(printf("LR->FY! \n"));
1356 }
1357 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_FULL))
1358 { //LR -> FR
1359 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0C10);
1360 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1361 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1362 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1363 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1364 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1365 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1366 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1367 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1368 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1369 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1370 bReturn = TRUE;
1371 DBG_HDMITX(printf("LR->FR! \n"));
1372 }
1373 else
1374 {
1375 DBG_HDMITX(printf("LR->LR! \n"));
1376 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1377 DBG_HDMITX(printf("In/Out Same Color! \n"));
1378 bReturn = TRUE;
1379 }
1380
1381 }
1382 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FR
1383 {
1384 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1385 { //FR -> LY
1386 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00E0);
1387 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x01C0);
1388 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E69);
1389 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD7);
1390 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00BA);
1391 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0273);
1392 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x003F);
1393 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F99);
1394 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1EA6);
1395 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x01C0);
1396 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1397 bReturn = TRUE;
1398 DBG_HDMITX(printf("FR->LY! \n"));
1399 }
1400 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1401 { //FR -> FY
1402 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A1);
1403 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1404 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0200);
1405 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E2F);
1406 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD1);
1407 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1408 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1409 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1410 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F8B);
1411 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E75);
1412 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0200);
1413 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1414 bReturn = TRUE;
1415 DBG_HDMITX(printf("FR->FY! \n"));
1416 }
1417 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1418 { //FR -> LR
1419 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x5040);
1420 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0381);
1421 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1422 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1423 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1424 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1425 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1426 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1427 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1428 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0381);
1429 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1430 bReturn = TRUE;
1431 DBG_HDMITX(printf("FR->LR! \n"));
1432 }
1433 else
1434 {
1435 DBG_HDMITX(printf("FR->FR! \n"));
1436 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1437 DBG_HDMITX(printf("In/Out Same Color! \n"));
1438 bReturn = TRUE;
1439 }
1440 }
1441 else
1442 {
1443 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1444 DBG_HDMITX(printf("Not Support This! \n"));
1445 }
1446 }
1447 else if((incolor == E_HDMITX_VIDEO_COLOR_YUV444) || (incolor == E_HDMITX_VIDEO_COLOR_YUV422))
1448 {
1449 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LY
1450 {
1451 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1452 {//LY->FR
1453 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x001A);
1454 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0731);
1455 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x04AC);
1456 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1457 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1DDD);
1458 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1459 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F25);
1460 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1461 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x04AC);
1462 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0879);
1463 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1464 bReturn = TRUE;
1465 DBG_HDMITX(printf("LY->FR! \n"));
1466 }
1467 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1468 {//LY->LR
1469 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1470 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0629);
1471 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1472 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1473 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E2B);
1474 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1475 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F44);
1476 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1477 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1478 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0742);
1479 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1480 bReturn = TRUE;
1481 DBG_HDMITX(printf("May over range! \n"));
1482 DBG_HDMITX(printf("LY->LR! \n"));
1483 }
1484 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1485 {//LY->FY
1486 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00BA);
1487 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0491);
1488 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1489 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1490 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1491 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1492 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1493 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1494 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1495 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0491);
1496 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1497 bReturn = TRUE;
1498 DBG_HDMITX(printf("LY->FY! \n"));
1499 }
1500 else
1501 {
1502 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1503 DBG_HDMITX(printf("In/Out Same Color! \n"));
1504 DBG_HDMITX(printf("LY->LY! \n"));
1505 bReturn = TRUE;
1506 }
1507
1508 }
1509 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FY
1510 {
1511 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1512 {//FY->FR
1513 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1514 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x064D);
1515 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1516 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1517 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E21);
1518 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1519 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F40);
1520 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1521 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1522 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x076C);
1523 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1524 bReturn = TRUE;
1525 DBG_HDMITX(printf("FY->FR! \n"));
1526 }
1527 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1528 {//FY->LR
1529 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x504A);
1530 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0565);
1531 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x036D);
1532 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1533 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E66);
1534 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1535 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F5C);
1536 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1537 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x036D);
1538 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x065B);
1539 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1540 bReturn = TRUE;
1541 DBG_HDMITX(printf("FY->LR! \n"));
1542 }
1543 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1544 {//FY->LY
1545 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00EA);
1546 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1547 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1548 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1549 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1550 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1551 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1552 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1553 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1554 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1555 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1556 bReturn = TRUE;
1557 DBG_HDMITX(printf("FY->LY! \n"));
1558 }
1559 else
1560 {
1561 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1562 DBG_HDMITX(printf("In/Out Same Color! \n"));
1563 DBG_HDMITX(printf("FY->FY! \n"));
1564 bReturn = TRUE;
1565 }
1566 }
1567 else
1568 {
1569 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1570 DBG_HDMITX(printf("Not Support This! \n"));
1571 }
1572 }
1573 else
1574 {
1575 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1576 DBG_HDMITX(printf("Not Support This! \n"));
1577 }
1578
1579 //if(bReturn == TRUE)
1580 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, (outcolor == E_HDMITX_VIDEO_COLOR_YUV422) ? BIT15 : 0);
1581
1582 return bReturn;
1583 }
1584
1585 //------------------------------------------------------------------------------
1586 /// @brief This routine will set or stop all HDMI packet generation
1587 /// @param[in] bflag True: Enable packet gen, False : Disable packet gen
1588 /// @return None
1589 //------------------------------------------------------------------------------
MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)1590 void MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)
1591 {
1592 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT2, bflag ? BIT2:0);
1593 }
1594
1595 //------------------------------------------------------------------------------
1596 /// @brief This routine sets HDMI/DVI mode
1597 /// @param[in] bflag
1598 /// @return None
1599 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDMImode(MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)1600 void MHal_HDMITx_SetHDMImode(MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)
1601 {
1602 MS_U8 ucRegVal = 0x00;
1603
1604 DBG_HDMITX(printf("[%s][%d]HDMI mode = %d, Color Depth = %d \n", __FUNCTION__, __LINE__, bflag, bflag));
1605
1606 if (bflag) // HDMI mode
1607 {
1608 switch(cd_val)
1609 {
1610 case E_HDMITX_VIDEO_CD_NoID:
1611 case E_HDMITX_VIDEO_CD_24Bits:
1612 default:
1613 ucRegVal = 0x00;
1614 break;
1615
1616 case E_HDMITX_VIDEO_CD_30Bits:
1617 ucRegVal = 0x40;
1618 break;
1619
1620 case E_HDMITX_VIDEO_CD_36Bits:
1621 ucRegVal = 0x80;
1622 break;
1623
1624 case E_HDMITX_VIDEO_CD_48Bits:
1625 ucRegVal = 0xC0;
1626 break;
1627 }
1628
1629 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, ucRegVal|BIT2); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1630 }
1631 else // DVI
1632 {
1633 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, BIT0); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1634 }
1635 }
1636
1637
1638 //------------------------------------------------------------------------------
1639 /// @brief This routine sets audio on/off
1640 /// @param[in] bflag
1641 /// @return None
1642 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)1643 void MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)
1644 {
1645 MS_U8 num;
1646
1647 if(bflag) // audio on
1648 {
1649 num = sizeof(HDMITxAudioOnTbl)/sizeof(MSTHDMITX_REG_TYPE);
1650 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOnTbl, num);
1651 }
1652 else // audio off
1653 {
1654 num = sizeof(HDMITxAudioOffTbl)/sizeof(MSTHDMITX_REG_TYPE);
1655 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOffTbl, num);
1656 }
1657 }
1658
1659 //------------------------------------------------------------------------------
1660 /// @brief This routine sets audio sampling freq.
1661 /// @return None
1662 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,MsHDMITX_AUDIO_CHANNEL_COUNT achidx,MsHDMITX_AUDIO_CODING_TYPE actidx)1663 void MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,
1664 MsHDMITX_AUDIO_CHANNEL_COUNT achidx, MsHDMITX_AUDIO_CODING_TYPE actidx
1665 )
1666 {
1667 // HDMI audio channel setting
1668 if(achidx == E_HDMITX_AUDIO_CH_2) // 2 channels
1669 {
1670 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5]: audio FIFO depth ch1234, [4]=1'b0: 2 channels
1671 }
1672 else // 8 channels
1673 {
1674 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels
1675 }
1676
1677 // Audio channel status
1678 #if 1 //NOTE:: kano: move channel status from address 0x00 to address 0x0A
1679 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1680 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[afidx].CH_Status3 << 8) | (achidx << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
1681 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
1682 #else
1683 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_00, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1684 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_01, 0);
1685 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_02, (achidx<<4)); // [7:4]: audio channel count
1686 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS3_03, TxAudioFreqTbl[afidx].CH_Status3); // [3:0]: audio sampling frequncy
1687 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS4_04, 0);
1688 #endif
1689 // ACR N code
1690 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_2_06, 0x0F00, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000));
1691 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_3_07, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1692
1693 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_61, 0x000F, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000) >> 8);
1694 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_60, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1695 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x0100, 0x0100); //enable cts * 2
1696 }
1697
1698 //------------------------------------------------------------------------------
1699 /// @brief This routine sets audio source format.
1700 /// @return None
1701 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)1702 void MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)
1703 {
1704 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8);
1705 }
1706
1707 //------------------------------------------------------------------------------
1708 /// @brief This routine Get Audio CTS value
1709 /// @return CTS
1710 //------------------------------------------------------------------------------
MHal_HDMITx_GetAudioCTS(void)1711 MS_U32 MHal_HDMITx_GetAudioCTS(void)
1712 {
1713 MS_U32 ret;
1714
1715 ret = ((MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_2_06) & 0x000F) << 16) | MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_1_05);
1716 return ret;
1717 }
1718
1719 //------------------------------------------------------------------------------
1720 /// @brief This routine Mute Audio FIFO
1721 /// @param[in] bflag: True: mute audio, False: unmute audio
1722 /// @return None
1723 //------------------------------------------------------------------------------
MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)1724 void MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)
1725 {
1726 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag);
1727 }
1728
1729 //------------------------------------------------------------------------------
1730 /// @brief This routine sets HDMI Tx HDCP encryption On/Off
1731 /// @return None
1732 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag,MS_BOOL hdmi_flag)1733 void MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag, MS_BOOL hdmi_flag)
1734 {
1735 if(hdcp_flag) // HDCP on
1736 {
1737 if (hdmi_flag) // HDMI EESS
1738 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400);
1739 else // DVI OESS
1740 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000);
1741 // HDCP encryption
1742 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008);
1743 }
1744 else // HDCP off
1745 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000);
1746 }
1747
1748 //------------------------------------------------------------------------------
1749 /// @brief This routine calculate check sum of infoframes.
1750 /// @param[in] packet_type packet type
1751 /// @return checksum
1752 //------------------------------------------------------------------------------
MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)1753 MS_U8 MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)
1754 {
1755 MS_U8 ucSumVal = 0;
1756 MS_U8 i = 0;
1757 MS_U8 j = 0;
1758 MS_U16 wRegVal = 0;
1759
1760 switch (packet_type)
1761 {
1762 case E_HDMITX_VS_INFOFRAME:
1763 ucSumVal += (E_HDMITX_VS_INFOFRAME + HDMITX_VS_INFO_PKT_VER + HDMITX_VS_INFO_PKT_LEN);
1764
1765 for ( i = 0; i < (HDMITX_VS_INFO_PKT_LEN + 1) >> 1; i++ )
1766 {
1767 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_VS_1_27 + i);
1768
1769 for ( j = 0; j < 2; j++ )
1770 {
1771 if ((i == 13) && (j==1))
1772 {
1773 ucSumVal += 0x00;
1774 }
1775 else
1776 {
1777 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1778 }
1779 }
1780 }
1781 break;
1782
1783 case E_HDMITX_AVI_INFOFRAME:
1784 ucSumVal += (E_HDMITX_AVI_INFOFRAME + HDMITX_AVI_INFO_PKT_VER + HDMITX_AVI_INFO_PKT_LEN);
1785
1786 for ( i = 0; i < ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1); i++ )
1787 {
1788 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + i);
1789
1790 for ( j = 0; j < 2; j++ )
1791 {
1792 if ((i == 1) && (j == 0)) // SC[1:0]
1793 {
1794 ucSumVal += (HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)(wRegVal & 0x00FF) & 0x03);
1795 }
1796 else if ((i == 1) && (j == 1)) // VIC[6:0]
1797 {
1798 ucSumVal += ((HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)((wRegVal & 0xFF00) >> 8) & 0x7F) : 0x00);
1799 }
1800 else if ((i == 2) && (j == 0)) // PR[3:0]
1801 {
1802 ucSumVal += (MS_U8)(wRegVal & 0x00FF); //bit 4:7 used for HDR; //ucSumVal += ((MS_U8)(wRegVal & 0x00FF) & 0x0F);
1803 }
1804 #if 0 //not resevered byte anymore; should be counted
1805 else if ((i == 2) && (j == 1)) // reserved
1806 {
1807 ucSumVal += 0x00;
1808 }
1809 #endif
1810 else if (( i == ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1) - 1)&&(j == 1))
1811 {
1812 ucSumVal += 0x00;
1813 }
1814 else
1815 {
1816 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1817 }
1818 }
1819 }
1820 break;
1821
1822 case E_HDMITX_SPD_INFOFRAME:
1823 ucSumVal += (E_HDMITX_SPD_INFOFRAME + HDMITX_SPD_INFO_PKT_VER + HDMITX_SPD_INFO_PKT_LEN);
1824
1825 for ( i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN+ 1) >> 1); i++ )
1826 {
1827 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_SPD_1_15 + i);
1828
1829 for ( j = 0; j < 2; j++ )
1830 {
1831 if ((i == 12) && (j == 0))
1832 {
1833 ucSumVal += (MS_U8)(wRegVal & 0x00FF);
1834 }
1835 else if ((i == 12) && (j == 1)) //reserved
1836 {
1837 ucSumVal += 0x00;
1838 }
1839 else
1840 {
1841 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1842 }
1843 }
1844 }
1845 break;
1846
1847 case E_HDMITX_AUDIO_INFOFRAME:
1848 ucSumVal += (E_HDMITX_AUDIO_INFOFRAME + HDMITX_AUD_INFO_PKT_VER + HDMITX_AUD_INFO_PKT_LEN);
1849
1850 for ( i = 0; i < (((HDMITX_AUD_INFO_PKT_LEN >> 1) + 1) >> 1); i++ )
1851 {
1852 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AUD_1_11 + i);
1853
1854 if (i == 1)
1855 {
1856 for ( j = 0; j < 2; j++ )
1857 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1858 }
1859
1860 if (i == 0)
1861 {
1862 for ( j = 0; j < 2; j++ )
1863 ucSumVal += ( (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xF7) : (((MS_U8)(wRegVal & 0xFF00) >> 8) & 0x1F));
1864 }
1865
1866 if (i == 2)
1867 {
1868 for ( j = 0; j < 2; j++ )
1869 ucSumVal += ((j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xFB) : 0x00);
1870 }
1871 }
1872 break;
1873
1874 case E_HDMITX_MPEG_INFOFRAME:
1875 //TBD
1876 break;
1877
1878 case E_HDMITX_HDR_INFOFRAME:
1879 {
1880 MS_U8 u8PktLen = 0x00;
1881
1882 u8PktLen = (MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0xFF00) >> 8;
1883 ucSumVal += (E_HDMITX_HDR_INFOFRAME + (MS_U8)(MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0x00FF) + u8PktLen);
1884
1885 for ( i = 0; i < ((u8PktLen + 1) >> 1); i++ )
1886 {
1887 wRegVal = MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_10 + i);
1888
1889 for ( j = 0; j < 2; j++ )
1890 {
1891 if ((i == 0x0D) && (j % 2 == 0x00))
1892 ucSumVal += (j % 2 == 0) ? (MS_U8)(wRegVal & 0x00FF) : 0x00;
1893 else
1894 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1895 }
1896 }
1897 }
1898 break;
1899
1900 default:
1901 break;
1902 }
1903
1904 return (MS_U8)((~ucSumVal) + 0x01);
1905
1906 }
1907
1908 //------------------------------------------------------------------------------
1909 /// @brief This routine sets video output mode (color/repetition/regen)
1910 /// @param[in] idx: gHDMITxInfo.output_video_timing
1911 /// @return None
1912 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx,MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val,MsHDMITX_ANALOG_TUNING * pInfo,MS_U8 ubSSCEn)1913 void MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx, MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val, MsHDMITX_ANALOG_TUNING *pInfo, MS_U8 ubSSCEn)
1914 {
1915 //MS_U16 reg_value=0;
1916 MS_U8 ubTimingChanged = TRUE;
1917 MS_U8 ucCDIdx = 0;
1918 MS_U16 wHfront = 0;
1919 MS_U16 wVfront = 0;
1920 MS_BOOL bIsHDMI20 = FALSE;
1921 MS_BOOL bIs420Fmt = FALSE;
1922 MS_BOOL bIsRPMode = FALSE;
1923 MsHDMITX_VIDEO_TIMING eSize_idx = idx;
1924
1925 //wilson@kano:TBD
1926 printf("video idx = 0x%X, color depth = 0x%X\r\n", idx, cd_val);
1927 // Deep color FIFO reset
1928 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, BIT10);
1929 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, 0);
1930 MsOS_DelayTask(10);
1931
1932
1933
1934 ucCDIdx = (cd_val == 0)? 0x00 : (cd_val - 4);
1935
1936 // Interlace mode
1937 #if (defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
1938 if (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE)
1939 {
1940 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_2D, 0x0008, 0x0008);
1941 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x005F);
1942 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x4000); //reg_interlace_mode_sel
1943 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0004); // PG interlace enable
1944
1945 if(idx == E_HDMITX_RES_720x480i)
1946 {
1947 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2
1948 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
1949 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
1950 }
1951 else if(idx == E_HDMITX_RES_720x576i)
1952 {
1953 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2
1954 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
1955 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
1956 }
1957 else if(idx == E_HDMITX_RES_1920x1080i_50Hz)
1958 {
1959 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x01C0); //video,pixel,tmds clock div 2
1960 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0001); //PHY tmds clock div 2
1961 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
1962 }
1963 else if(idx == E_HDMITX_RES_1920x1080i_60Hz)
1964 {
1965 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x01C0); //video,pixel,tmds clock div 2
1966 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0001); //PHY tmds clock div 2
1967 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
1968 }
1969 }
1970 else
1971 {
1972 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_2D, 0x0008, 0x0008);
1973 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x004E);
1974 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x0000); //reg_interlace_mode_sel
1975 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0000); // PG interlace disable
1976
1977 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video clock div 2
1978 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
1979 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
1980 }
1981 #else
1982 if (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE)
1983 {
1984 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x005F);
1985 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x4000); //reg_interlace_mode_sel
1986 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2
1987 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0004); // PG interlace enable
1988 }
1989 else
1990 {
1991 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x004E);
1992 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x0000); //reg_interlace_mode_sel
1993 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0000); //video clock div 2
1994 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0000); // PG interlace disable
1995 }
1996 #endif
1997
1998 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt != E_HDMITX_VIDEO_COLOR_YUV420) &&
1999 ((idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || \
2000 (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz) || \
2001 ((idx > E_HDMITX_RES_1280x1470p_60Hz) && (cd_val > E_HDMITX_VIDEO_CD_24Bits))))
2002 bIsHDMI20 = TRUE;
2003
2004 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420) &&
2005 ((idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz)) &&
2006 (cd_val > E_HDMITX_VIDEO_CD_24Bits))
2007 bIsHDMI20 = TRUE;
2008
2009 //for 2.0
2010 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0100, bIsHDMI20 ? 0x0100 : 0x00);
2011 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_52, BIT0, bIsHDMI20 ? BIT0 : 0x00);
2012
2013 //scdc
2014 if (bIsHDMI20 == TRUE)
2015 Mhal_HDMITx_SCDCSetTmdsConfig(TRUE, TRUE);
2016 else
2017 Mhal_HDMITx_SCDCSetTmdsConfig(FALSE, FALSE);
2018
2019 #if (defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1))
2020 if (gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420)
2021 {
2022 if(cd_val > E_HDMITX_VIDEO_CD_24Bits)
2023 {
2024 switch (idx)
2025 {
2026 case E_HDMITX_RES_3840x2160p_50Hz:
2027 idx = E_HDMITX_RES_3840x2160p_25Hz;
2028 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video, pixel,tmds clock div 2 for 420
2029 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2030 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2031 break;
2032
2033 case E_HDMITX_RES_3840x2160p_60Hz:
2034 idx = E_HDMITX_RES_3840x2160p_30Hz;
2035 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video, pixel,tmds clock div 2 for 420
2036 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2037 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2038 break;
2039
2040 case E_HDMITX_RES_4096x2160p_50Hz:
2041 idx = E_HDMITX_RES_4096x2160p_25Hz;
2042 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video, pixel,tmds clock div 2 for 420
2043 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2044 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2045 break;
2046
2047 case E_HDMITX_RES_4096x2160p_60Hz:
2048 idx = E_HDMITX_RES_4096x2160p_30Hz;
2049 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video, pixel,tmds clock div 2 for 420
2050 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2051 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2052 break;
2053
2054 default:
2055 if( idx < E_HDMITX_RES_1920x1080p_50Hz)
2056 {
2057 printf("[HDMITX] Invalid Combination of Color Format & Video Timing, Keep Origional Timing Setting!!\r\n");
2058 }
2059 else
2060 {
2061 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x01C0); //video, pixel,tmds clock div 2 for 420
2062 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0001); //PHY tmds clock div 2
2063 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
2064 }
2065 break;
2066 }
2067 }
2068 else
2069 {
2070 if( idx < E_HDMITX_RES_1920x1080p_50Hz)
2071 {
2072 printf("[HDMITX] Invalid Combination of Color Format & Video Timing, Keep Origional Timing Setting!!\r\n");
2073 }
2074 else
2075 {
2076 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x01C0); //video, pixel,tmds clock div 2 for 420
2077 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0001); //PHY tmds clock div 2
2078 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideo_OTMDS_ODATA_Ratio[ucCDIdx][idx] << 12);
2079 }
2080 }
2081
2082 bIs420Fmt = TRUE;
2083 //MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2 for 420
2084
2085 }
2086 else if (HDMITxVideoModeTbl[idx].i_p_mode != E_HDMITX_VIDEO_INTERLACE_MODE)//Not 420
2087 {
2088 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x01C0, 0x0000); //video, pixel,tmds clock div 2 for 420
2089 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, 0x0001, 0x0000); //PHY tmds clock div 2
2090 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2091 }
2092 #else
2093 if (gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420)
2094 {
2095 switch (idx)
2096 {
2097 case E_HDMITX_RES_3840x2160p_50Hz:
2098 idx = E_HDMITX_RES_3840x2160p_25Hz;
2099 break;
2100
2101 case E_HDMITX_RES_3840x2160p_60Hz:
2102 idx = E_HDMITX_RES_3840x2160p_30Hz;
2103 break;
2104
2105 case E_HDMITX_RES_4096x2160p_50Hz:
2106 idx = E_HDMITX_RES_4096x2160p_25Hz;
2107 break;
2108
2109 case E_HDMITX_RES_4096x2160p_60Hz:
2110 idx = E_HDMITX_RES_4096x2160p_30Hz;
2111 break;
2112
2113 default:
2114 printf("[HDMITX] Invalid Combination of Color Format & Video Timing, Keep Origional Timing Setting!!\r\n");
2115 break;
2116 }
2117
2118 bIs420Fmt = TRUE;
2119 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2 for 420
2120 }
2121 #endif
2122
2123 //Timing Changed Judgement
2124 if( (MHal_HDMITx_Read(HDMITX_VIDEO_REG_BASE, REG_VE_STATUS_15) & 0x3FFF) == HDMITxVideoModeTbl[idx].vtotal)
2125 {
2126 if( MHal_HDMITx_Read(HDMITX_VIDEO_REG_BASE, REG_VE_STATUS_16) == HDMITxVideoModeTbl[idx].htotal)
2127 {
2128 MS_U32 uiSynthSet = 0;
2129 uiSynthSet |= (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0x0FFF);
2130 uiSynthSet = uiSynthSet << 16;
2131 uiSynthSet |= MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02);
2132
2133
2134 if(uiSynthSet == HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet)
2135 {
2136 ubTimingChanged = FALSE;
2137 }
2138 }
2139 }
2140
2141 if((idx == E_HDMITX_RES_720x480i) || (idx == E_HDMITX_RES_720x576i))
2142 {
2143 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x008B);
2144 MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x000F, 0x0001);//Repetition times
2145
2146 bIsRPMode = TRUE;
2147 }
2148 else
2149 {
2150 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x00AC);
2151 MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x000F, 0x0000);//Repetition times
2152
2153 bIsRPMode = FALSE;
2154 }
2155
2156 //enable H, VSync regen
2157 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x8001, 0x8001);
2158 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0002, HDMITxVideoModeTbl[idx].h_polarity ? 0x0002 : 0x0000);
2159 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0004, HDMITxVideoModeTbl[idx].v_polarity ? 0x0004 : 0x0000);
2160
2161 //deep color setting
2162 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00C0, ucCDIdx << 6);
2163
2164 //HDMITx phy clock
2165 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0xCC0C, 0x0000);
2166
2167 #if( (!(defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1))) && (!(defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))) )
2168 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2169 #endif
2170
2171 //sythesizer setting
2172 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, (MS_U16)(HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0000FFFF));
2173 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x0FFF, (MS_U16)((HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0FFF0000) >> 16));
2174
2175 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1003, 0x0000);
2176 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_26, 0x0100, 0x0000);
2177
2178 //atop
2179 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x0003, HDMITxVideoAtopSetting[ucCDIdx][idx].MUX_DIVSEL_POST);
2180 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0xC000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 14);
2181 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x3000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_PIXEL << 12);
2182
2183 #if 0
2184 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
2185 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
2186 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012);
2187 #else //RD suggestion
2188 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, 0x0000);
2189 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, 0x0000);
2190 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, 0x0000);
2191 #endif
2192
2193 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
2194 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
2195 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012);
2196
2197 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x000F, HDMITxVideoAtopSetting[ucCDIdx][idx].PD_RT);
2198
2199
2200 // Timing regeneration
2201 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT10|BIT13, 0x0000/*BIT10|BIT13*/); // 0: delay from DE end; 1: delay from end of h, v sync
2202
2203 #if( (!(defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1))) && (!(defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))) )
2204 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_02, HDMITxVideoModeTbl[idx].vs_width);
2205 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_05, HDMITxVideoModeTbl[idx].vs_delayline);
2206 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_06, HDMITxVideoModeTbl[idx].vs_delaypixel);
2207 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_07, HDMITxVideoModeTbl[idx].hs_width >> (bIs420Fmt ? 0x01 : 0x00));
2208 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_0A, HDMITxVideoModeTbl[idx].hs_delay >> (bIs420Fmt ? 0x01 : 0x00));
2209
2210 //for PG
2211 wHfront = HDMITxVideoModeTbl[idx].hs_delay;
2212 wVfront = HDMITxVideoModeTbl[idx].vs_delayline;
2213
2214 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0003, 0x0003);
2215 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hde_width/4 - 1) : (HDMITxVideoModeTbl[idx].hde_width/2 - 1));
2216 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, (bIs420Fmt||bIsRPMode) ?
2217 ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/4 - 1) : ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/2 - 1));
2218 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (bIs420Fmt||bIsRPMode) ? (wHfront/4 - 1) : (wHfront/2 - 1));
2219 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hs_width/4 - 1) : (HDMITxVideoModeTbl[idx].hs_width/2 - 1));
2220
2221 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_35, HDMITxVideoModeTbl[idx].vde_width - 1);
2222 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_36, (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) ?
2223 ((HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width)/2 - 1) : (HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width - 1));
2224 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_37, wVfront - 1);
2225 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_38, HDMITxVideoModeTbl[idx].vs_width - 1);
2226
2227 #else//444->420 || P2I
2228
2229 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_02, HDMITxVideoModeTbl[eSize_idx].vs_width);
2230 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_05, HDMITxVideoModeTbl[eSize_idx].vs_delayline);
2231 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_06, HDMITxVideoModeTbl[eSize_idx].vs_delaypixel);
2232 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_07, HDMITxVideoModeTbl[eSize_idx].hs_width >> (bIs420Fmt ? 0x01 : 0x00));
2233 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_0A, HDMITxVideoModeTbl[eSize_idx].hs_delay >> (bIs420Fmt ? 0x01 : 0x00));
2234
2235 //for PG
2236 wHfront = HDMITxVideoModeTbl[eSize_idx].hs_delay;
2237 wVfront = HDMITxVideoModeTbl[eSize_idx].vs_delayline;
2238
2239 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0003, 0x0003);
2240 #if (defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1))
2241 if( ( (eSize_idx == E_HDMITX_RES_3840x2160p_60Hz) || (eSize_idx == E_HDMITX_RES_3840x2160p_50Hz) || \
2242 (eSize_idx == E_HDMITX_RES_4096x2160p_50Hz) || (eSize_idx == E_HDMITX_RES_4096x2160p_60Hz)
2243 ) && bIs420Fmt && (cd_val > E_HDMITX_VIDEO_CD_24Bits)
2244 )//4K60 420
2245 {
2246 if( MHal_HDMITx_Read(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31) != (HDMITxVideoModeTbl[eSize_idx].hde_width/4 - 1) )
2247 {
2248 if(ubTimingChanged == FALSE)
2249 {
2250 ubTimingChanged = TRUE;
2251 }
2252 }
2253
2254 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (HDMITxVideoModeTbl[eSize_idx].hde_width/4 - 1) );
2255 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, ((HDMITxVideoModeTbl[eSize_idx].htotal - HDMITxVideoModeTbl[eSize_idx].hde_width)/4 - 1) );
2256 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (wHfront/4 - 1) );
2257 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (HDMITxVideoModeTbl[eSize_idx].hs_width/4 - 1) );
2258 }
2259 else
2260 {
2261 if(bIsRPMode)
2262 {
2263 if( MHal_HDMITx_Read(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31) != (HDMITxVideoModeTbl[eSize_idx].hde_width/4 - 1) )
2264 {
2265 if(ubTimingChanged == FALSE)
2266 {
2267 ubTimingChanged = TRUE;
2268 }
2269 }
2270 }
2271 else
2272 {
2273 if( MHal_HDMITx_Read(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31) != (HDMITxVideoModeTbl[eSize_idx].hde_width/2 - 1) )
2274 {
2275 if(ubTimingChanged == FALSE)
2276 {
2277 ubTimingChanged = TRUE;
2278 }
2279 }
2280 }
2281
2282 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (bIsRPMode) ? (HDMITxVideoModeTbl[eSize_idx].hde_width/4 - 1) : (HDMITxVideoModeTbl[eSize_idx].hde_width/2 - 1));
2283 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, (bIsRPMode) ?
2284 ((HDMITxVideoModeTbl[eSize_idx].htotal - HDMITxVideoModeTbl[eSize_idx].hde_width)/4 - 1) : ((HDMITxVideoModeTbl[eSize_idx].htotal - HDMITxVideoModeTbl[eSize_idx].hde_width)/2 - 1));
2285 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (bIsRPMode) ? (wHfront/4 - 1) : (wHfront/2 - 1));
2286 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (bIsRPMode) ? (HDMITxVideoModeTbl[eSize_idx].hs_width/4 - 1) : (HDMITxVideoModeTbl[eSize_idx].hs_width/2 - 1));
2287 }
2288 #else//Not 444->420
2289 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hde_width/4 - 1) : (HDMITxVideoModeTbl[idx].hde_width/2 - 1));
2290 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, (bIs420Fmt||bIsRPMode) ?
2291 ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/4 - 1) : ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/2 - 1));
2292 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (bIs420Fmt||bIsRPMode) ? (wHfront/4 - 1) : (wHfront/2 - 1));
2293 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hs_width/4 - 1) : (HDMITxVideoModeTbl[idx].hs_width/2 - 1));
2294 #endif
2295
2296 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_35, HDMITxVideoModeTbl[eSize_idx].vde_width - 1);
2297
2298 #if(defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
2299 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_36, (HDMITxVideoModeTbl[eSize_idx].vtotal - HDMITxVideoModeTbl[eSize_idx].vde_width - 1) );
2300 #else
2301 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_36, (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) ?
2302 ((HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width)/2 - 1) : (HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width - 1));
2303 #endif
2304 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_37, wVfront - 1);
2305 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_38, HDMITxVideoModeTbl[eSize_idx].vs_width - 1);
2306
2307 //P2I Setting
2308 #if(defined(HDMITX_SUPPORT_P2I) && (HDMITX_SUPPORT_P2I == 1))
2309 if(HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE)
2310 {
2311 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_50, 0x000D, 0x000D);
2312 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_52, wVfront);
2313 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_53, HDMITxVideoModeTbl[eSize_idx].vs_width);
2314 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_54, bIsRPMode ? wHfront/2 : wHfront);
2315 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_55, wHfront ? HDMITxVideoModeTbl[eSize_idx].hs_width/2 : HDMITxVideoModeTbl[eSize_idx].hs_width);
2316 }
2317 else
2318 {
2319 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_50, 0x000D, 0x0000);
2320 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_52, wVfront);
2321 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_53, HDMITxVideoModeTbl[eSize_idx].vs_width);
2322 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_54, bIsRPMode ? wHfront/2 : wHfront);
2323 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_55, wHfront ? HDMITxVideoModeTbl[eSize_idx].hs_width/2 : HDMITxVideoModeTbl[eSize_idx].hs_width);
2324 }
2325 #endif
2326
2327 //444 -> 420
2328 #if (defined(HDMITX_SUPPORT_444TO420) && (HDMITX_SUPPORT_444TO420 == 1))
2329 if(bIs420Fmt)
2330 {
2331 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_50, 0x0002, 0x0002);
2332 }
2333 else
2334 {
2335 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_50, 0x0002, 0x0000);
2336 }
2337 #endif///444->420
2338
2339 #endif//!444->420 && !P2I
2340
2341 MHal_HDMITx_EnableSSC(ubSSCEn);
2342
2343 // fifo reset
2344 if(ubTimingChanged)
2345 {
2346 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0x0008);
2347 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0);
2348 }
2349 }
2350
2351 //------------------------------------------------------------------------------
2352 /// @brief This routine will power on or off HDMITx clock (power saving)
2353 /// @param[in] bEnable: TRUE/FALSE
2354 /// @return None
2355 //------------------------------------------------------------------------------
MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)2356 void MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)
2357 {
2358 if (bEnable)
2359 {
2360 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, 0);
2361 }
2362 else
2363 {
2364 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, BIT0);
2365 }
2366 }
2367
2368
MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq,MS_BOOL bflag)2369 MS_BOOL MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq, MS_BOOL bflag)
2370 {
2371 //wilson@kano:TBD
2372 #if 1
2373 return FALSE;
2374 #else
2375 printf("[HDMITx] Bypass Mode = 0x%d\r\n", bflag);
2376 if (bflag == TRUE)
2377 {
2378 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, BIT0); //reg_atop_en_clko_vcodiv8_syn
2379
2380 //Note: change frequency tolerance if need
2381 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2382 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2383 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2384 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2385 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2386 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2387 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //change 250Mhz -> 297Mhz
2388
2389 //Enable Fifo and select input source
2390 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1919); //selct clock from Rx;
2391
2392 #if 0
2393 if (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7A) & 0x00C0) //for HDMI 2.0 timing bypass mode
2394 {
2395 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, BIT0); //tmds clock div 2;
2396 }
2397 #endif
2398
2399 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x000E, 0x0004); //[1:0]: Lane 0 to fifo; [2]: enable
2400 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x000E, 0x0005); //[1:0]: Lane 1 to fifo; [2]: enable
2401 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x000E, 0x0006); //[1:0]: Lane 2 to fifo; [2]: enable
2402 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x000E, 0x0007); //[1:0]: Lane 3 to fifo; [2]: enable
2403
2404 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1000, 0x1000); //bit repetition HW mode;
2405
2406 //synthesizer setting //TBD
2407 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x0001, 0x0001);
2408 //ssc_set = 0x140000
2409 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, 0x0000); //ssc_set [15..0]
2410 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x00FF, 0x0014);//ssc_set [7..0]
2411
2412 #if 0 //with SSC clock
2413 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, ssc_step);
2414 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3000, ssc_span);
2415 #else //without SSC clock
2416 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, 0x0000);
2417 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3FFF, 0x0000);
2418 #endif
2419
2420 //ATOP setting
2421 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00); //[9]:en_clk_pixel;[11]:en_clk_tmds;[13..15]:en_data_out
2422 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0x0000); //[11..0]: disable power down;[15:12]:pre-emphasis
2423 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x007F, 0x000F); //[3:0]:rterm turn off;[6:4]:disable power down
2424 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x2001); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2425 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0200); //[9] hdmi20 hw config mode;
2426 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7E, 0x0200, 0x0200); //[9]: freq range tolerance up direction;
2427 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_60, 0x0001, 0x0001); //[0]: freq range reset follow rx big change;
2428 }
2429 else
2430 {
2431 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2432 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2433 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2434 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2435 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2436 }
2437
2438 return TRUE;
2439
2440 #endif
2441 }
2442
2443
2444 /// @brief This routine will disable TMDS clock, data, and DDC... bypass mode
2445 /// @return None
2446 //------------------------------------------------------------------------------
MHal_HDMITx_Disable_RxBypass(void)2447 MS_BOOL MHal_HDMITx_Disable_RxBypass(void)
2448 {
2449 #if 1
2450 return FALSE;
2451 #else
2452 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2453 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2454 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2455 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2456 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2457
2458 return TRUE;
2459 #endif
2460 }
2461
2462
2463 //------------------------------------------------------------------------------
2464 /// @brief This routine will set GPIO pin for HPD
2465 /// @param[in] u8pin: GPIO0 ~ 12
2466 /// @return None
2467 //------------------------------------------------------------------------------
MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)2468 void MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)
2469 {
2470 printf("_gHPDGpioPin = 0x%X\r\n", u8pin);
2471 _gHPDGpioPin = u8pin;
2472 }
2473
2474 //------------------------------------------------------------------------------
2475 /// @brief This routine return CHIP capability of DVI mode
2476 /// @return TRUE, FALSE
2477 //------------------------------------------------------------------------------
MHal_HDMITx_IsSupportDVIMode(void)2478 MS_BOOL MHal_HDMITx_IsSupportDVIMode(void)
2479 {
2480 return TRUE;
2481 }
2482
2483 // ************* For customer NDS **************//
2484
MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process,MsHDMITX_AVI_CONTENT_TYPE content_type,MS_U16 * data)2485 void MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process, MsHDMITX_AVI_CONTENT_TYPE content_type, MS_U16 *data)
2486 {
2487 MS_U16 tmp_value=0;
2488
2489 if (IS_STOP_PKT(packet_process)) // Stop sending packet
2490 {
2491 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000); // Stop AVI packet
2492 }
2493 else
2494 {
2495 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0080, 0x80); // EIA version 2
2496 switch(content_type)
2497 {
2498 case E_HDMITX_AVI_PIXEL_FROMAT:
2499 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0060, *data);
2500 break;
2501 case E_HDMITX_AVI_ASPECT_RATIO:
2502 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x3F1F, *data);
2503 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0003, *(data+1));
2504 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_4_0C, 0xFFFF, *(data+2));
2505 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_5_0D, 0xFFFF, *(data+3));
2506 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_6_0E, 0xFFFF, *(data+4));
2507 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0xFFFF, *(data+5));
2508 break;
2509 case E_HDMITX_AVI_COLORIMETRY:
2510 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xC000, *data);
2511 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0030, *(data+1));
2512 break;
2513 default:
2514 break;
2515 }
2516
2517 tmp_value = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME); // Checksum
2518 // cyclic packet
2519 if (IS_CYCLIC_PKT(packet_process))
2520 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ( (tmp_value<<8) | (HDMITX_PACKET_AVI_FCNT<<3) | 0x0005)); // send AVI packet
2521 // single packet
2522 else
2523 {
2524 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (tmp_value<<8) | 0x0001);
2525 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1<<E_HDMITX_ACT_AVI_CMD);
2526 }
2527 }
2528 }
2529
2530 //wilson@kano
2531 //**************************************************************************
2532 // [Function Name]:
2533 // MHal_HDMITx_SetGCPParameter()
2534 // [Description]:
2535 // setting General Control packet attribute
2536 // [Arguments]:
2537 // [stGC_PktPara] stPktPara
2538 // [Return]:
2539 // void
2540 //
2541 //**************************************************************************
MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)2542 void MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)
2543 {
2544 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enAVMute = stPktPara.enAVMute;
2545 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enColorDepInfo = stPktPara.enColorDepInfo;
2546 }
2547
2548 //**************************************************************************
2549 // [Function Name]:
2550 // MHal_HDMITx_SetPktAttribute()
2551 // [Description]:
2552 // configure settings to corresponding packet
2553 // [Arguments]:
2554 // [MsHDMITX_PACKET_TYPE] enPktType
2555 // [MS_BOOL] bEnUserDef
2556 // [MS_U8] u8FrmCntNum
2557 // [MsHDMITX_PACKET_PROCESS] enPktCtrl
2558 // [Return]:
2559 // void
2560 //
2561 //**************************************************************************
MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType,MS_BOOL bEnUserDef,MS_U8 u8FrmCntNum,MsHDMITX_PACKET_PROCESS enPktCtrl)2562 void MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType, MS_BOOL bEnUserDef, MS_U8 u8FrmCntNum, MsHDMITX_PACKET_PROCESS enPktCtrl)
2563 {
2564 if (enPktType & 0x80) //infoframe packet type
2565 {
2566 gbInfoFrmPktList[enPktType & (~0x80)].EnableUserDef = bEnUserDef;
2567 gbInfoFrmPktList[enPktType & (~0x80)].FrmCntNum = u8FrmCntNum;
2568 gbInfoFrmPktList[enPktType & (~0x80)].enPktCtrl = enPktCtrl;
2569 }
2570 else
2571 {
2572 gbGeneralPktList[enPktType].EnableUserDef = bEnUserDef;
2573 gbGeneralPktList[enPktType].FrmCntNum = u8FrmCntNum;
2574 gbGeneralPktList[enPktType].enPktCtrl = enPktCtrl;
2575 }
2576 }
2577
2578 //**************************************************************************
2579 // [Function Name]:
2580 // MHal_HDMITx_SetAVIInfoParameter()
2581 // [Description]:
2582 // Assign content to AVI Infoframe packet
2583 // [Arguments]:
2584 // [stAVIInfo_PktPara] stPktPara
2585 // [Return]:
2586 // void
2587 //
2588 //**************************************************************************
MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)2589 void MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)
2590 {
2591 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.A0Value = stPktPara.A0Value;
2592 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enableAFDoverWrite = stPktPara.enableAFDoverWrite;
2593 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorFmt = stPktPara.enColorFmt;
2594 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorimetry = stPktPara.enColorimetry;
2595 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enExtColorimetry = stPktPara.enExtColorimetry;
2596 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enYCCQuantRange = stPktPara.enYCCQuantRange;
2597 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enVidTiming = stPktPara.enVidTiming;
2598 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAFDRatio = stPktPara.enAFDRatio;
2599 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enScanInfo = stPktPara.enScanInfo;
2600 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAspectRatio = stPktPara.enAspectRatio;
2601 }
2602
2603 //**************************************************************************
2604 // [Function Name]:
2605 // MHal_HDMITx_SetVSInfoParameter()
2606 // [Description]:
2607 // Assign content to VendorSpecific Infoframe packet
2608 // [Arguments]:
2609 // [stVSInfo_PktPara] stPketPara
2610 // [Return]:
2611 // void
2612 //
2613 //**************************************************************************
MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)2614 void MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)
2615 {
2616 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en3DStruct = stPktPara.en3DStruct;
2617 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en4k2kVIC = stPktPara.en4k2kVIC;
2618 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.enVSFmt = stPktPara.enVSFmt;
2619 }
2620
2621 //**************************************************************************
2622 // [Function Name]:
2623 // MHal_HDMITx_SetVSInfoParameter()
2624 // [Description]:
2625 // Assign content to VendorSpecific Infoframe packet
2626 // [Arguments]:
2627 // [stVSInfo_PktPara] stPketPara
2628 // [Return]:
2629 // void
2630 //
2631 //**************************************************************************
MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)2632 void MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)
2633 {
2634 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudChCnt = stPktPara.enAudChCnt;
2635 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudType = stPktPara.enAudType;
2636 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudFreq = stPktPara.enAudFreq;
2637 }
2638
2639 //**************************************************************************
2640 // [Function Name]:
2641 // MHal_HDMITx_SendPacket()
2642 // [Description]:
2643 // configure packet content and process according to user define or defalut setting
2644 // [Arguments]:
2645 // [MsHDMITX_PACKET_TYPE] enPktType
2646 // [Return]:
2647 // void
2648 //
2649 //**************************************************************************
MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType,MsHDMITX_PACKET_PROCESS packet_process)2650 void MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType, MsHDMITX_PACKET_PROCESS packet_process)
2651 {
2652 if (enPktType & 0x80) //info frame packet
2653 {
2654 MS_U8 ucInfoPktType = enPktType & (~0x80);
2655 MS_U8 ucChkSum = 0;
2656
2657 gbInfoFrmPktList[ucInfoPktType].enPktCtrl = packet_process;
2658
2659 switch (enPktType)
2660 {
2661 case E_HDMITX_VS_INFOFRAME:
2662 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2663 {
2664 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, 0x0005, 0x0000);
2665 }
2666 else
2667 {
2668 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2669 {
2670 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2671
2672 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2673 {
2674 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2675 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2676 }
2677 else
2678 {
2679 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2680 }
2681 }
2682 else
2683 {
2684 //fill IEEE HDMI tag
2685 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27, 0xFFFF, 0x0C03);
2686
2687 //check content
2688 if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_3D)
2689 {
2690 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_3D << 13); // video format
2691 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en3DStruct) << 4); // 3D structure
2692 }
2693 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_4k_2k)
2694 {
2695 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_4k_2k << 13); // video format
2696 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en4k2kVIC)); // 4k2k vic
2697 }
2698 else
2699 {
2700 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, 0); // video format
2701 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, 0);
2702 }
2703
2704 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2705
2706 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2707 {
2708 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2709 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2710 }
2711 else
2712 {
2713 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum << 8) | (HDMITX_PACKET_VS_FCNT << 3) | 0x0005));
2714 }
2715 }
2716 }
2717 break;
2718
2719 case E_HDMITX_AVI_INFOFRAME:
2720 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2721 {
2722 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000);
2723 }
2724 else
2725 {
2726 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2727 {
2728 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
2729
2730 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2731 {
2732 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
2733 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
2734 }
2735 else
2736 {
2737 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2738 }
2739 }
2740 else
2741 {
2742 MS_U8 ucPktVal = 0;
2743
2744 //Y2, Y1, Y0: RGB, YCbCr 422, 444, 420
2745 ucPktVal = (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt << 5);// | 0x10;
2746 //A0 field
2747 ucPktVal |= ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.A0Value == 0x01) ? 0x10 : 0x00);
2748 //S1, S0 field
2749 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enScanInfo);
2750
2751 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x00FF, (MS_U16)ucPktVal); //MDrv_WriteByte(REG_HDMITX_09_L, ucPktVal);
2752
2753 //C1, C0, M1, M0
2754 if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2755 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p))
2756 {
2757 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2758 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio << 4);
2759 }
2760 else
2761 {
2762 //HD timing is always 16:9
2763 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2764 }
2765
2766 //R3, R2, R1, R0: active porting aspect ration
2767 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enableAFDoverWrite == TRUE)
2768 {
2769 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAFDRatio & 0x0F);
2770 }
2771
2772 //ucPktVal |= ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry == 0) ? 0 : 0xC0; //set [C1, C0] = [1, 1]
2773
2774 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorimetry != E_HDMITX_COLORIMETRY_MAX)
2775 {
2776 ucPktVal = (ucPktVal & 0x3F) | ( ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorimetry & 0x03) << 6);
2777 }
2778
2779 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xFF00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_09_H, ucPktVal);
2780
2781 //EC0, EC1, EC2
2782 ucPktVal = (MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry;
2783 ucPktVal = (ucPktVal > 6) ? 6 : ucPktVal; //BT2020 RGB & BT2020 YCbCr share same value 6; 7 is reserved;
2784 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0070, ucPktVal << 4); //MDrv_WriteByteMask(REG_HDMITX_0A_L, ucPktVal << 4, 0x70);
2785
2786 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_RGB444)
2787 {
2788 //Q1, Q0
2789 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2790 {
2791 ucPktVal = 1;
2792 }
2793 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2794 {
2795 ucPktVal = 2;
2796 }
2797 else
2798 {
2799 ucPktVal = 0;
2800 }
2801
2802 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, ucPktVal << 2);
2803 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, 0x00);
2804 }
2805 else
2806 {
2807 //YQ1, YQ0
2808 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2809 {
2810 ucPktVal = 0;
2811 }
2812 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2813 {
2814 ucPktVal = 1;
2815 }
2816 else
2817 {
2818 ucPktVal = 3;
2819 }
2820
2821 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, 0x00);
2822 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, ucPktVal << 6);
2823 }
2824
2825 //VIC code: VIC code shoud +1 if aspect ration is 16:9
2826 ucPktVal = HDMITX_AviVicTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2827
2828 if (((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2829 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p)) &&
2830 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_16_9))
2831 {
2832 ucPktVal += 1;
2833 }
2834 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_21_9)
2835 {
2836 MS_U8 AR21_9MappingTbl[14][2] = {
2837 {60, 65},
2838 {61, 66},
2839 {62, 67},
2840 {19, 68},
2841 { 4, 69},
2842 {41, 70},
2843 {47, 71},
2844 {32, 72},
2845 {33, 73},
2846 {34, 74},
2847 {31, 75},
2848 {16, 76},
2849 {64, 77},
2850 {63, 78}
2851 };
2852
2853 if ((ucPktVal >= 93) && (ucPktVal <= 97))//3840*2160p@24 ~ 3840*2160@60
2854 {
2855 ucPktVal += 10;
2856 }
2857 else if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= 17) &&\
2858 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= 19))
2859 {
2860 ucPktVal += (103 + (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming - 17));
2861 }
2862 else if ((ucPktVal > 78) && (ucPktVal <= 92))
2863 {
2864 //do nothing;
2865 }
2866 else
2867 {
2868 MS_U8 i = 0;
2869 MS_BOOL bValidVIC = FALSE;
2870
2871 for ( i = 0; i < 14; i++ )
2872 {
2873 if (AR21_9MappingTbl[i][0] == ucPktVal)
2874 {
2875 ucPktVal = AR21_9MappingTbl[i][1];
2876 bValidVIC = TRUE;
2877 break;
2878 }
2879 }
2880
2881 if (!bValidVIC)
2882 {
2883 printf("%s :: Invalid VIC Code for 21:9 Aspect Ratio!!!\r\n", __FUNCTION__);
2884 }
2885 }
2886 }
2887
2888 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x7F00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_0A_H, (ucPktVal & 0x7F));
2889
2890 //check repetition
2891 if ((HDMITxVideoModeTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) &&
2892 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576i))
2893 {
2894 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0001); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x01, 0x0F);
2895 }
2896 else
2897 {
2898 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x00, 0x0F);
2899 }
2900
2901 //YQ1, YQ0
2902 //MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, (MS_U8)(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange << 6));
2903
2904 //AVI version
2905 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0x0300, (MS_U16)(HDMITX_AVI_INFO_PKT_VER << 8));
2906 //MDrv_WriteByteMask(REG_HDMITX_0F_H, HDMITX_AVI_INFO_PKT_VER, 0x03);
2907
2908 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
2909
2910 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2911 {
2912 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
2913 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
2914 }
2915 else
2916 {
2917 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3) | 0x0005));
2918 //MDrv_Write2Byte(REG_HDMITX_10_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3));
2919 }
2920 }
2921 }
2922 break;
2923
2924 case E_HDMITX_SPD_INFOFRAME:
2925 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2926 {
2927 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, 0x0005, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_22_L, 0x00, 0x05);
2928 }
2929 else
2930 {
2931 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2932 {
2933 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
2934
2935 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2936 {
2937 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
2938 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
2939 }
2940 else
2941 {
2942 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2943 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3));
2944 }
2945 }
2946 else
2947 {
2948 MS_U8 i = 0;
2949 MS_U8 ucPktVal = 0;
2950
2951 for (i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN + 1) >> 1); i++)
2952 {
2953 if (i < 4) // vendor name
2954 {
2955 ucPktVal = (HDMITX_VendorName[2*i+1]<<8) | HDMITX_VendorName[2*i];
2956 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+i, 0x7F7F, ucPktVal);
2957 }
2958 else if ((i >= 4) && (i < 12)) // product description
2959 {
2960 ucPktVal = (HDMITX_ProductName[2*(i-4)+1]<<8) | HDMITX_ProductName[2*(i-4)];
2961 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_5_19+(i-4), 0x7F7F, ucPktVal);
2962 }
2963 else // source device information
2964 {
2965 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_13_21, 0x00FF, HDMITX_PACKET_SPD_SDI);
2966 }
2967 }
2968
2969 #if 0
2970 for ( i = 0; i < (HDMITX_SPD_INFO_PKT_LEN - 1); i++ )
2971 {
2972 if ( i < 8 )
2973 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_VendorName[i]);
2974 else
2975 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_ProductName[i-8]);
2976 }
2977
2978 MDrv_WriteByte(REG_HDMITX_21_L, 0x01); //SPD infoframe, byte25: source information: 0x01 = Digital STB
2979 #endif
2980
2981 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
2982
2983 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2984 {
2985 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
2986 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
2987 }
2988 else
2989 {
2990 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3) | 0x0005));
2991 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3));
2992 }
2993 }
2994 }
2995
2996 break;
2997
2998 case E_HDMITX_AUDIO_INFOFRAME:
2999 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
3000 {
3001 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, 0x0005, 0x0000);
3002 }
3003 else
3004 {
3005 // Modified for HDMI CTS test -
3006 // - Audio Coding Type (CT3~CT0) is 0x0 then continue else then FAIL
3007 // - Sampling Frequency (SF2~ SF0) is zero then continue else then FAIL.
3008 // - Sample Size (SS1~ SS0) is zero then continue else then FAIL.
3009 //tmp_value = (gHDMITxInfo.output_audio_frequncy << 10) | 0x11; // audio sampling frequency, PCM and 2 channel.
3010 //MHal_HDMITx_Mask_Write(REG_HDMITX_BANK1, REG_PKT_AUD_1_11, 0x1FFF, tmp_value);
3011
3012 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt == E_HDMITX_AUDIO_CH_2) // 2-channel
3013 {
3014 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_2 - 1) & 0x07); // 2 channels
3015 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0); // Channel allocation
3016 }
3017 else //8- channel
3018 {
3019 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_8 - 1)&0x07); // 8 channels
3020 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0x1F00); // Channel allocation
3021 }
3022 //clear LFEP value
3023 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_3_13, 0x0001, 0x0000); //Fix LFEP defalut value in Kappa.
3024
3025 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AUDIO_INFOFRAME);
3026
3027 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3028 {
3029 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, (ucChkSum << 8) | 0x0001);
3030 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AUD_CMD);
3031 }
3032 else
3033 {
3034 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
3035 {
3036 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
3037 }
3038 else
3039 {
3040 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (HDMITX_PACKET_AUD_FCNT << 3) | 0x0005));
3041 }
3042 }
3043 }
3044
3045 //NOTE:: Kano move channel status from 0x00 to 0x0A
3046 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == FALSE)
3047 {
3048 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudType == E_HDMITX_AUDIO_PCM) ? 0 : BIT1)); // [1]: PCM / non-PCM
3049 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudFreq].CH_Status3 << 8) | (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
3050 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
3051 }
3052 // Audio sampling frequency
3053 // 1 1 0 0 32 kHz
3054 // 0 0 0 0 44.1 kHz
3055 // 0 0 0 1 88.2 kHz
3056 // 0 0 1 1 176.4 kHz
3057 // 0 1 0 0 48 kHz
3058 // 0 1 0 1 96 kHz
3059 // 0 1 1 1 192 kHz
3060 // 1 0 0 1 768 kHz
3061 break;
3062
3063 case E_HDMITX_MPEG_INFOFRAME:
3064 //TBD
3065 break;
3066
3067 case E_HDMITX_HDR_INFOFRAME:
3068 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
3069 {
3070 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000);
3071 }
3072 else
3073 {
3074 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
3075 {
3076 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
3077
3078 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3079 {
3080 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
3081 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
3082 }
3083 else
3084 {
3085 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
3086 }
3087 }
3088 else
3089 {
3090 //TBD
3091 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
3092
3093 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3094 {
3095 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
3096 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
3097 }
3098 else
3099 {
3100 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCNT << 3) | 0x0005));
3101 }
3102
3103 }
3104 }
3105 break;
3106
3107 default:
3108 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
3109 break;
3110 }
3111 }
3112 else //general packet
3113 {
3114 gbGeneralPktList[enPktType].enPktCtrl = packet_process;
3115
3116 switch (enPktType)
3117 {
3118 case E_HDMITX_NULL_PACKET:
3119 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
3120 {
3121 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x0005, 0x0000);
3122 }
3123 else
3124 {
3125 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3126 {
3127 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, 0x0001);
3128 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_NUL_CMD);
3129 }
3130 else
3131 {
3132 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3133 {
3134 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 3) |0x0005) );
3135 }
3136 else
3137 {
3138 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((HDMITX_PACKET_NULL_FCNT << 3) |0x0005) );
3139 }
3140 }
3141 }
3142 break;
3143
3144 case E_HDMITX_ACR_PACKET:
3145 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
3146 {
3147 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x000F, 0x0008);
3148 }
3149 else
3150 {
3151 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3152 {
3153 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, 0x0009);
3154 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACR_CMD);
3155 }
3156 else //cyclic
3157 {
3158 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3159 {
3160 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 4) |0x05));
3161 }
3162 else
3163 {
3164 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((HDMITX_PACKET_ACR_FCNT << 4) |0x05));
3165 }
3166 }
3167 }
3168 break;
3169
3170 case E_HDMITX_AS_PACKET:
3171 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
3172 {
3173 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable audio FIFO, [0]:audio FIFO flush
3174 }
3175 else
3176 {
3177 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT7); // [7]: enable audio FIFO, [0]:audio FIFO not flush
3178 }
3179 break;
3180
3181 case E_HDMITX_GC_PACKET:
3182 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
3183 {
3184 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x000F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | 0x0000);
3185 }
3186 else
3187 {
3188 //fill color depth information
3189 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC12_04, 0x010F, gbGeneralPktList[enPktType].PktPara.GCPktPara.enColorDepInfo); // [8]: default phase = 0, [3:0]: Color depth
3190
3191 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3192 {
3193 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1)| 0x21); // [6]: 0, DC and non-DC info send together
3194 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_GCP_CMD);
3195 //MDrv_WriteByteMask(REG_HDMITX_03_L, 0x21, 0x7F);
3196 }
3197 else //cyclic
3198 {
3199 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3200 {
3201 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (gbGeneralPktList[enPktType].FrmCntNum << 4) | 0x29));
3202 }
3203 else
3204 {
3205 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (HDMITX_PACKET_GC_FCNT << 4) | 0x29));
3206 }
3207 }
3208 }
3209 break;
3210
3211 case E_HDMITX_ACP_PACKET:
3212 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
3213 {
3214 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0005, 0x0000);
3215 }
3216 else
3217 {
3218 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_0_38, 0xFFFF, 0x0000); //acp type is 0x00
3219
3220 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3221 {
3222 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0001);
3223 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACP_CMD);
3224 }
3225 else //cyclic
3226 {
3227 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3228 {
3229 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
3230 }
3231 else
3232 {
3233 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, (HDMITX_PACKET_ACP_FCNT | 0x0005));
3234 }
3235 }
3236 }
3237 break;
3238
3239 case E_HDMITX_ISRC1_PACKET:
3240 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
3241 {
3242 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
3243 }
3244 else
3245 {
3246 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3247 {
3248 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0001);
3249 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
3250 }
3251 else //cyclic
3252 {
3253 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3254 {
3255 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005)); }
3256 else
3257 {
3258 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
3259 }
3260 }
3261 }
3262 break;
3263
3264 case E_HDMITX_ISRC2_PACKET:
3265 //check ISRC cnt value
3266 if (MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51) & 0x8000)
3267 {
3268 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
3269 {
3270 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
3271 }
3272 else
3273 {
3274 MS_U8 u8ISRCCntVal = 0x80;
3275
3276 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
3277 {
3278 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, (u8ISRCCntVal << 8) | 0x0001 ); // 0x80: ISRC_CONT = 1, ISRC1 & ISRC2
3279 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
3280 }
3281 else //cyclic
3282 {
3283 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
3284 {
3285 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
3286 }
3287 else
3288 {
3289 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
3290 }
3291 }
3292 }
3293 }
3294 break;
3295
3296 case E_HDMITX_DSD_PACKET:
3297 //TBD
3298 break;
3299
3300 case E_HDMITX_HBR_PACKET:
3301 //TBD
3302 break;
3303
3304 case E_HDMITX_GM_PACKET:
3305 //TBD
3306 break;
3307
3308 default:
3309 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
3310 break;
3311 }
3312 }
3313 }
3314
MHal_HDMITx_EnableSSC(MS_BOOL bEnable)3315 void MHal_HDMITx_EnableSSC(MS_BOOL bEnable)
3316 {
3317 //MST253B does not support SSC yet
3318 #if 0
3319 #define HDMITX_MPLL_CLK 432 //432MHz
3320 #define HDMITX_SSC_CLK 30 //30KHz
3321 #define HDMITX_SSC_DEVIATION 0.001 // 0.1%
3322 #define HDMITX_SSC_THREAD_LEVEL1 150 ///1080p 8bits
3323 #define HDMITX_SSC_THREAD_LEVEL2 300 ///4K30 8bits
3324 #define HDMITX_SSC_SPAN_REG REG_HDMITxPHY_CONFIG_06
3325 #define HDMITX_SSC_STEP_REG REG_HDMITxPHY_CONFIG_07
3326 #define HDMITX_SSC_SUB_DIVIDER_REG REG_HDMITxPHY_CONFIG_01
3327
3328 double ub2x19times = 524288;// 2^ 19
3329 double dSYNCLK = 1;
3330 double ub432MHz = HDMITX_MPLL_CLK;
3331 double ubSSCClk = HDMITX_SSC_CLK;
3332 double dSSc_Deviation= HDMITX_SSC_DEVIATION;
3333 MS_U32 ubSYNSet = 0;
3334 double dSSC_Span = 0;
3335 double dSSC_Step = 0;
3336 double dPixel_Clk = 0;
3337
3338 if(!bEnable)
3339 {
3340 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, 0 );//Span
3341 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, 0);//Step
3342 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0 );//Sub-Divider
3343 return;
3344 }
3345
3346
3347 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02);
3348 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16);
3349
3350 dSYNCLK = (double) ((ub432MHz*ub2x19times)/ubSYNSet);
3351
3352 dSSC_Span = dSYNCLK * 1000 / (ubSSCClk * 4); //Span = SYN_CLK / (SSC_CLK * 4)
3353 dSSC_Step = ubSYNSet * dSSc_Deviation / dSSC_Span; //Step = SYN_SET * deviation / Span
3354
3355 printf("ubSYNSet=%x, dSYNCLK=%f, dSSC_Span=%f, dSSC_Step=%f\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dSSC_Step);
3356
3357 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, ( ((int)dSSC_Span) & 0x3FFF) );//Span
3358 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, ( ((int)dSSC_Step) & 0xFFFF) );//Step
3359
3360 //Read tmds clock
3361 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_20, 0x3F, 0x3F);
3362 dPixel_Clk = (double) ( (double)(MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_21) << 1) * 12 / 128);
3363 printf("dPixel_Clk=%f\r\n", dPixel_Clk);
3364
3365 if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL1)
3366 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x0000 );//Sub-Divider
3367 else if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL2)
3368 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x1000 );//Sub-Divider
3369 else
3370 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x3000 );//Sub-Divider
3371 #endif
3372 }
3373
3374
3375