1 //<MStar Software>
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #define MHAL_HDMITX_C
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 // Common Definition
101 #ifdef MSOS_TYPE_LINUX_KERNEL
102 #include <linux/string.h>
103 #else
104 #include <string.h>
105 #endif
106
107 #include "MsCommon.h"
108
109 // Internal Definition
110 #include "regHDMITx.h"
111 #include "halHDMIUtilTx.h"
112 #include "halHDMITx.h"
113 #include "drvHDMITx.h"
114
115 // External Definition
116 #include "drvGPIO.h"
117 #include "drvSYS.h"
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126
127 #define GENERAL_PKT_NUM 0x0BU //wilson@kano
128 #define INFOFRM_PKT_NUM 0x08U //for HDR packet ID = 0x87; 0x06U //wilson@kano
129
130
131 #define HDMITX_VS_INFO_PKT_VER 0x01U
132 #define HDMITX_VS_INFO_PKT_LEN 0x1BU
133
134 #define HDMITX_AVI_INFO_PKT_VER 0x02U
135 #define HDMITX_AVI_INFO_PKT_LEN 0x0DU
136
137 #define HDMITX_SPD_INFO_PKT_VER 0x01U
138 #define HDMITX_SPD_INFO_PKT_LEN 0x19U
139
140 #define HDMITX_AUD_INFO_PKT_VER 0x01U
141 #define HDMITX_AUD_INFO_PKT_LEN 0x0AU
142
143 #define HDMITX_HDR_INFO_PKT_VER 0x01U
144 #define HDMITX_HDR_INFO_PKT_LEN 0x1BU //wilson@kano: temp solution
145
146
147
148 #define IS_STOP_PKT(_X_) ( (_X_ & E_HDMITX_STOP_PACKET) ? 1 : 0 )
149 #define IS_CYCLIC_PKT(_X_) ( (_X_ & E_HDMITX_CYCLIC_PACKET) ? 1 : 0 )
150
151 // HDMI packet cyclic frame count
152 #define HDMITX_PACKET_NULL_FCNT 0U ///< 0 ~ 31
153 #define HDMITX_PACKET_ACR_FCNT 0U ///< 0 ~ 15
154 #define HDMITX_PACKET_GC_FCNT 0U ///< 0 ~ 1
155 #define HDMITX_PACKET_ACP_FCNT 15U ///< 0 ~ 31
156 #define HDMITX_PACKET_ISRC_FCNT 15U ///< 0 ~ 31
157
158 #define HDMITX_PACKET_VS_FCNT 0U ///< 0 ~ 31
159 #define HDMITX_PACKET_AVI_FCNT 0U ///< 0 ~ 31
160 #define HDMITX_PACKET_SPD_FCNT 1U ///< 0 ~ 31
161 #define HDMITX_PACKET_AUD_FCNT 0U ///< 0 ~ 31
162 #define HDMITX_PACKET_HDR_FCNT 0U
163
164 #define HDMITX_PACKET_SPD_SDI 1U // Digital STB
165 #define HDMITX_CSC_SUPPORT_R2Y 1U
166
167 //-------------------------------------------------------------------------------------------------
168 // Local Structures
169 //-------------------------------------------------------------------------------------------------
170
171 //*********************//
172 // Video //
173 //*********************//
174
175 typedef struct
176 {
177 MDrv_HDMITx_VIDEO_MODE i_p_mode; // interlace / progressive mode
178 MDrv_HDMITx_VIDEO_POLARITY h_polarity; // Hsync polarity
179 MDrv_HDMITx_VIDEO_POLARITY v_polarity; // Vsync polarity
180 MS_U16 vs_width; // Vsync pulse width
181 MS_U16 vs_bporch; // Vsync back-porch
182 MS_U16 vde_width; // Vde active width
183 MS_U16 vs_delayline; // Vsync line delay
184 MS_U16 vs_delaypixel; // Vsync pixel delay
185 MS_U16 hs_width; // Hsync pulse width
186 MS_U16 hs_bporch; // Hsync back-porch
187 MS_U16 hde_width; // Hde active width
188 MS_U16 hs_delay; // Hsync delay
189 MS_U16 vtotal; // Vsync total
190 MS_U16 htotal; // Hsync total
191 } MDrv_HDMITx_VIDEO_MODE_INFO_TYPE;
192
193 //*********************//
194 // Packet //
195 //*********************//
196
197 typedef enum
198 {
199 E_HDMITX_ACT_GCP_CMD = 0,
200 E_HDMITX_ACT_ACR_CMD = 1,
201 E_HDMITX_ACT_AVI_CMD = 2,
202 E_HDMITX_ACT_AUD_CMD = 3,
203 E_HDMITX_ACT_SPD_CMD = 4,
204 E_HDMITX_ACT_MPG_CMD = 5,
205 E_HDMITX_ACT_VSP_CMD = 6,
206 E_HDMITX_ACT_NUL_CMD = 7,
207 E_HDMITX_ACT_ACP_CMD = 8,
208 E_HDMITX_ACT_ISRC_CMD = 9,
209 E_HDMITX_ACT_GCP_DC_CMD = 10, // GCP with non-zero CD
210 E_HDMITX_ACT_GMP_CMD = 11, // Gamut Metadata packet
211 } MDrvHDMITX_PKTS_ACT_CMD;
212
213 typedef struct PKT
214 {
215 MS_BOOL User_Define;
216 MsHDMITX_PACKET_PROCESS Define_Process;
217 MS_U8 Define_FCnt;
218 }PKT_Behavior;
219 //*********************//
220 // Audio //
221 //*********************//
222 typedef struct
223 {
224 MS_U8 CH_Status3;
225 MS_U32 NcodeValue;
226 } MDrv_HDMITx_AUDIO_FREQ_TYPE;
227
228 //-------------------------------------------------------------------------------------------------
229 // Global Variables
230 //-------------------------------------------------------------------------------------------------
231 MS_U8 gDivider = 0x00;
232 MS_BOOL gDivFlag = FALSE;
233 static MS_U8 gu8ChipVerNum = 0x00;
234
235 stHDMITx_PKT_ATTRIBUTE gbGeneralPktList[GENERAL_PKT_NUM]; //wilson@kano
236 stHDMITx_PKT_ATTRIBUTE gbInfoFrmPktList[INFOFRM_PKT_NUM]; //wilson@kano
237
238 // User defined packet behavior
239 PKT_Behavior NULL_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
240 PKT_Behavior ACR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
241 PKT_Behavior AS_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
242 PKT_Behavior GC_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
243 PKT_Behavior ACP_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
244 PKT_Behavior ISRC1_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
245 PKT_Behavior ISRC2_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
246 PKT_Behavior DSD_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
247 PKT_Behavior HBR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
248 PKT_Behavior GM_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
249
250 PKT_Behavior VS_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
251 PKT_Behavior AVI_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
252 PKT_Behavior SPD_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
253 PKT_Behavior AUDIO_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
254 PKT_Behavior MPEG_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
255 //-------------------------------------------------------------------------------------------------
256 // Local Variables
257 //-------------------------------------------------------------------------------------------------
258
259 //*********************//
260 // Video //
261 //*********************//
262
263 // It should be mapped with MsHDMITX_VIDEO_TIMING structure in drvHDMITx.h
264 MDrv_HDMITx_VIDEO_MODE_INFO_TYPE HDMITxVideoModeTbl[E_HDMITX_RES_MAX]=
265 {
266 //IorPMode; PolarityH; PolarityV; VSW; VbckP; VDe; VSDel; VSDelP; HSW; HbckP; HDe; HSDel; VSTotal; HSTotal;
267 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0002, 0x0021, 0x01E0, 0x000A, 0, 0x0060, 0x0030, 0x0280, 0x0010, 0x020D, 0x0320}, // 0: 640x480p
268 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x000F, 0x01E0, 0x0004, 0, 0x007C, 0x0072, 0x05A0, 0x0026, 0x020D, 0x06B4}, // 1: 720x480i
269 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x0013, 0x0240, 0x0002, 0, 0x007E, 0x008A, 0x05A0, 0x0018, 0x0271, 0x06C0}, // 2: 720x576i
270 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0006, 0x001E, 0x01E0, 0x0009, 0, 0x003E, 0x003C, 0x02D0, 0x0010, 0x020D, 0x035A}, // 3: 720x480p
271 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0005, 0x0027, 0x0240, 0x0005, 0, 0x0040, 0x0044, 0x02D0, 0x000C, 0x0271, 0x0360}, // 4: 720x576p
272 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x02EE, 0x07BC}, // 5: 1280x720p_50Hz
273 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x02EE, 0x0672}, // 6: 1280x720p_60Hz
274 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50}, // 7: 1920x1080i_50Hz
275 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898}, // 8: 1920x1080i_60Hz
276 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x0465, 0x0ABE}, // 9: 1920x1080p_24Hz
277 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50}, // 10: 1920x1080p_25Hz
278 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898}, // 11: 1920x1080p_30Hz
279 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50}, // 12: 1920x1080p_50Hz
280 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898}, // 13: 1920x1080p_60Hz
281 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x089D, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x08CA, 0x0ABE}, // 14: 1920x2205p_24Hz
282 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x05DC, 0x07BC}, // 15: 1280x1470p_50Hz
283 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x05DC, 0x0672}, // 16: 1280x1470p_60Hz
284
285 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x04FC, 0x08CA, 0x157C}, // 17:93: 3840x2160p_24Hz
286 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0}, // 18:94: 3840x2160p_25Hz
287 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130}, // 19:95: 3840x2160p_30Hz
288 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0}, // 20:96: 3840x2160p_50Hz
289 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130}, // 21:97: 3840x2160p_60Hz
290
291 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x1000, 0x03FC, 0x08CA, 0x157C}, // 22:98: 4096x2160p_24Hz
292 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0}, // 23:99: 4096x2160p_25Hz
293 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130}, // 24:100: 4096x2160p_30Hz
294 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0}, // 25:101: 4096x2160p_50Hz
295 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130}, // 26:102: 4096x2160p_60Hz
296
297 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0003, 0x002E, 0x04B0, 0x0001, 0, 0x00C0, 0x0130, 0x0640, 0x0040, 0x04E2, 0x0870, 60, 162000000}, // 27: 1600x1200p_60Hz
298 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0006, 0x0019, 0x0384, 0x0003, 0, 0x0098, 0x00E8, 0x05A0, 0x0050, 0x03A6, 0x0770, 60, 106500000}, // 28: 1440x900p_60Hz
299 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0003, 0x0026, 0x0400, 0x0001, 0, 0x0070, 0x00F8, 0x0500, 0x0030, 0x042A, 0x0698, 60, 108000000}, // 29: 1280x1024p_60Hz
300 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0006, 0x001D, 0x0300, 0x0003, 0, 0x0088, 0x00A0, 0x0400, 0x0024, 0x0326, 0x0540, 60, 65000000}, // 30: 1024x768p_60Hz
301 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
302 };
303
304 //atop setting
305 stHDMITx_ATOP_SETTING HDMITxVideoAtopSetting[HDMITX_COLOR_DEPTH_TYPE_NUM][E_HDMITX_RES_MAX] =
306 {
307 //color depth = 8bit
308 {
309 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
310 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
311 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
312 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
313 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
314 // 74Mhz
315 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
316 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
317 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
318 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
319 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
320 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
321 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
322 // 148Mhz
323 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 12: 1920x1080p_50Hz
324 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 13: 1920x1080p_60Hz
325 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 14: 1920x2205p_24Hz
326 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 15: 1280x1470p_50Hz
327 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 16: 1280x1470p_60Hz
328 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
329 // 300Mhz
330 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
331 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
332 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
333 // 600Mhz
334 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
335 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
336 // 300Mhz
337 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
338 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
339 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
340 // 600Mhz
341 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
342 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
343
344 // 150MHz
345 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x2AAAAA}, // 27: 1600x1200p_60Hz
346 // 106.5MHz
347 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x40EB71}, // 28: 1440x900p_60Hz
348 // 108MHz
349 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 29: 1280x1024p_60Hz
350 // 65MHz
351 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x352B52}, // 30: 1024x768p_60Hz
352 },
353
354 //color depth = 10 bit
355 {
356 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 0: 640x480p
357 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 1: 720x480i
358 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 2: 720x576i
359 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 3: 720x480p
360 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 4: 720x576p
361 // 74Mhz
362 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 5: 1280x720p_50Hz
363 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 6: 1280x720p_60Hz
364 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 7: 1920x1080i_50Hz
365 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x25460A}, // 8: 1920x1080i_60Hz
366 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 9: 1920x1080p_24Hz
367 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 10: 1920x1080p_25Hz
368 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 11: 1920x1080p_30Hz
369 // 148Mhz
370 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 12: 1920x1080p_50Hz
371 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 13: 1920x1080p_60Hz
372 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 14: 1920x2205p_24Hz
373 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 15: 1280x1470p_50Hz
374 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 16: 1280x1470p_60Hz
375 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
376 // 300Mhz
377 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 17:93: 3840x2160p_24Hz
378 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 18:94: 3840x2160p_25Hz
379 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 19:95: 3840x2160p_30Hz
380 // 600Mhz ==> not support !!!
381 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 20:96: 3840x2160p_50Hz
382 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 21:97: 3840x2160p_60Hz
383 // 300Mhz
384 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 22:98: 4096x2160p_24Hz
385 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 23:99: 4096x2160p_25Hz
386 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 24:100: 4096x2160p_30Hz
387 // 600Mhz ==> not support !!!
388 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 25:101: 4096x2160p_50Hz
389 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 26:102: 4096x2160p_60Hz
390
391 // 150MHz
392 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x222222}, // 27: 1600x1200p_60Hz
393 // 106.5MHz
394 //{0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x33EBCE}, // 28: 1440x900p_60Hz
395 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x33EF8D},
396 // 108MHz
397 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 29: 1280x1024p_60Hz
398 // 65MHz
399 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x2A890E}, // 30: 1024x768p_60Hz
400 },
401
402 //color depth = 12 bit
403 {
404 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 0: 640x480p
405 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 1: 720x480i
406 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 2: 720x576i
407 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 3: 720x480p
408 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 4: 720x576p
409 // 74Mhz
410 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 5: 1280x720p_50Hz
411 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 6: 1280x720p_60Hz
412 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 7: 1920x1080i_50Hz
413 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F0FB3}, // 8: 1920x1080i_60Hz
414 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 9: 1920x1080p_24Hz
415 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 10: 1920x1080p_25Hz
416 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 11: 1920x1080p_30Hz
417 // 148Mhz
418 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 12: 1920x1080p_50Hz
419 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 13: 1920x1080p_60Hz
420 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 14: 1920x2205p_24Hz
421 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 15: 1280x1470p_50Hz
422 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 16: 1280x1470p_60Hz
423 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
424 // 300Mhz
425 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 17:93: 3840x2160p_24Hz
426 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 18:94: 3840x2160p_25Hz
427 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 19:95: 3840x2160p_30Hz
428 // 600Mhz ==> not support !!!
429 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 20:96: 3840x2160p_50Hz
430 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 21:97: 3840x2160p_60Hz
431 // 300Mhz
432 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 22:98: 4096x2160p_24Hz
433 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 23:99: 4096x2160p_25Hz
434 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 24:100: 4096x2160p_30Hz
435 // 600Mhz ==> not support !!!
436 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 25:101: 4096x2160p_50Hz
437 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 26:102: 4096x2160p_60Hz
438
439 // 150MHz
440 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x04, 0x1C71C7}, // 27: 1600x1200p_60Hz
441 // 106.5MHz
442 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x2B47A0}, // 28: 1440x900p_60Hz
443 // 108MHz
444 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x2AAAAA}, // 29: 1280x1024p_60Hz
445 // 65MHz
446 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x237237}, // 30: 1024x768p_60Hz
447 },
448
449 //color depth = 16 bit
450 {
451 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
452 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
453 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
454 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
455 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
456 // 74Mhz
457 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
458 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
459 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
460 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
461 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
462 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
463 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
464 // 148Mhz
465 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 12: 1920x1080p_50Hz
466 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 13: 1920x1080p_60Hz
467 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 14: 1920x2205p_24Hz
468 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 15: 1280x1470p_50Hz
469 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 16: 1280x1470p_60Hz
470 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
471 // 300Mhz
472 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
473 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
474 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
475 // 600Mhz ==> Not support !!!
476 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
477 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
478 // 300Mhz
479 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
480 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
481 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
482 // 600Mhz ==> Not support !!!
483 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
484 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
485
486 // 150MHz
487 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x04, 0x2AAAAA}, // 27: 1600x1200p_60Hz
488 // 106.5MHz
489 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x40EB71}, // 28: 1440x900p_60Hz
490 // 108MHz
491 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x400000}, // 29: 1280x1024p_60Hz
492 // 65MHz
493 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x352B52}, // 30: 1024x768p_60Hz
494 },
495 };
496
497 //*********************//
498 // Audio //
499 //*********************//
500
501 MSTHDMITX_REG_TYPE HDMITxAudioOnTbl[] =
502 {
503 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enable audio FIFO, [2]:enable CTS Gen, [1]: automatically block start, [0]: audio FIFO not flush
504 };
505
506 MSTHDMITX_REG_TYPE HDMITxAudioOffTbl[] =
507 {
508 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
509 };
510
511 MSTHDMITX_REG_TYPE HDMITxAudioInitTbl[] =
512 {
513 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
514 };
515
516 MDrv_HDMITx_AUDIO_FREQ_TYPE TxAudioFreqTbl[E_HDMITX_AUDIO_FREQ_MAX_NUM] =
517 {
518 {0x02, 0x001800}, // No signal, set to 48 KHz
519 {0x03, 0x001000}, // 0 ~(32)~ 38 KHz, 4096
520 {0x00, 0x001880}, // 38 ~(44.1)~ 46 KHz, 6272
521 {0x02, 0x001800}, // 46 ~(48)~ 60 KHz, 6144
522 {0x08, 0x003100}, // 60 ~(88.2)~ 92 KHz, 12544
523 {0x0a, 0x003000}, // 92 ~(96)~ 140 KHz, 12288
524 {0x0c, 0x006200}, // 140 ~(176.4)~ 180 KHz, 25088
525 {0x0e, 0x006000}, // 180 ~(192)~ ~~ KHz, 24576
526 };
527
528 //*********************//
529 // Packet //
530 //*********************//
531
532 MS_U8 HDMITX_AviCmrTbl[E_HDMITX_RES_MAX] =
533 {
534 0x48, 0x48, 0x48, 0x48, 0x48, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, // SDTV C=01(601),M=00(no data) ,R=1000(same)
535 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0x48,
536 0xA8, 0x48, 0x48,
537 };
538
539 MS_U8 HDMITX_AviVicTbl[E_HDMITX_RES_MAX] =
540 {
541 1, 6, 21, 2, 17, 19, 4, 20, 5, 32, 33, 34, 31, 16, // SDTV 480i60,576i50,480p60,576p50,720p50,720p60,1080i50,1080i60,1080p24,1080p25,1080p30, 1080p50, 1080p60
542 32, 19, 4, 0, 0, 0, 96, 97, 0, 99, 100, 101, 102, 0,
543 0, 0, 0,
544 };
545 MS_U8 HDMITX_VendorName[8] =
546 {
547 "MStar "
548 };
549
550 MS_U8 HDMITX_ProductName[16] =
551 {
552 "HDMI Tx Demo",
553 };
554
555 MS_U8 _gHPDGpioPin = 0;
556
557 //-------------------------------------------------------------------------------------------------
558 // Debug Functions
559 //-------------------------------------------------------------------------------------------------
560
561 #ifdef MS_DEBUG
562 #define DBG_HDMITX(_f) (_f)
563 #else
564 #define DBG_HDMITX(_f)
565 #endif
566
567 //-------------------------------------------------------------------------------------------------
568 // Local Functions
569 //-------------------------------------------------------------------------------------------------
570
571
572 //-------------------------------------------------------------------------------------------------
573 // Global Functions
574 //-------------------------------------------------------------------------------------------------
575 /*********************************************************************/
576 /* */
577 /* HDCP22 Relative */
578 /* */
579 /*********************************************************************/
MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)580 void MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)
581 {
582 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x11, bEnable ? 0x11 : 0x00); // bit 0: enable hdcp22; bit 4: enable EESS
583 if (bEnable)
584 {
585 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x02); //reset hdcp22 FSM
586 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x00);
587 }
588 }
589
MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)590 void MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)
591 {
592 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x04, bEnable ? 0x04 : 0x00); //bit 2: authentication pass
593 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x08, bEnable ? 0x08 : 0x00); //bit 3: enable hdcp22 to issue encryption enable signal
594 }
595
MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 * pu8Riv,MS_U8 * pu8KsXORLC128)596 void MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 *pu8Riv, MS_U8 *pu8KsXORLC128)
597 {
598 #define DEF_HDCP2CIPHER_DBG 0
599 #define SIZE_OF_KSXORLC128 16
600 #define SIZE_OF_RIV 8
601
602 MS_U8 cnt = 0;
603
604 #if (DEF_HDCP2CIPHER_DBG == 1)
605 printf("Ks^LC128:\r\n");
606 for ( cnt = 0; cnt < SIZE_OF_KSXORLC128; cnt++ )
607 {
608 printf("0x%02X ", *(pu8KsXORLC128 + cnt));
609 }
610 printf("\r\n");
611
612 printf("Riv:\r\n");
613 for ( cnt = 0; cnt < SIZE_OF_RIV; cnt++ )
614 {
615 printf("0x%02X ", *(pu8Riv + cnt));
616 }
617 printf("\r\n");
618 #endif
619
620 #undef DEF_HDCP2CIPHER_DBG
621 //MHal_HDMITx_Mask_Write(0x172F00, 0x01, 0x0020, 0x0020); //reverse order of cihper key
622 //MHal_HDMITx_Mask_Write(0x172B00, 0x01, 0x8000, 0x0000); //disable hdcp 1.4 module
623
624 for ( cnt = 0; cnt < (SIZE_OF_KSXORLC128>>1); cnt++)
625 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x60 + (SIZE_OF_KSXORLC128 >> 1) - 1 - cnt, *(pu8KsXORLC128 + cnt*2 + 1)|(*(pu8KsXORLC128 + cnt*2)<<8));
626
627 for ( cnt = 0; cnt < (SIZE_OF_RIV>>1); cnt++)
628 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x68 + (SIZE_OF_RIV >> 1) - 1 - cnt, *(pu8Riv + cnt*2 + 1)|(*(pu8Riv + cnt*2)<<8));
629 }
630
MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)631 void MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)
632 {
633 gu8ChipVerNum = u8ChipVer;
634 }
635
636 // HPD: GPIO_PM[11] -> external interrupt[11], register 0x000E00[14]
637 // DVI disconnet: must power down clock termination resistor: TM_REG[0] = 1, TM_REG[16:15] = 00, TM_REG[35:34] = 00.
638 // Interrupt helper functoins
639 //------------------------------------------------------------------------------
640 /// @brief Disable interrupt
641 /// @param[in] u32Int interrupter value
642 /// @return None
643 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Disable(MS_U32 u32Int)644 void MHal_HDMITx_Int_Disable(MS_U32 u32Int)
645 {
646 //MS_U16 u16reg_val = 0;
647
648 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int);
649 // [9]: mask FIQ, [8]: mask IRQ
650 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) );
651
652 #if 0 // K1 HPD pin doesn't have interrupt function
653 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
654 {
655 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
656 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank
657 {
658 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask
659 }
660 }
661 #endif
662 }
663
664 //------------------------------------------------------------------------------
665 /// @brief Enable interrupt
666 /// @param[in] u32Int interrupter value
667 /// @return None
668 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Enable(MS_U32 u32Int)669 void MHal_HDMITx_Int_Enable(MS_U32 u32Int)
670 {
671 //MS_U16 u16reg_val = 0;
672
673 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int);
674 // [9]: mask FIQ, [8]: unmask IRQ
675 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 );
676
677 #if 0 // K1 HPD pin doesn't have interrupt function
678 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
679 {
680 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
681 if(u32Int & E_HDMITX_IRQ_12)
682 {
683 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_PM output disable
684 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask
685 }
686 }
687 #endif
688 }
689
690 //------------------------------------------------------------------------------
691 /// @brief MHal_HDMITx_Int_Clear
692 /// @param[in] u32Int interrupter value
693 /// @return None
694 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Clear(MS_U32 u32Int)695 void MHal_HDMITx_Int_Clear(MS_U32 u32Int)
696 {
697 //MS_U16 u16reg_val = 0;
698
699 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int);
700 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16));
701
702 #if 0 // K1 HPD pin doesn't have interrupt function
703 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
704 {
705 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
706 if(u32Int & E_HDMITX_IRQ_12)
707 {
708 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val);
709 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0);
710 }
711 }
712 #endif
713 }
714
715 //------------------------------------------------------------------------------
716 /// @brief MHal_HDMITx_Int_Status
717 /// @param[in] u32Int interrupter value
718 /// @return None
719 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Status(void)720 MS_U32 MHal_HDMITx_Int_Status(void)
721 {
722 //MS_U16 u16reg_val = 0;
723 MS_U32 reg_value=0;
724
725 reg_value |= MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E);
726 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16);
727
728 #if 0 // K1 HPD pin doesn't have interrupt function
729 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4
730 {
731 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
732 reg_value = ((MHal_HDMITxPM_Read(PMBK_PMSLEEP_REG_BASE, 0x0A) & u16reg_val) ? (reg_value|E_HDMITX_IRQ_12):(reg_value&(~E_HDMITX_IRQ_12)));
733 }
734 #endif
735 return reg_value;
736 }
737
738
739 //------------------------------------------------------------------------------
740 /// @brief This routine is to get HDMI receiver DVI clock and HPD status.
741 /// @return MsHDMITX_RX_STATUS
742 //------------------------------------------------------------------------------
MHal_HDMITx_GetRXStatus(void)743 MsHDMITX_RX_STATUS MHal_HDMITx_GetRXStatus(void)
744 {
745 MS_BOOL dviclock_s, hpd_s = FALSE;
746 MsHDMITX_RX_STATUS state;
747
748 dviclock_s = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F) & BIT0 ? FALSE : TRUE;
749
750 #if (defined(MSOS_TYPE_LINUX_KERNEL))
751 hpd_s = MHal_HDMITx_Read(0x001100, 0x33); //temp solution for kernal mode: GPIO 23
752 #else
753 hpd_s = mdrv_gpio_get_level(_gHPDGpioPin);
754 #endif
755
756 if((dviclock_s == FALSE) && (hpd_s == FALSE))
757 state = E_HDMITX_DVIClock_L_HPD_L;
758 else if((dviclock_s == FALSE) && (hpd_s == TRUE))
759 state = E_HDMITX_DVIClock_L_HPD_H;
760 else if((dviclock_s == TRUE) && (hpd_s == FALSE))
761 state = E_HDMITX_DVIClock_H_HPD_L;
762 else
763 state = E_HDMITX_DVIClock_H_HPD_H;
764
765 return state;
766 }
767
768
769 //------------------------------------------------------------------------------
770 /// @brief MHal_HDMITX_SetHDCPConfig
771 /// @param[in] u32Int HDCP mode
772 /// @return None
773 //------------------------------------------------------------------------------
MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)774 void MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)
775 {
776 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8);
777 }
778
779
780 //------------------------------------------------------------------------------
781 /// @brief MHal_HDMITX_GetM02Bytes
782 /// @param[in] u16Int index
783 /// @return M0 2 bytes
784 //------------------------------------------------------------------------------
MHal_HDMITX_GetM02Bytes(MS_U16 idx)785 MS_U16 MHal_HDMITX_GetM02Bytes(MS_U16 idx)
786 {
787 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx));
788 }
789
790
791 //------------------------------------------------------------------------------
792 /// @brief MHal_HDMITx_InitSeq
793 /// @param[in] None
794 /// @return None
795 //------------------------------------------------------------------------------
MHal_HDMITx_InitSeq(void)796 void MHal_HDMITx_InitSeq(void)
797 {
798 MHal_HDMITx_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, 0); // enable clk_hdmi_tx_p
799
800 //set at mboot
801 //MHal_HDMITx_Mask_Write(0x101E00, 0x0B, BIT12, BIT12); //enable hdmitx DDC
802
803 //MAC setting
804 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1C, 0x0000);
805 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1D, 0x0000);
806 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1E, 0xFFFF);
807 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1F, 0x0000);
808
809 //sw reset modules
810 if(MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E) & 0xE800)
811 {
812 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
813 }
814 else
815 {
816 //disable power down
817 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
818 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
819 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
820 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0017);
821 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0000);
822 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x001F);
823 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x0000);
824 }
825
826 //MHal_HDMITx_Write(HDMITX_REG_BASE, REG_HPLL_LOCK_CNT_53, 0x0300); // HPLL lock counter
827
828 //enable PHY setting
829 //[0]:enable synth clock; [4]:enable synth clock to a top; [8]:enable tmds clock; [12]: enable atop 40 bit clock
830 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101, 0x1101);
831 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
832 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00);
833
834 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F, 0x0010, 0x0010); //reg_atop_nodie_en_disc
835
836 //disable power down
837 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
838 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, 0x0000);
839
840 //rterm set by Mboot according to data of EFUSE, rterm 50 Ohm
841 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x01F0, 0x0000);
842
843 //txpll input div 1
844 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x03F3, 0x0051);
845
846 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3D, 0x030F, 0x0003); //REG_TXPLL_SEL_CLKIN, REG_TXPLL_ICP_ICTRL
847 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0003); //REG_ICTRL_PREDRV_MAIN_CLK
848 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0000); //REG_ICTRL_PREDRV_MAIN_CLK
849 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x003F, 0x0010); //REG_ICTRL_DRV_MAIN_CLK
850
851 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_32, 0x3F3F, 0x0000);
852 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_36, 0x3F3F, 0x0000);
853 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_37, 0x3F3F, 0x0000);
854
855 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
856
857 //lane fifo setting
858 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x0007, 0x0004);
859 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x0007, 0x0005);
860 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x0007, 0x0006);
861 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x0007, 0x0007);
862
863 //timing field regen enable (due to scaler can't guarantee field signal and even/odd frame is asynchronize)
864 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x0010, 0x0010);
865
866 //for U02: QD980 CTS compatibility issue
867 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x8000, 0x8000);
868
869 }
870
871 //------------------------------------------------------------------------------
872 /// @brief This routine is the initialization for Video module.
873 /// @return None
874 //------------------------------------------------------------------------------
MHal_HDMITx_VideoInit(void)875 void MHal_HDMITx_VideoInit(void)
876 {
877 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, BIT4, BIT4); //enable video engine fifo r/w pointer
878 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_12, 0x000F, BIT3); // [3]: manual mode of pixel-repetition enable
879 }
880
881 //------------------------------------------------------------------------------
882 /// @brief This routine is the initialization for Audio module.
883 /// @return None
884 //------------------------------------------------------------------------------
MHal_HDMITx_AudioInit(void)885 void MHal_HDMITx_AudioInit(void)
886 {
887 int num;
888
889 num = sizeof(HDMITxAudioInitTbl) / sizeof(MSTHDMITX_REG_TYPE);
890 MHal_HDMITx_RegsTbl_Write(HDMITxAudioInitTbl, num);
891 }
892
893
894 //------------------------------------------------------------------------------
895 /// @brief This routine turn on/off HDMI PLL
896 /// @return None
897 //------------------------------------------------------------------------------
MHal_HDMITx_PLLOnOff(MS_BOOL bflag)898 void MHal_HDMITx_PLLOnOff(MS_BOOL bflag)
899 {
900 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, bflag ? 0x0000 : 0x0010);
901 }
902
903
MHal_HDMITx_PKT_User_Define_Clear(void)904 void MHal_HDMITx_PKT_User_Define_Clear(void)
905 {
906 MS_U8 i = 0;
907
908 for ( i = 0; i < GENERAL_PKT_NUM; i++ )
909 {
910 gbGeneralPktList[i].EnableUserDef = FALSE;
911 gbGeneralPktList[i].FrmCntNum = 0x00;
912 gbGeneralPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
913 memset(&gbGeneralPktList[i].PktPara, 0x00, sizeof(gbGeneralPktList[i].PktPara));
914 }
915
916 for ( i = 0; i < INFOFRM_PKT_NUM; i++ )
917 {
918 gbInfoFrmPktList[i].EnableUserDef = FALSE;
919 gbInfoFrmPktList[i].FrmCntNum = 0x00;
920 gbInfoFrmPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
921 memset(&gbInfoFrmPktList[i].PktPara, 0x00, sizeof(gbInfoFrmPktList[i].PktPara));
922 }
923 }
924
MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type,MS_BOOL def_flag,MsHDMITX_PACKET_PROCESS def_process,MS_U8 def_fcnt)925 void MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type, MS_BOOL def_flag,
926 MsHDMITX_PACKET_PROCESS def_process, MS_U8 def_fcnt)
927 {
928 if (packet_type & 0x80) //infoframe packet type
929 {
930 gbInfoFrmPktList[packet_type & (~0x80)].EnableUserDef = def_flag;
931 gbInfoFrmPktList[packet_type & (~0x80)].FrmCntNum = def_fcnt;
932 gbInfoFrmPktList[packet_type & (~0x80)].enPktCtrl = def_process;
933 }
934 else
935 {
936 gbGeneralPktList[packet_type].EnableUserDef = def_flag;
937 gbGeneralPktList[packet_type].FrmCntNum = def_fcnt;
938 gbGeneralPktList[packet_type].enPktCtrl = def_process;
939 }
940 }
941
MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type,MS_U8 * data,MS_U8 length)942 MS_BOOL MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type, MS_U8* data, MS_U8 length)
943 {
944 MS_BOOL bRet = TRUE;
945 MS_U8 i, j, *ptr;
946 ptr = data;
947
948 switch(packet_type)
949 {
950 case E_HDMITX_VS_INFOFRAME:
951 for (i=0; i < length; i++)
952 {
953 j = i>>1;
954
955 if ((REG_PKT_VS_1_27+j > REG_PKT_VS_14_34) || ((REG_PKT_VS_1_27+j == REG_PKT_VS_14_34) && (i % 2 == 1)))
956 {
957 //Packet over size, last VS packet PB register is REG_PKT_VS_14_34[7:0]
958 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
959 break;
960 }
961
962 if((i%2)==0)
963 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0x00FF, *(ptr+i));
964 else
965 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0xFF00, (*(ptr+i))<<8);
966 }
967 break;
968 case E_HDMITX_SPD_INFOFRAME:
969 for(i=0;i<length;i++)
970 {
971 j = i>>1;
972
973 if((REG_PKT_SPD_1_15+j > REG_PKT_SPD_13_21) || ((REG_PKT_SPD_1_15+j == REG_PKT_SPD_13_21) && (i % 2 == 1)))
974 {
975 //Packet over size, last SPD packet PB register is REG_PKT_SPD_13_21[7:0]
976 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
977 break;
978 }
979
980 if((i%2)==0)
981 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0x00FF, *(ptr+i));
982 else
983 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0xFF00, (*(ptr+i))<<8);
984 }
985 break;
986
987 //wilson@kano HDR packet
988 case E_HDMITX_HDR_INFOFRAME:
989 //first 3 bytes will follow spec, (1) type code (2) version (3) length, and reamins will be content
990 length = (length > (HDMITX_HDR_INFO_PKT_LEN + 3)) ? (HDMITX_HDR_INFO_PKT_LEN + 3) : length;
991 //fill length and version
992 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F,(*(ptr+2) << 8) | *(ptr+1));
993
994 if (length >= 3)
995 {
996 for ( i = 0; i < (length-3); i++ )
997 {
998 j = i >> 1;
999
1000 if ( ((REG_HDMI_2_CONFIG_10 + j) > REG_HDMI_2_CONFIG_1D) || (((REG_HDMI_2_CONFIG_10 + j) == REG_HDMI_2_CONFIG_1D) && (i % 2 == 1)) )
1001 {
1002 DBG_HDMITX(printf("HDR packet over size, length = %d \n", length));
1003 break;
1004 }
1005
1006 if ((i % 2) == 0)
1007 {
1008 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0x00FF, *(ptr+i+3));
1009 }
1010 else
1011 {
1012 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0xFF00, (*(ptr+i+3))<<8);
1013 }
1014 }
1015 }
1016 break;
1017
1018 case E_HDMITX_AUDIO_INFOFRAME:
1019 {
1020 //total length should be 192 bits *2 = 384 bits = 48 bytes;
1021
1022 length = (length < ((192>>3)<<1) ) ? length : ((192>>3)<<1);
1023
1024 for ( i = 0; i < length; i++ )
1025 {
1026 j = i >> 1;
1027
1028 if ((i % 2) == 0)
1029 {
1030 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0x00FF, *(ptr+i));
1031 }
1032 else
1033 {
1034 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0xFF00, (*(ptr+i) << 8));
1035 }
1036 }
1037 }
1038 break;
1039
1040 default:
1041 i = 0;
1042 j = 0;
1043 bRet = FALSE;
1044 DBG_HDMITX(printf("Not implemented, packet type = %u\n", packet_type));
1045 break;
1046 }
1047
1048 return bRet;
1049 }
1050
1051 //------------------------------------------------------------------------------
1052 /// @brief This routine turn on/off HDMI Tx TMDS signal
1053 /// @param[in] bRB_Swap: R/B swap; bTMDS: TMDS flag
1054 /// @return None
1055 //------------------------------------------------------------------------------
MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap,MS_BOOL bTMDS)1056 void MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap, MS_BOOL bTMDS)
1057 {
1058 if(bRB_Swap) // R/B channel swap
1059 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, BIT13);
1060 else
1061 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, 0);
1062
1063 //reg_atop_en_data_out[13..15]: Enable data channel data output
1064 if (bTMDS == TRUE)
1065 {
1066 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
1067 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0xE800);
1068 //TBD: turn off tmds clock
1069
1070 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo
1071 MsOS_DelayTask(10);
1072 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000);
1073 }
1074 else
1075 {
1076 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
1077 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0x0000);
1078 //TBD: turn off tmds clock
1079 }
1080 }
1081
1082 //------------------------------------------------------------------------------
1083 /// @brief This routine turn on/off HDMI Tx video output
1084 /// @param[in] bVideo: Video flag; bCSC: CSC flag, b709format = BT.709-5
1085 /// @return None
1086 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo,MS_BOOL bCSC,MS_BOOL b709format)1087 void MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo, MS_BOOL bCSC, MS_BOOL b709format)
1088 {
1089 if (bVideo == TRUE)
1090 {
1091 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0, 0x0000); // disable test pattern
1092 }
1093 else
1094 {
1095 MS_U8 i = 0x00;
1096
1097 DBG_HDMITX(printf("MDrv_HDMITx_SetVideoOnOff: csc flag= %d \n", bCSC));
1098
1099 // enable test pattern
1100 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3A, 0x0000);
1101 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3B, 0x0000);
1102 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3C, 0x03FF); // whole-blue
1103 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0|BIT1, BIT0|BIT1);
1104
1105 for ( i = 0; i < 6; i++ )
1106 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3D + i, 0x0000);
1107 }
1108 }
1109
1110 //------------------------------------------------------------------------------
1111 /// @brief This routine sets video color formatt
1112 /// @param[in] bCSC: CSC flag, YUV422 12 bit, b709format = BT.709-5
1113 /// @return None
1114 //------------------------------------------------------------------------------
MHal_HDMITx_SetColorFormat(MS_BOOL bCSC,MS_BOOL bHdmi422b12,MS_BOOL b709format)1115 void MHal_HDMITx_SetColorFormat(MS_BOOL bCSC, MS_BOOL bHdmi422b12, MS_BOOL b709format)
1116 {
1117 if (bCSC) // YUV -> RGB
1118 {
1119 DBG_HDMITX(printf("YUV -> RGB \n"));
1120 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, BIT0); //bypass
1121 }
1122 else // bypass
1123 {
1124 DBG_HDMITX(printf("bypass YUV -> RGB \n"));
1125 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, 0x00); //bypass
1126 }
1127
1128 // YUV422 12 bits output
1129 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, bHdmi422b12 ? BIT15 : 0x00);
1130 }
1131
1132 //------------------------------------------------------------------------------
1133 /// @brief This routine get CSC capability
1134 /// @param[in]
1135 /// @return False : not support R2Y. Ture : ok.
1136 //------------------------------------------------------------------------------
MHal_HDMITx_CSC_Support_R2Y(void * pDatatIn)1137 MS_BOOL MHal_HDMITx_CSC_Support_R2Y(void* pDatatIn)
1138 {
1139 pDatatIn = pDatatIn;
1140 return HDMITX_CSC_SUPPORT_R2Y;
1141 }
1142
1143 //------------------------------------------------------------------------------
1144 /// @brief This routine sets color domain and color range transform
1145 /// @param[in]
1146 /// @return False : not support this command. Ture : ok.
1147 //------------------------------------------------------------------------------
MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor,MsHDMITX_VIDEO_COLOR_FORMAT outcolor,MsHDMITX_YCC_QUANT_RANGE inrange,MsHDMITX_YCC_QUANT_RANGE outrange)1148 MS_BOOL MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor, MsHDMITX_VIDEO_COLOR_FORMAT outcolor, MsHDMITX_YCC_QUANT_RANGE inrange, MsHDMITX_YCC_QUANT_RANGE outrange)
1149 {
1150 MS_BOOL bReturn = FALSE;
1151
1152 if(incolor == E_HDMITX_VIDEO_COLOR_RGB444)
1153 {
1154 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LR
1155 {
1156 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1157 { //LR -> LY
1158 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1159 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x020C);
1160 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E24);
1161 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD0);
1162 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1163 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1164 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1165 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F88);
1166 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E6C);
1167 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x020C);
1168 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1169 bReturn = TRUE;
1170 DBG_HDMITX(printf("LR->LY! \n"));
1171 }
1172 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1173 { //LR -> FY
1174 #if 1
1175 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1176 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x020C);
1177 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E24);
1178 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD0);
1179 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1180 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1181 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1182 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F88);
1183 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E6C);
1184 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x020C);
1185 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1186
1187 DBG_HDMITX(printf("Not Support This! Replace by LR -> LY\n"));
1188 DBG_HDMITX(printf("LR->FY! \n"));
1189 bReturn = FALSE;
1190 #else
1191 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0CB0);
1192 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0256);
1193 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1DE1);
1194 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FC9);
1195 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00FE);
1196 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0357);
1197 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0056);
1198 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F77);
1199 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E33);
1200 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0256);
1201 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1202 bReturn = TRUE;
1203 DBG_HDMITX(printf("LR->FY! \n"));
1204 #endif
1205 }
1206 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_FULL))
1207 { //LR -> FR
1208 #if 1
1209 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1210 DBG_HDMITX(printf("Not Support This! \n"));
1211 DBG_HDMITX(printf("LR->FR! \n"));
1212 bReturn = FALSE;
1213 #else
1214 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0C10);
1215 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1216 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1217 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1218 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1219 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1220 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1221 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1222 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1223 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1224 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1225 bReturn = TRUE;
1226 DBG_HDMITX(printf("LR->FR! \n"));
1227 #endif
1228 }
1229 else
1230 {
1231 DBG_HDMITX(printf("LR->LR! \n"));
1232 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1233 DBG_HDMITX(printf("In/Out Same Color! \n"));
1234 }
1235
1236 }
1237 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FR
1238 {
1239 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1240 { //FR -> LY
1241 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00E0);
1242 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x01C0);
1243 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E69);
1244 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD7);
1245 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00BA);
1246 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0273);
1247 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x003F);
1248 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F99);
1249 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1EA6);
1250 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x01C0);
1251 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1252 bReturn = TRUE;
1253 DBG_HDMITX(printf("FR->LY! \n"));
1254 }
1255 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1256 { //FR -> FY
1257 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1258 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0200);
1259 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E2F);
1260 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD1);
1261 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1262 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1263 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1264 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F8B);
1265 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E75);
1266 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0200);
1267 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1268 bReturn = TRUE;
1269 DBG_HDMITX(printf("FR->FY! \n"));
1270 }
1271 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1272 { //FR -> LR
1273 #if 1
1274 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1275 DBG_HDMITX(printf("Not Support This! \n"));
1276 DBG_HDMITX(printf("FR->LR! \n"));
1277 bReturn = FALSE;
1278 #else
1279 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x5040);
1280 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0381);
1281 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1282 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1283 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1284 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1285 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1286 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1287 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1288 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0381);
1289 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1290 bReturn = TRUE;
1291 DBG_HDMITX(printf("FR->LR! \n"));
1292 #endif
1293 }
1294 else
1295 {
1296 DBG_HDMITX(printf("FR->FR! \n"));
1297 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1298 DBG_HDMITX(printf("In/Out Same Color! \n"));
1299 }
1300 }
1301 else
1302 {
1303 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1304 DBG_HDMITX(printf("Not Support This! \n"));
1305 }
1306 }
1307 else if((incolor == E_HDMITX_VIDEO_COLOR_YUV444) || (incolor == E_HDMITX_VIDEO_COLOR_YUV422))
1308 {
1309 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LY
1310 {
1311 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1312 {//LY->FR
1313 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x001A);
1314 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0731);
1315 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x04AC);
1316 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1317 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1DDD);
1318 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1319 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F25);
1320 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1321 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x04AC);
1322 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0879);
1323 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1324 bReturn = TRUE;
1325 DBG_HDMITX(printf("LY->FR! \n"));
1326 }
1327 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1328 {//LY->LR
1329 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1330 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0629);
1331 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1332 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1333 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E2B);
1334 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1335 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F44);
1336 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1337 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1338 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0742);
1339 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1340 bReturn = TRUE;
1341 DBG_HDMITX(printf("May over range! \n"));
1342 DBG_HDMITX(printf("LY->LR! \n"));
1343 }
1344 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1345 {//LY->FY
1346 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00BA);
1347 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0491);
1348 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1349 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1350 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1351 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1352 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1353 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1354 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1355 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0491);
1356 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1357 bReturn = TRUE;
1358 DBG_HDMITX(printf("LY->FY! \n"));
1359 }
1360 else
1361 {
1362 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1363 DBG_HDMITX(printf("In/Out Same Color! \n"));
1364 DBG_HDMITX(printf("LY->LY! \n"));
1365 }
1366
1367 }
1368 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FY
1369 {
1370 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1371 {//FY->FR
1372 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1373 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x064D);
1374 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1375 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1376 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E21);
1377 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1378 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F40);
1379 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1380 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1381 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x076C);
1382 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1383 bReturn = TRUE;
1384 DBG_HDMITX(printf("FY->FR! \n"));
1385 }
1386 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1387 {//FY->LR
1388 #if 1
1389 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1390 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x064D);
1391 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1392 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1393 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E21);
1394 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1395 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F40);
1396 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1397 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1398 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x076C);
1399 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1400
1401 DBG_HDMITX(printf("Not Support This! Replace by FY -> FR\n"));
1402 DBG_HDMITX(printf("FY->LR! \n"));
1403 bReturn = FALSE;
1404 #else
1405 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x504A);
1406 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0565);
1407 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x036D);
1408 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1409 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E66);
1410 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1411 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F5C);
1412 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1413 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x036D);
1414 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x065B);
1415 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1416 bReturn = TRUE;
1417 DBG_HDMITX(printf("FY->LR! \n"));
1418 #endif
1419 }
1420 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1421 {//FY->LY
1422 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00EA);
1423 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1424 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1425 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1426 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1427 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1428 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1429 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1430 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1431 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1432 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1433 bReturn = TRUE;
1434 DBG_HDMITX(printf("FY->LY! \n"));
1435 }
1436 else
1437 {
1438 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1439 DBG_HDMITX(printf("In/Out Same Color! \n"));
1440 DBG_HDMITX(printf("FY->FY! \n"));
1441 }
1442 }
1443 else
1444 {
1445 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1446 DBG_HDMITX(printf("Not Support This! \n"));
1447 }
1448 }
1449 else
1450 {
1451 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1452 DBG_HDMITX(printf("Not Support This! \n"));
1453 }
1454
1455 //if((bReturn == TRUE) && (outcolor == E_HDMITX_VIDEO_COLOR_YUV422))
1456 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, (outcolor == E_HDMITX_VIDEO_COLOR_YUV422) ? BIT15 : 0);
1457
1458 return bReturn;
1459 }
1460
1461 //------------------------------------------------------------------------------
1462 /// @brief This routine will set or stop all HDMI packet generation
1463 /// @param[in] bflag True: Enable packet gen, False : Disable packet gen
1464 /// @return None
1465 //------------------------------------------------------------------------------
MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)1466 void MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)
1467 {
1468 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT2, bflag ? BIT2:0);
1469 }
1470
1471 //------------------------------------------------------------------------------
1472 /// @brief This routine sets HDMI/DVI mode
1473 /// @param[in] bflag
1474 /// @return None
1475 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDMImode(MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)1476 void MHal_HDMITx_SetHDMImode(MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)
1477 {
1478 MS_U8 ucRegVal = 0x00;
1479
1480 DBG_HDMITX(printf("[%s][%d]HDMI mode = %d, Color Depth = %d \n", __FUNCTION__, __LINE__, bflag, bflag));
1481
1482 if (bflag) // HDMI mode
1483 {
1484 switch(cd_val)
1485 {
1486 case E_HDMITX_VIDEO_CD_NoID:
1487 case E_HDMITX_VIDEO_CD_24Bits:
1488 default:
1489 ucRegVal = 0x00;
1490 break;
1491
1492 case E_HDMITX_VIDEO_CD_30Bits:
1493 ucRegVal = 0x40;
1494 break;
1495
1496 case E_HDMITX_VIDEO_CD_36Bits:
1497 ucRegVal = 0x80;
1498 break;
1499
1500 case E_HDMITX_VIDEO_CD_48Bits:
1501 ucRegVal = 0xC0;
1502 break;
1503 }
1504
1505 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, ucRegVal|BIT2); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1506 }
1507 else // DVI
1508 {
1509 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, BIT0); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1510 }
1511 }
1512
1513
1514 //------------------------------------------------------------------------------
1515 /// @brief This routine sets audio on/off
1516 /// @param[in] bflag
1517 /// @return None
1518 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)1519 void MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)
1520 {
1521 MS_U8 num;
1522
1523 if(bflag) // audio on
1524 {
1525 num = sizeof(HDMITxAudioOnTbl)/sizeof(MSTHDMITX_REG_TYPE);
1526 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOnTbl, num);
1527 }
1528 else // audio off
1529 {
1530 num = sizeof(HDMITxAudioOffTbl)/sizeof(MSTHDMITX_REG_TYPE);
1531 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOffTbl, num);
1532 }
1533 }
1534
1535 //------------------------------------------------------------------------------
1536 /// @brief This routine sets audio sampling freq.
1537 /// @return None
1538 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,MsHDMITX_AUDIO_CHANNEL_COUNT achidx,MsHDMITX_AUDIO_CODING_TYPE actidx)1539 void MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,
1540 MsHDMITX_AUDIO_CHANNEL_COUNT achidx, MsHDMITX_AUDIO_CODING_TYPE actidx
1541 )
1542 {
1543 // HDMI audio channel setting
1544 if(achidx == E_HDMITX_AUDIO_CH_2) // 2 channels
1545 {
1546 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5]: audio FIFO depth ch1234, [4]=1'b0: 2 channels
1547 }
1548 else // 8 channels
1549 {
1550 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels
1551 }
1552
1553 // Audio channel status
1554 #if 1 //NOTE:: kano: move channel status from address 0x00 to address 0x0A
1555 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1556 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[afidx].CH_Status3 << 8) | (achidx << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
1557 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
1558 #else
1559 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_00, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1560 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_01, 0);
1561 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_02, (achidx<<4)); // [7:4]: audio channel count
1562 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS3_03, TxAudioFreqTbl[afidx].CH_Status3); // [3:0]: audio sampling frequncy
1563 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS4_04, 0);
1564 #endif
1565 // ACR N code
1566 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_2_06, 0x0F00, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000));
1567 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_3_07, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1568
1569 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_61, 0x000F, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000) >> 8);
1570 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_60, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1571 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x0100, 0x0100); //enable cts * 2
1572 }
1573
1574 //------------------------------------------------------------------------------
1575 /// @brief This routine sets audio source format.
1576 /// @return None
1577 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)1578 void MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)
1579 {
1580 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8);
1581 }
1582
1583 //------------------------------------------------------------------------------
1584 /// @brief This routine Get Audio CTS value
1585 /// @return CTS
1586 //------------------------------------------------------------------------------
MHal_HDMITx_GetAudioCTS(void)1587 MS_U32 MHal_HDMITx_GetAudioCTS(void)
1588 {
1589 MS_U32 ret;
1590
1591 ret = ((MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_2_06) & 0x000F) << 16) | MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_1_05);
1592 return ret;
1593 }
1594
1595 //------------------------------------------------------------------------------
1596 /// @brief This routine Mute Audio FIFO
1597 /// @param[in] bflag: True: mute audio, False: unmute audio
1598 /// @return None
1599 //------------------------------------------------------------------------------
MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)1600 void MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)
1601 {
1602 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag);
1603 }
1604
1605 //------------------------------------------------------------------------------
1606 /// @brief This routine sets HDMI Tx HDCP encryption On/Off
1607 /// @return None
1608 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag,MS_BOOL hdmi_flag)1609 void MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag, MS_BOOL hdmi_flag)
1610 {
1611 if(hdcp_flag) // HDCP on
1612 {
1613 if (hdmi_flag) // HDMI EESS
1614 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400);
1615 else // DVI OESS
1616 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000);
1617 // HDCP encryption
1618 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008);
1619 }
1620 else // HDCP off
1621 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000);
1622 }
1623
1624 //------------------------------------------------------------------------------
1625 /// @brief This routine calculate check sum of infoframes.
1626 /// @param[in] packet_type packet type
1627 /// @return checksum
1628 //------------------------------------------------------------------------------
MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)1629 MS_U8 MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)
1630 {
1631 MS_U8 ucSumVal = 0;
1632 MS_U8 i = 0;
1633 MS_U8 j = 0;
1634 MS_U16 wRegVal = 0;
1635
1636 switch (packet_type)
1637 {
1638 case E_HDMITX_VS_INFOFRAME:
1639 ucSumVal += (E_HDMITX_VS_INFOFRAME + HDMITX_VS_INFO_PKT_VER + HDMITX_VS_INFO_PKT_LEN);
1640
1641 for ( i = 0; i < (HDMITX_VS_INFO_PKT_LEN + 1) >> 1; i++ )
1642 {
1643 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_VS_1_27 + i);
1644
1645 for ( j = 0; j < 2; j++ )
1646 {
1647 if ((i == 13) && (j==1))
1648 {
1649 ucSumVal += 0x00;
1650 }
1651 else
1652 {
1653 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1654 }
1655 }
1656 }
1657 break;
1658
1659 case E_HDMITX_AVI_INFOFRAME:
1660 ucSumVal += (E_HDMITX_AVI_INFOFRAME + HDMITX_AVI_INFO_PKT_VER + HDMITX_AVI_INFO_PKT_LEN);
1661
1662 for ( i = 0; i < ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1); i++ )
1663 {
1664 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + i);
1665
1666 for ( j = 0; j < 2; j++ )
1667 {
1668 if ((i == 1) && (j == 0)) // SC[1:0]
1669 {
1670 ucSumVal += (HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)(wRegVal & 0x00FF) & 0x03);
1671 }
1672 else if ((i == 1) && (j == 1)) // VIC[6:0]
1673 {
1674 ucSumVal += ((HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)((wRegVal & 0xFF00) >> 8) & 0x7F) : 0x00);
1675 }
1676 else if ((i == 2) && (j == 0)) // PR[3:0]
1677 {
1678 ucSumVal += (MS_U8)(wRegVal & 0x00FF); //bit 4:7 used for HDR; //ucSumVal += ((MS_U8)(wRegVal & 0x00FF) & 0x0F);
1679 }
1680 #if 0 //not resevered byte anymore; should be counted
1681 else if ((i == 2) && (j == 1)) // reserved
1682 {
1683 ucSumVal += 0x00;
1684 }
1685 #endif
1686 else if (( i == ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1) - 1)&&(j == 1))
1687 {
1688 ucSumVal += 0x00;
1689 }
1690 else
1691 {
1692 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1693 }
1694 }
1695 }
1696 break;
1697
1698 case E_HDMITX_SPD_INFOFRAME:
1699 ucSumVal += (E_HDMITX_SPD_INFOFRAME + HDMITX_SPD_INFO_PKT_VER + HDMITX_SPD_INFO_PKT_LEN);
1700
1701 for ( i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN+ 1) >> 1); i++ )
1702 {
1703 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_SPD_1_15 + i);
1704
1705 for ( j = 0; j < 2; j++ )
1706 {
1707 if ((i == 12) && (j == 0))
1708 {
1709 ucSumVal += (MS_U8)(wRegVal & 0x00FF);
1710 }
1711 else if ((i == 12) && (j == 1)) //reserved
1712 {
1713 ucSumVal += 0x00;
1714 }
1715 else
1716 {
1717 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1718 }
1719 }
1720 }
1721 break;
1722
1723 case E_HDMITX_AUDIO_INFOFRAME:
1724 ucSumVal += (E_HDMITX_AUDIO_INFOFRAME + HDMITX_AUD_INFO_PKT_VER + HDMITX_AUD_INFO_PKT_LEN);
1725
1726 for ( i = 0; i < (((HDMITX_AUD_INFO_PKT_LEN >> 1) + 1) >> 1); i++ )
1727 {
1728 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AUD_1_11 + i);
1729
1730 if (i == 1)
1731 {
1732 for ( j = 0; j < 2; j++ )
1733 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1734 }
1735
1736 if (i == 0)
1737 {
1738 for ( j = 0; j < 2; j++ )
1739 ucSumVal += ( (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xF7) : (((MS_U8)(wRegVal & 0xFF00) >> 8) & 0x1F));
1740 }
1741
1742 if (i == 2)
1743 {
1744 for ( j = 0; j < 2; j++ )
1745 ucSumVal += ((j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xFB) : 0x00);
1746 }
1747 }
1748 break;
1749
1750 case E_HDMITX_MPEG_INFOFRAME:
1751 //TBD
1752 break;
1753
1754 case E_HDMITX_HDR_INFOFRAME:
1755 {
1756 MS_U8 u8PktLen = 0x00;
1757
1758 u8PktLen = (MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0xFF00) >> 8;
1759 ucSumVal += (E_HDMITX_HDR_INFOFRAME + (MS_U8)(MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0x00FF) + u8PktLen);
1760
1761 for ( i = 0; i < ((u8PktLen + 1) >> 1); i++ )
1762 {
1763 wRegVal = MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_10 + i);
1764
1765 for ( j = 0; j < 2; j++ )
1766 {
1767 if ((i == 0x0D) && (j % 2 == 0x00))
1768 ucSumVal += (j % 2 == 0) ? (MS_U8)(wRegVal & 0x00FF) : 0x00;
1769 else
1770 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1771 }
1772 }
1773 }
1774 break;
1775
1776 default:
1777 break;
1778 }
1779
1780 return (MS_U8)((~ucSumVal) + 0x01);
1781
1782 }
1783
1784 //------------------------------------------------------------------------------
1785 /// @brief This routine sets video output mode (color/repetition/regen)
1786 /// @param[in] idx: gHDMITxInfo.output_video_timing
1787 /// @return None
1788 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx,MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val,MsHDMITX_ANALOG_TUNING * pInfo,MS_U8 ubSSCEn)1789 void MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx, MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val, MsHDMITX_ANALOG_TUNING *pInfo, MS_U8 ubSSCEn)
1790 {
1791 //MS_U16 reg_value=0;
1792 MS_U8 ucCDIdx = 0;
1793 MS_U16 wHfront = 0;
1794 MS_U16 wVfront = 0;
1795 MS_BOOL bIsHDMI20 = FALSE;
1796 MS_BOOL bIs420Fmt = FALSE;
1797 MS_BOOL bIsRPMode = FALSE;
1798 MS_U32 uiTMDSCLK = 0;
1799
1800 //wilson@kano:TBD
1801 printf("video idx = 0x%X, color depth = 0x%X\r\n", idx, cd_val);
1802 // Deep color FIFO reset
1803 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, BIT10);
1804 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, 0);
1805 MsOS_DelayTask(10);
1806
1807 // Interlace mode
1808 if (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE)
1809 {
1810 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x005F);
1811 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x4000); //reg_interlace_mode_sel
1812 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2
1813 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0004); // PG interlace enable
1814 }
1815 else
1816 {
1817 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x004E);
1818 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x0000); //reg_interlace_mode_sel
1819 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0000); //video clock div 2
1820 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0000); // PG interlace disable
1821 }
1822
1823 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt != E_HDMITX_VIDEO_COLOR_YUV420) &&
1824 (
1825 (idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || \
1826 (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz) || \
1827 (
1828 (
1829 (idx == E_HDMITX_RES_1280x1470p_60Hz) || \
1830 (idx == E_HDMITX_RES_3840x2160p_24Hz) || \
1831 (idx == E_HDMITX_RES_3840x2160p_25Hz) || \
1832 (idx == E_HDMITX_RES_3840x2160p_30Hz) || \
1833 (idx == E_HDMITX_RES_4096x2160p_24Hz) || \
1834 (idx == E_HDMITX_RES_4096x2160p_25Hz) || \
1835 (idx == E_HDMITX_RES_4096x2160p_30Hz)
1836
1837 ) &&
1838 (
1839 (cd_val != E_HDMITX_VIDEO_CD_24Bits) && (cd_val != E_HDMITX_VIDEO_CD_NoID)
1840 )
1841 )
1842 ))
1843 bIsHDMI20 = TRUE;
1844
1845 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420) &&
1846 ((idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz)) &&
1847 (cd_val != E_HDMITX_VIDEO_CD_24Bits) && (cd_val != E_HDMITX_VIDEO_CD_NoID))
1848 bIsHDMI20 = TRUE;
1849
1850 //for 2.0
1851 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0100, bIsHDMI20 ? 0x0100 : 0x00);
1852 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_52, BIT0, bIsHDMI20 ? BIT0 : 0x00);
1853
1854 //scdc
1855 if (bIsHDMI20 == TRUE)
1856 Mhal_HDMITx_SCDCSetTmdsConfig(TRUE, TRUE);
1857 else
1858 Mhal_HDMITx_SCDCSetTmdsConfig(FALSE, FALSE);
1859
1860 if (gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420)
1861 {
1862 switch (idx)
1863 {
1864 case E_HDMITX_RES_3840x2160p_50Hz:
1865 idx = E_HDMITX_RES_3840x2160p_25Hz;
1866 break;
1867
1868 case E_HDMITX_RES_3840x2160p_60Hz:
1869 idx = E_HDMITX_RES_3840x2160p_30Hz;
1870 break;
1871
1872 case E_HDMITX_RES_4096x2160p_50Hz:
1873 idx = E_HDMITX_RES_4096x2160p_25Hz;
1874 break;
1875
1876 case E_HDMITX_RES_4096x2160p_60Hz:
1877 idx = E_HDMITX_RES_4096x2160p_30Hz;
1878 break;
1879
1880 default:
1881 printf("[HDMITX] Invalid Combination of Color Format & Video Timing, Keep Origional Timing Setting!!\r\n");
1882 break;
1883 }
1884
1885 bIs420Fmt = TRUE;
1886 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2 for 420
1887 }
1888
1889 if((idx == E_HDMITX_RES_720x480i) || (idx == E_HDMITX_RES_720x576i))
1890 {
1891 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x008B);
1892
1893 bIsRPMode = TRUE;
1894 }
1895 else
1896 {
1897 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x00AC);
1898
1899 bIsRPMode = FALSE;
1900 }
1901
1902 //enable H, VSync regen
1903 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x8001, 0x8001);
1904 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0002, HDMITxVideoModeTbl[idx].h_polarity ? 0x0002 : 0x0000);
1905 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0004, HDMITxVideoModeTbl[idx].v_polarity ? 0x0004 : 0x0000);
1906
1907 ucCDIdx = (cd_val == 0)? 0x00 : (cd_val - 4);
1908
1909 //deep color setting
1910 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00C0, ucCDIdx << 6);
1911
1912 //HDMITx phy clock
1913 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0xCC0C, 0x0000);
1914
1915 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
1916
1917 //sythesizer setting
1918 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, (MS_U16)(HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0000FFFF));
1919 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x0FFF, (MS_U16)((HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0FFF0000) >> 16));
1920
1921 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1003, 0x0000);
1922 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_26, 0x0100, 0x0000);
1923
1924 //atop
1925 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x0003, HDMITxVideoAtopSetting[ucCDIdx][idx].MUX_DIVSEL_POST);
1926 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0xC000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 14);
1927 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x3000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_PIXEL << 12);
1928
1929 #if 0
1930 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
1931 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
1932 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012);
1933 #else //RD suggestion
1934 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, 0x0000);
1935 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, 0x0000);
1936 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, 0x0000);
1937 #endif
1938
1939 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
1940 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
1941 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012);
1942
1943 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x000F, HDMITxVideoAtopSetting[ucCDIdx][idx].PD_RT);
1944
1945
1946 // Timing regeneration
1947 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT10|BIT13, 0x0000/*BIT10|BIT13*/); // 0: delay from DE end; 1: delay from end of h, v sync
1948
1949 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_02, HDMITxVideoModeTbl[idx].vs_width);
1950 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_05, HDMITxVideoModeTbl[idx].vs_delayline);
1951 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_06, HDMITxVideoModeTbl[idx].vs_delaypixel);
1952 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_07, HDMITxVideoModeTbl[idx].hs_width >> (bIs420Fmt ? 0x01 : 0x00));
1953 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_0A, HDMITxVideoModeTbl[idx].hs_delay >> (bIs420Fmt ? 0x01 : 0x00));
1954
1955 //for PG
1956 wHfront = HDMITxVideoModeTbl[idx].hs_delay;
1957 wVfront = HDMITxVideoModeTbl[idx].vs_delayline;
1958
1959 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0003, 0x0003);
1960 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hde_width/4 - 1) : (HDMITxVideoModeTbl[idx].hde_width/2 - 1));
1961 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, (bIs420Fmt||bIsRPMode) ?
1962 ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/4 - 1) : ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/2 - 1));
1963 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (bIs420Fmt||bIsRPMode) ? (wHfront/4 - 1) : (wHfront/2 - 1));
1964 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hs_width/4 - 1) : (HDMITxVideoModeTbl[idx].hs_width/2 - 1));
1965
1966 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_35, HDMITxVideoModeTbl[idx].vde_width - 1);
1967 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_36, (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) ?
1968 ((HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width)/2 - 1) : (HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width - 1));
1969 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_37, wVfront - 1);
1970 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_38, HDMITxVideoModeTbl[idx].vs_width - 1);
1971
1972 MHal_HDMITx_EnableSSC(ubSSCEn, uiTMDSCLK);
1973
1974 // fifo reset
1975 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0x0008);
1976 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0);
1977 }
1978
1979 //------------------------------------------------------------------------------
1980 /// @brief This routine will power on or off HDMITx clock (power saving)
1981 /// @param[in] bEnable: TRUE/FALSE
1982 /// @return None
1983 //------------------------------------------------------------------------------
MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)1984 void MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)
1985 {
1986 if (bEnable)
1987 {
1988 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, 0);
1989 }
1990 else
1991 {
1992 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, BIT0);
1993 }
1994 }
1995
1996
MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq,MS_BOOL bflag)1997 MS_BOOL MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq, MS_BOOL bflag)
1998 {
1999 //wilson@kano:TBD
2000 #if 0
2001 return FALSE;
2002 #else
2003 printf("[HDMITx] Bypass Mode = 0x%d\r\n", bflag);
2004 if (bflag == TRUE)
2005 {
2006 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, BIT0); //reg_atop_en_clko_vcodiv8_syn
2007
2008 //Note: change frequency tolerance if need
2009 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2010 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2011 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2012 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2013 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2014 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2015 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //change 250Mhz -> 297Mhz
2016
2017 //Enable Fifo and select input source
2018 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1919); //selct clock from Rx;
2019
2020 #if 0
2021 if (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7A) & 0x00C0) //for HDMI 2.0 timing bypass mode
2022 {
2023 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, BIT0); //tmds clock div 2;
2024 }
2025 #endif
2026
2027 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x000E, 0x0004); //[1:0]: Lane 0 to fifo; [2]: enable
2028 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x000E, 0x0005); //[1:0]: Lane 1 to fifo; [2]: enable
2029 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x000E, 0x0006); //[1:0]: Lane 2 to fifo; [2]: enable
2030 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x000E, 0x0007); //[1:0]: Lane 3 to fifo; [2]: enable
2031
2032 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1000, 0x1000); //bit repetition HW mode;
2033
2034 //synthesizer setting //TBD
2035 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x0001, 0x0001);
2036 //ssc_set = 0x140000
2037 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, 0x0000); //ssc_set [15..0]
2038 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x00FF, 0x0014);//ssc_set [7..0]
2039
2040 #if 0 //with SSC clock
2041 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, ssc_step);
2042 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3000, ssc_span);
2043 #else //without SSC clock
2044 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, 0x0000);
2045 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3FFF, 0x0000);
2046 #endif
2047
2048 //ATOP setting
2049 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00); //[9]:en_clk_pixel;[11]:en_clk_tmds;[13..15]:en_data_out
2050 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0x0000); //[11..0]: disable power down;[15:12]:pre-emphasis
2051 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x007F, 0x000F); //[3:0]:rterm turn off;[6:4]:disable power down
2052 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x2001); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2053 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0200); //[9] hdmi20 hw config mode;
2054 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7E, 0x0200, 0x0200); //[9]: freq range tolerance up direction;
2055 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_60, 0x0001, 0x0001); //[0]: freq range reset follow rx big change;
2056 }
2057 else
2058 {
2059 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2060 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2061 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2062 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2063 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2064 }
2065
2066 return TRUE;
2067
2068 #endif
2069 }
2070
2071
2072 /// @brief This routine will disable TMDS clock, data, and DDC... bypass mode
2073 /// @return None
2074 //------------------------------------------------------------------------------
MHal_HDMITx_Disable_RxBypass(void)2075 MS_BOOL MHal_HDMITx_Disable_RxBypass(void)
2076 {
2077 #if 0
2078 return FALSE;
2079 #else
2080 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2081 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2082 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2083 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2084 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2085
2086 return TRUE;
2087 #endif
2088 }
2089
2090
2091 //------------------------------------------------------------------------------
2092 /// @brief This routine will set GPIO pin for HPD
2093 /// @param[in] u8pin: GPIO0 ~ 12
2094 /// @return None
2095 //------------------------------------------------------------------------------
MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)2096 void MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)
2097 {
2098 printf("_gHPDGpioPin = 0x%X\r\n", u8pin);
2099 _gHPDGpioPin = u8pin;
2100 }
2101
2102 //------------------------------------------------------------------------------
2103 /// @brief This routine return CHIP capability of DVI mode
2104 /// @return TRUE, FALSE
2105 //------------------------------------------------------------------------------
MHal_HDMITx_IsSupportDVIMode(void)2106 MS_BOOL MHal_HDMITx_IsSupportDVIMode(void)
2107 {
2108 return TRUE;
2109 }
2110
2111 // ************* For customer NDS **************//
2112
MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process,MsHDMITX_AVI_CONTENT_TYPE content_type,MS_U16 * data)2113 void MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process, MsHDMITX_AVI_CONTENT_TYPE content_type, MS_U16 *data)
2114 {
2115 MS_U16 tmp_value=0;
2116
2117 if (IS_STOP_PKT(packet_process)) // Stop sending packet
2118 {
2119 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000); // Stop AVI packet
2120 }
2121 else
2122 {
2123 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0080, 0x80); // EIA version 2
2124 switch(content_type)
2125 {
2126 case E_HDMITX_AVI_PIXEL_FROMAT:
2127 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0060, *data);
2128 break;
2129 case E_HDMITX_AVI_ASPECT_RATIO:
2130 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x3F1F, *data);
2131 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0003, *(data+1));
2132 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_4_0C, 0xFFFF, *(data+2));
2133 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_5_0D, 0xFFFF, *(data+3));
2134 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_6_0E, 0xFFFF, *(data+4));
2135 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0xFFFF, *(data+5));
2136 break;
2137 case E_HDMITX_AVI_COLORIMETRY:
2138 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xC000, *data);
2139 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0030, *(data+1));
2140 break;
2141 default:
2142 break;
2143 }
2144
2145 tmp_value = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME); // Checksum
2146 // cyclic packet
2147 if (IS_CYCLIC_PKT(packet_process))
2148 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ( (tmp_value<<8) | (HDMITX_PACKET_AVI_FCNT<<3) | 0x0005)); // send AVI packet
2149 // single packet
2150 else
2151 {
2152 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (tmp_value<<8) | 0x0001);
2153 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1<<E_HDMITX_ACT_AVI_CMD);
2154 }
2155 }
2156 }
2157
2158 //wilson@kano
2159 //**************************************************************************
2160 // [Function Name]:
2161 // MHal_HDMITx_SetGCPParameter()
2162 // [Description]:
2163 // setting General Control packet attribute
2164 // [Arguments]:
2165 // [stGC_PktPara] stPktPara
2166 // [Return]:
2167 // void
2168 //
2169 //**************************************************************************
MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)2170 void MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)
2171 {
2172 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enAVMute = stPktPara.enAVMute;
2173 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enColorDepInfo = stPktPara.enColorDepInfo;
2174 }
2175
2176 //**************************************************************************
2177 // [Function Name]:
2178 // MHal_HDMITx_SetPktAttribute()
2179 // [Description]:
2180 // configure settings to corresponding packet
2181 // [Arguments]:
2182 // [MsHDMITX_PACKET_TYPE] enPktType
2183 // [MS_BOOL] bEnUserDef
2184 // [MS_U8] u8FrmCntNum
2185 // [MsHDMITX_PACKET_PROCESS] enPktCtrl
2186 // [Return]:
2187 // void
2188 //
2189 //**************************************************************************
MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType,MS_BOOL bEnUserDef,MS_U8 u8FrmCntNum,MsHDMITX_PACKET_PROCESS enPktCtrl)2190 void MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType, MS_BOOL bEnUserDef, MS_U8 u8FrmCntNum, MsHDMITX_PACKET_PROCESS enPktCtrl)
2191 {
2192 if (enPktType & 0x80) //infoframe packet type
2193 {
2194 gbInfoFrmPktList[enPktType & (~0x80)].EnableUserDef = bEnUserDef;
2195 gbInfoFrmPktList[enPktType & (~0x80)].FrmCntNum = u8FrmCntNum;
2196 gbInfoFrmPktList[enPktType & (~0x80)].enPktCtrl = enPktCtrl;
2197 }
2198 else
2199 {
2200 gbGeneralPktList[enPktType].EnableUserDef = bEnUserDef;
2201 gbGeneralPktList[enPktType].FrmCntNum = u8FrmCntNum;
2202 gbGeneralPktList[enPktType].enPktCtrl = enPktCtrl;
2203 }
2204 }
2205
2206 //**************************************************************************
2207 // [Function Name]:
2208 // MHal_HDMITx_SetAVIInfoParameter()
2209 // [Description]:
2210 // Assign content to AVI Infoframe packet
2211 // [Arguments]:
2212 // [stAVIInfo_PktPara] stPktPara
2213 // [Return]:
2214 // void
2215 //
2216 //**************************************************************************
MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)2217 void MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)
2218 {
2219 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.A0Value = stPktPara.A0Value;
2220 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enableAFDoverWrite = stPktPara.enableAFDoverWrite;
2221 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorFmt = stPktPara.enColorFmt;
2222 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enExtColorimetry = stPktPara.enExtColorimetry;
2223 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enYCCQuantRange = stPktPara.enYCCQuantRange;
2224 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enVidTiming = stPktPara.enVidTiming;
2225 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAFDRatio = stPktPara.enAFDRatio;
2226 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enScanInfo = stPktPara.enScanInfo;
2227 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAspectRatio = stPktPara.enAspectRatio;
2228 }
2229
2230 //**************************************************************************
2231 // [Function Name]:
2232 // MHal_HDMITx_SetVSInfoParameter()
2233 // [Description]:
2234 // Assign content to VendorSpecific Infoframe packet
2235 // [Arguments]:
2236 // [stVSInfo_PktPara] stPketPara
2237 // [Return]:
2238 // void
2239 //
2240 //**************************************************************************
MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)2241 void MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)
2242 {
2243 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en3DStruct = stPktPara.en3DStruct;
2244 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en4k2kVIC = stPktPara.en4k2kVIC;
2245 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.enVSFmt = stPktPara.enVSFmt;
2246 }
2247
2248 //**************************************************************************
2249 // [Function Name]:
2250 // MHal_HDMITx_SetVSInfoParameter()
2251 // [Description]:
2252 // Assign content to VendorSpecific Infoframe packet
2253 // [Arguments]:
2254 // [stVSInfo_PktPara] stPketPara
2255 // [Return]:
2256 // void
2257 //
2258 //**************************************************************************
MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)2259 void MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)
2260 {
2261 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudChCnt = stPktPara.enAudChCnt;
2262 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudType = stPktPara.enAudType;
2263 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudFreq = stPktPara.enAudFreq;
2264 }
2265
2266 //**************************************************************************
2267 // [Function Name]:
2268 // MHal_HDMITx_SendPacket()
2269 // [Description]:
2270 // configure packet content and process according to user define or defalut setting
2271 // [Arguments]:
2272 // [MsHDMITX_PACKET_TYPE] enPktType
2273 // [Return]:
2274 // void
2275 //
2276 //**************************************************************************
MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType,MsHDMITX_PACKET_PROCESS packet_process)2277 void MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType, MsHDMITX_PACKET_PROCESS packet_process)
2278 {
2279 if (enPktType & 0x80) //info frame packet
2280 {
2281 MS_U8 ucInfoPktType = enPktType & (~0x80);
2282 MS_U8 ucChkSum = 0;
2283
2284 gbInfoFrmPktList[ucInfoPktType].enPktCtrl = packet_process;
2285
2286 switch (enPktType)
2287 {
2288 case E_HDMITX_VS_INFOFRAME:
2289 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2290 {
2291 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, 0x0005, 0x0000);
2292 }
2293 else
2294 {
2295 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2296 {
2297 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2298
2299 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2300 {
2301 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2302 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2303 }
2304 else
2305 {
2306 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2307 }
2308 }
2309 else
2310 {
2311 //fill IEEE HDMI tag
2312 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27, 0xFFFF, 0x0C03);
2313
2314 //check content
2315 if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_3D)
2316 {
2317 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_3D << 13); // video format
2318 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en3DStruct) << 4); // 3D structure
2319 }
2320 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_4k_2k)
2321 {
2322 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_4k_2k << 13); // video format
2323 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en4k2kVIC)); // 4k2k vic
2324 }
2325 else
2326 {
2327 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, 0); // video format
2328 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, 0);
2329 }
2330
2331 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2332
2333 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2334 {
2335 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2336 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2337 }
2338 else
2339 {
2340 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum << 8) | (HDMITX_PACKET_VS_FCNT << 3) | 0x0005));
2341 }
2342 }
2343 }
2344 break;
2345
2346 case E_HDMITX_AVI_INFOFRAME:
2347 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2348 {
2349 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000);
2350 }
2351 else
2352 {
2353 MS_U8 ucPktVal = 0;
2354
2355 //Y2, Y1, Y0: RGB, YCbCr 422, 444, 420
2356 ucPktVal = (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt << 5);// | 0x10;
2357 //A0 field
2358 ucPktVal |= ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.A0Value == 0x01) ? 0x10 : 0x00);
2359 //S1, S0 field
2360 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enScanInfo);
2361
2362 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x00FF, (MS_U16)ucPktVal); //MDrv_WriteByte(REG_HDMITX_09_L, ucPktVal);
2363
2364 //C1, C0, M1, M0
2365 if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2366 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p))
2367 {
2368 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2369 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio << 4);
2370 }
2371 else
2372 {
2373 //HD timing is always 16:9
2374 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2375 }
2376
2377 //R3, R2, R1, R0: active porting aspect ration
2378 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enableAFDoverWrite == TRUE)
2379 {
2380 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAFDRatio & 0x0F);
2381 }
2382
2383 ucPktVal |= ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry == 0) ? 0 : 0xC0; //set [C1, C0] = [1, 1]
2384 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xFF00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_09_H, ucPktVal);
2385
2386 //EC0, EC1, EC2
2387 ucPktVal = (MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry;
2388 ucPktVal = (ucPktVal > 6) ? 6 : ucPktVal; //BT2020 RGB & BT2020 YCbCr share same value 6; 7 is reserved;
2389 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0070, ucPktVal << 4); //MDrv_WriteByteMask(REG_HDMITX_0A_L, ucPktVal << 4, 0x70);
2390
2391 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_RGB444)
2392 {
2393 //Q1, Q0
2394 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2395 {
2396 ucPktVal = 1;
2397 }
2398 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2399 {
2400 ucPktVal = 2;
2401 }
2402 else
2403 {
2404 ucPktVal = 0;
2405 }
2406
2407 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, ucPktVal << 2);
2408 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, 0x00);
2409 }
2410 else
2411 {
2412 //YQ1, YQ0
2413 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2414 {
2415 ucPktVal = 0;
2416 }
2417 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2418 {
2419 ucPktVal = 1;
2420 }
2421 else
2422 {
2423 ucPktVal = 3;
2424 }
2425
2426 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, 0x00);
2427 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, ucPktVal << 6);
2428 }
2429
2430 //VIC code: VIC code shoud +1 if aspect ration is 16:9
2431 ucPktVal = HDMITX_AviVicTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2432
2433 if (((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2434 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p)) &&
2435 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_16_9))
2436 {
2437 ucPktVal += 1;
2438 }
2439 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_21_9)
2440 {
2441 MS_U8 AR21_9MappingTbl[14][2] = {
2442 {60, 65},
2443 {61, 66},
2444 {62, 67},
2445 {19, 68},
2446 { 4, 69},
2447 {41, 70},
2448 {47, 71},
2449 {32, 72},
2450 {33, 73},
2451 {34, 74},
2452 {31, 75},
2453 {16, 76},
2454 {64, 77},
2455 {63, 78}
2456 };
2457
2458 if ((ucPktVal >= 93) && (ucPktVal <= 97))//3840*2160p@24 ~ 3840*2160@60
2459 {
2460 ucPktVal += 10;
2461 }
2462 else if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_3840x2160p_24Hz) &&\
2463 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_3840x2160p_30Hz))
2464 {
2465 ucPktVal += (103 + (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming - E_HDMITX_RES_3840x2160p_24Hz));
2466 }
2467 else if ((ucPktVal > 78) && (ucPktVal <= 92))
2468 {
2469 //do nothing;
2470 }
2471 else
2472 {
2473 MS_U8 i = 0;
2474 MS_BOOL bValidVIC = FALSE;
2475
2476 for ( i = 0; i < 14; i++ )
2477 {
2478 if (AR21_9MappingTbl[i][0] == ucPktVal)
2479 {
2480 ucPktVal = AR21_9MappingTbl[i][1];
2481 bValidVIC = TRUE;
2482 break;
2483 }
2484 }
2485
2486 if (!bValidVIC)
2487 {
2488 printf("%s :: Invalid VIC Code for 21:9 Aspect Ratio!!!\r\n", __FUNCTION__);
2489 }
2490 }
2491 }
2492
2493 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x7F00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_0A_H, (ucPktVal & 0x7F));
2494
2495 //check repetition
2496 if ((HDMITxVideoModeTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) &&
2497 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576i))
2498 {
2499 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0001); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x01, 0x0F);
2500 }
2501 else
2502 {
2503 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x00, 0x0F);
2504 }
2505
2506 //YQ1, YQ0
2507 //MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, (MS_U8)(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange << 6));
2508
2509 //AVI version
2510 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0x0300, (MS_U16)(HDMITX_AVI_INFO_PKT_VER << 8));
2511 //MDrv_WriteByteMask(REG_HDMITX_0F_H, HDMITX_AVI_INFO_PKT_VER, 0x03);
2512
2513 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
2514
2515 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2516 {
2517 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
2518 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
2519 }
2520 else
2521 {
2522 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2523 {
2524 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2525 //MDrv_Write2Byte(REG_HDMITX_10_L, 0x05 | (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum<< 3));
2526 }
2527 else
2528 {
2529 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3) | 0x0005));
2530 //MDrv_Write2Byte(REG_HDMITX_10_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3));
2531 }
2532 }
2533 }
2534 break;
2535
2536 case E_HDMITX_SPD_INFOFRAME:
2537 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2538 {
2539 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, 0x0005, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_22_L, 0x00, 0x05);
2540 }
2541 else
2542 {
2543 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2544 {
2545 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
2546
2547 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2548 {
2549 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
2550 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
2551 }
2552 else
2553 {
2554 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2555 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3));
2556 }
2557 }
2558 else
2559 {
2560 MS_U8 i = 0;
2561 MS_U8 ucPktVal = 0;
2562
2563 for (i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN + 1) >> 1); i++)
2564 {
2565 if (i < 4) // vendor name
2566 {
2567 ucPktVal = (HDMITX_VendorName[2*i+1]<<8) | HDMITX_VendorName[2*i];
2568 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+i, 0x7F7F, ucPktVal);
2569 }
2570 else if ((i >= 4) && (i < 12)) // product description
2571 {
2572 ucPktVal = (HDMITX_ProductName[2*(i-4)+1]<<8) | HDMITX_ProductName[2*(i-4)];
2573 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_5_19+(i-4), 0x7F7F, ucPktVal);
2574 }
2575 else // source device information
2576 {
2577 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_13_21, 0x00FF, HDMITX_PACKET_SPD_SDI);
2578 }
2579 }
2580
2581 #if 0
2582 for ( i = 0; i < (HDMITX_SPD_INFO_PKT_LEN - 1); i++ )
2583 {
2584 if ( i < 8 )
2585 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_VendorName[i]);
2586 else
2587 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_ProductName[i-8]);
2588 }
2589
2590 MDrv_WriteByte(REG_HDMITX_21_L, 0x01); //SPD infoframe, byte25: source information: 0x01 = Digital STB
2591 #endif
2592
2593 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
2594
2595 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2596 {
2597 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
2598 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
2599 }
2600 else
2601 {
2602 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3) | 0x0005));
2603 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3));
2604 }
2605 }
2606 }
2607
2608 break;
2609
2610 case E_HDMITX_AUDIO_INFOFRAME:
2611 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2612 {
2613 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, 0x0005, 0x0000);
2614 }
2615 else
2616 {
2617 // Modified for HDMI CTS test -
2618 // - Audio Coding Type (CT3~CT0) is 0x0 then continue else then FAIL
2619 // - Sampling Frequency (SF2~ SF0) is zero then continue else then FAIL.
2620 // - Sample Size (SS1~ SS0) is zero then continue else then FAIL.
2621 //tmp_value = (gHDMITxInfo.output_audio_frequncy << 10) | 0x11; // audio sampling frequency, PCM and 2 channel.
2622 //MHal_HDMITx_Mask_Write(REG_HDMITX_BANK1, REG_PKT_AUD_1_11, 0x1FFF, tmp_value);
2623
2624 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt == E_HDMITX_AUDIO_CH_2) // 2-channel
2625 {
2626 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_2 - 1) & 0x07); // 2 channels
2627 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0); // Channel allocation
2628 }
2629 else //8- channel
2630 {
2631 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_8 - 1)&0x07); // 8 channels
2632 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0x1F00); // Channel allocation
2633 }
2634 //clear LFEP value
2635 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_3_13, 0x0001, 0x0000); //Fix LFEP defalut value in Kappa.
2636
2637 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AUDIO_INFOFRAME);
2638
2639 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2640 {
2641 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, (ucChkSum << 8) | 0x0001);
2642 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AUD_CMD);
2643 }
2644 else
2645 {
2646 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2647 {
2648 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2649 }
2650 else
2651 {
2652 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (HDMITX_PACKET_AUD_FCNT << 3) | 0x0005));
2653 }
2654 }
2655 }
2656
2657 //NOTE:: Kano move channel status from 0x00 to 0x0A
2658 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == FALSE)
2659 {
2660 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudType == E_HDMITX_AUDIO_PCM) ? 0 : BIT1)); // [1]: PCM / non-PCM
2661 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudFreq].CH_Status3 << 8) | (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
2662 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
2663 }
2664 // Audio sampling frequency
2665 // 1 1 0 0 32 kHz
2666 // 0 0 0 0 44.1 kHz
2667 // 0 0 0 1 88.2 kHz
2668 // 0 0 1 1 176.4 kHz
2669 // 0 1 0 0 48 kHz
2670 // 0 1 0 1 96 kHz
2671 // 0 1 1 1 192 kHz
2672 // 1 0 0 1 768 kHz
2673 break;
2674
2675 case E_HDMITX_MPEG_INFOFRAME:
2676 //TBD
2677 break;
2678
2679 case E_HDMITX_HDR_INFOFRAME:
2680 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2681 {
2682 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000);
2683 }
2684 else
2685 {
2686 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2687 {
2688 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
2689
2690 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2691 {
2692 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
2693 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
2694 }
2695 else
2696 {
2697 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2698 }
2699 }
2700 else
2701 {
2702 //TBD
2703 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
2704
2705 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2706 {
2707 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
2708 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
2709 }
2710 else
2711 {
2712 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCNT << 3) | 0x0005));
2713 }
2714
2715 }
2716 }
2717 break;
2718
2719 default:
2720 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
2721 break;
2722 }
2723 }
2724 else //general packet
2725 {
2726 gbGeneralPktList[enPktType].enPktCtrl = packet_process;
2727
2728 switch (enPktType)
2729 {
2730 case E_HDMITX_NULL_PACKET:
2731 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2732 {
2733 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x0005, 0x0000);
2734 }
2735 else
2736 {
2737 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2738 {
2739 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, 0x0001);
2740 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_NUL_CMD);
2741 }
2742 else
2743 {
2744 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2745 {
2746 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 3) |0x0005) );
2747 }
2748 else
2749 {
2750 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((HDMITX_PACKET_NULL_FCNT << 3) |0x0005) );
2751 }
2752 }
2753 }
2754 break;
2755
2756 case E_HDMITX_ACR_PACKET:
2757 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2758 {
2759 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x000F, 0x0008);
2760 }
2761 else
2762 {
2763 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2764 {
2765 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, 0x0009);
2766 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACR_CMD);
2767 }
2768 else //cyclic
2769 {
2770 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2771 {
2772 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 4) |0x05));
2773 }
2774 else
2775 {
2776 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((HDMITX_PACKET_ACR_FCNT << 4) |0x05));
2777 }
2778 }
2779 }
2780 break;
2781
2782 case E_HDMITX_AS_PACKET:
2783 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2784 {
2785 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable audio FIFO, [0]:audio FIFO flush
2786 }
2787 else
2788 {
2789 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT7); // [7]: enable audio FIFO, [0]:audio FIFO not flush
2790 }
2791 break;
2792
2793 case E_HDMITX_GC_PACKET:
2794 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2795 {
2796 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x000F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | 0x0000);
2797 }
2798 else
2799 {
2800 //fill color depth information
2801 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC12_04, 0x010F, gbGeneralPktList[enPktType].PktPara.GCPktPara.enColorDepInfo); // [8]: default phase = 0, [3:0]: Color depth
2802
2803 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2804 {
2805 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1)| 0x21); // [6]: 0, DC and non-DC info send together
2806 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_GCP_CMD);
2807 //MDrv_WriteByteMask(REG_HDMITX_03_L, 0x21, 0x7F);
2808 }
2809 else //cyclic
2810 {
2811 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2812 {
2813 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (gbGeneralPktList[enPktType].FrmCntNum << 4) | 0x29));
2814 }
2815 else
2816 {
2817 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (HDMITX_PACKET_GC_FCNT << 4) | 0x29));
2818 }
2819 }
2820 }
2821 break;
2822
2823 case E_HDMITX_ACP_PACKET:
2824 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2825 {
2826 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0005, 0x0000);
2827 }
2828 else
2829 {
2830 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_0_38, 0xFFFF, 0x0000); //acp type is 0x00
2831
2832 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2833 {
2834 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0001);
2835 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACP_CMD);
2836 }
2837 else //cyclic
2838 {
2839 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2840 {
2841 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
2842 }
2843 else
2844 {
2845 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, (HDMITX_PACKET_ACP_FCNT | 0x0005));
2846 }
2847 }
2848 }
2849 break;
2850
2851 case E_HDMITX_ISRC1_PACKET:
2852 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2853 {
2854 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
2855 }
2856 else
2857 {
2858 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2859 {
2860 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0001);
2861 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
2862 }
2863 else //cyclic
2864 {
2865 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2866 {
2867 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005)); }
2868 else
2869 {
2870 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
2871 }
2872 }
2873 }
2874 break;
2875
2876 case E_HDMITX_ISRC2_PACKET:
2877 //check ISRC cnt value
2878 if (MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51) & 0x8000)
2879 {
2880 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2881 {
2882 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
2883 }
2884 else
2885 {
2886 MS_U8 u8ISRCCntVal = 0x80;
2887
2888 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2889 {
2890 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, (u8ISRCCntVal << 8) | 0x0001 ); // 0x80: ISRC_CONT = 1, ISRC1 & ISRC2
2891 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
2892 }
2893 else //cyclic
2894 {
2895 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2896 {
2897 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
2898 }
2899 else
2900 {
2901 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
2902 }
2903 }
2904 }
2905 }
2906 break;
2907
2908 case E_HDMITX_DSD_PACKET:
2909 //TBD
2910 break;
2911
2912 case E_HDMITX_HBR_PACKET:
2913 //TBD
2914 break;
2915
2916 case E_HDMITX_GM_PACKET:
2917 //TBD
2918 break;
2919
2920 default:
2921 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
2922 break;
2923 }
2924 }
2925 }
2926
MHal_HDMITx_EnableSSC(MS_BOOL bEnable,MS_U32 uiTMDSCLK)2927 void MHal_HDMITx_EnableSSC(MS_BOOL bEnable, MS_U32 uiTMDSCLK)
2928 {
2929 //K6 does not implement SSC yet.
2930 #if 0
2931 #define HDMITX_MPLL_CLK 432 //432MHz
2932 #define HDMITX_SSC_CLK 30 //30KHz
2933 #define HDMITX_SSC_DEVIATION 0.001 // 0.1%
2934 #define HDMITX_SSC_THREAD_LEVEL1 150 ///1080p 8bits
2935 #define HDMITX_SSC_THREAD_LEVEL2 300 ///4K30 8bits
2936 #define HDMITX_SSC_SPAN_REG REG_HDMITxPHY_CONFIG_06
2937 #define HDMITX_SSC_STEP_REG REG_HDMITxPHY_CONFIG_07
2938 #define HDMITX_SSC_SUB_DIVIDER_REG REG_HDMITxPHY_CONFIG_01
2939
2940 double ub2x19times = 524288;// 2^ 19
2941 double dSYNCLK = 1;
2942 double ub432MHz = HDMITX_MPLL_CLK;
2943 double ubSSCClk = HDMITX_SSC_CLK;
2944 double dSSc_Deviation= HDMITX_SSC_DEVIATION;
2945 MS_U32 ubSYNSet = 0;
2946 double dSSC_Span = 0;
2947 double dSSC_Step = 0;
2948 double dPixel_Clk = 0;
2949
2950 if(!bEnable)
2951 {
2952 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, 0 );//Span
2953 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, 0);//Step
2954 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0 );//Sub-Divider
2955 return;
2956 }
2957
2958
2959 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02);
2960 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16);
2961
2962 dSYNCLK = (double) ((ub432MHz*ub2x19times)/ubSYNSet);
2963
2964 dSSC_Span = dSYNCLK * 1000 / (ubSSCClk * 4); //Span = SYN_CLK / (SSC_CLK * 4)
2965 dSSC_Step = ubSYNSet * dSSc_Deviation / dSSC_Span; //Step = SYN_SET * deviation / Span
2966
2967 printf("ubSYNSet=%x, dSYNCLK=%f, dSSC_Span=%f, dSSC_Step=%f\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dSSC_Step);
2968
2969 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, ( ((int)dSSC_Span) & 0x3FFF) );//Span
2970 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, ( ((int)dSSC_Step) & 0xFFFF) );//Step
2971
2972 //Read tmds clock
2973 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_20, 0x3F, 0x3F);
2974 dPixel_Clk = (double) ( (double)(MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_21) << 1) * 12 / 128);
2975 printf("dPixel_Clk=%f\r\n", dPixel_Clk);
2976
2977 if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL1)
2978 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x0000 );//Sub-Divider
2979 else if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL2)
2980 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x1000 );//Sub-Divider
2981 else
2982 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x3000 );//Sub-Divider
2983 #endif
2984 }
MHal_HDMITx_SetVideoInfoByCustomer(MsHDMITX_VIDEO_TIMING idx,stHDMITX_TIMING_INFO_BY_CUSTOMER stTimingInfo)2985 void MHal_HDMITx_SetVideoInfoByCustomer(MsHDMITX_VIDEO_TIMING idx, stHDMITX_TIMING_INFO_BY_CUSTOMER stTimingInfo)
2986 {
2987 return;
2988 }
MHal_HDMITx_GetTMDSStatus(void)2989 MS_U32 MHal_HDMITx_GetTMDSStatus(void)
2990 {
2991
2992 return 0;
2993 }
MHal_HDMITx_GetMaxPixelClk(void)2994 MS_U32 MHal_HDMITx_GetMaxPixelClk(void)
2995 {
2996
2997 return 0;
2998 }
Mhal_HDMITx_SetSCDCCapability(MS_BOOL bFlag)2999 void Mhal_HDMITx_SetSCDCCapability(MS_BOOL bFlag)
3000 {
3001 return;
3002 }
MHal_HDMITx_GetPixelClk_ByTiming(MsHDMITX_VIDEO_TIMING idx,MsHDMITX_VIDEO_COLOR_FORMAT color_fmt,MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth)3003 MS_U32 MHal_HDMITx_GetPixelClk_ByTiming(MsHDMITX_VIDEO_TIMING idx, MsHDMITX_VIDEO_COLOR_FORMAT color_fmt, MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth)
3004 {
3005
3006 return 0;
3007 }
3008
3009