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Searched refs:_REG16_SET (Results 1 – 7 of 7) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsio/
H A DhalTSIO.c72 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value)); macro
514 _REG16_SET(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSIO), REG_CLKGEN0_TSIO_DISABLE_CLOCK); in HAL_TSIO_ClkOpen()
528 _REG16_SET(&(_TSIOCtrl0->SW_RSTZ), TSIO0_SW_RSTZ); in HAL_TSIO_Reset()
535 _REG16_SET(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_INSERT_CTS_IN_TX); in HAL_TSIO_Tx2Rx_InsertCTS()
547 _REG16_SET(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_TX_DIRECT_RX_8); in HAL_TSIO_Tx2Rx_Direct8()
559 _REG16_SET(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_TX_DIRECT_RX_16); in HAL_TSIO_Tx2Rx_Direct16()
560 _REG16_SET(&(_TSIOCtrl0->PUH_CONFIG1), TSIO0_PUH_CONFIG1_VCC_POWER_GOOD_SET_HIGHT); in HAL_TSIO_Tx2Rx_Direct16()
561 _REG16_SET(&(_TSIOCtrl0->PUH_CONFIG1), TSIO0_PUH_CONFIG1_TSIO_RX_DATA_VALID_SET_HIGH); in HAL_TSIO_Tx2Rx_Direct16()
597 _REG16_SET(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_DECRYPT_DISABLE); in HAL_TSIO_Decrypt_Set()
601 _REG16_SET(&(_TSIOCtrl1->PKT_SYNC_CTRL),TSIO1_PKT_SYNC_EN); in HAL_TSIO_Decrypt_Set()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsio/
H A DhalTSIO.c72 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value)); macro
514 _REG16_SET(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSIO), REG_CLKGEN0_TSIO_DISABLE_CLOCK); in HAL_TSIO_ClkOpen()
528 _REG16_SET(&(_TSIOCtrl0->SW_RSTZ), TSIO0_SW_RSTZ); in HAL_TSIO_Reset()
535 _REG16_SET(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_INSERT_CTS_IN_TX); in HAL_TSIO_Tx2Rx_InsertCTS()
547 _REG16_SET(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_TX_DIRECT_RX_8); in HAL_TSIO_Tx2Rx_Direct8()
559 _REG16_SET(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_TX_DIRECT_RX_16); in HAL_TSIO_Tx2Rx_Direct16()
560 _REG16_SET(&(_TSIOCtrl0->PUH_CONFIG1), TSIO0_PUH_CONFIG1_VCC_POWER_GOOD_SET_HIGHT); in HAL_TSIO_Tx2Rx_Direct16()
561 _REG16_SET(&(_TSIOCtrl0->PUH_CONFIG1), TSIO0_PUH_CONFIG1_TSIO_RX_DATA_VALID_SET_HIGH); in HAL_TSIO_Tx2Rx_Direct16()
597 _REG16_SET(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_DECRYPT_DISABLE); in HAL_TSIO_Decrypt_Set()
601 _REG16_SET(&(_TSIOCtrl1->PKT_SYNC_CTRL),TSIO1_PKT_SYNC_EN); in HAL_TSIO_Decrypt_Set()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c93 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value)); macro
244 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
251 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
890 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
893 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
899 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
902 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
905 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c94 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value)); macro
247 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
254 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
256 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
893 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
899 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
902 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
905 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
908 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c93 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value)); macro
243 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
246 …_REG16_SET(&(_TSOCtrl1->REG_TSO_MIU_ABT_CONFIG_1), REG_MIU_ABT_CONFIG_1_CHECK2MI_RDY | REG_MIU_ABT… in HAL_TSO_Init()
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
255 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
884 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
887 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
890 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
893 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c93 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value)); macro
246 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
255 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
881 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
884 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
887 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
890 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
893 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c93 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value)); macro
246 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
255 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
881 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
884 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
887 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
890 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
893 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
[all …]