93 #define _REG16_SET(reg, value);    _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value));  macro
243     _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH);  in HAL_TSO_Init()
246 …_REG16_SET(&(_TSOCtrl1->REG_TSO_MIU_ABT_CONFIG_1), REG_MIU_ABT_CONFIG_1_CHECK2MI_RDY | REG_MIU_ABT…  in HAL_TSO_Init()
253     _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);  in HAL_TSO_Reset_All()
255     _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1);  in HAL_TSO_Reset_All()
884                 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
887 …             _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
890 …             _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
893 …             _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
896 …             _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
899 …             _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
1028     _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ);  in HAL_TSO_Get_Filein_ReadAddr()
1187             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1);  in HAL_TSO_ChIf_ClrByteCnt()
1191             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2);  in HAL_TSO_ChIf_ClrByteCnt()
1195             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3);  in HAL_TSO_ChIf_ClrByteCnt()
1199             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4);  in HAL_TSO_ChIf_ClrByteCnt()
1203             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5);  in HAL_TSO_ChIf_ClrByteCnt()
1207             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6);  in HAL_TSO_ChIf_ClrByteCnt()
1401         _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);  in HAL_TSO_RW_ValidBlock_Count()
1420         _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);  in HAL_TSO_RW_InvalidBlock_Count()
1497     _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_WLD);  in HAL_TSO_LPcr2_Set()
1509     _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_LOAD);  in HAL_TSO_LPcr2_Get()
1735                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1);  in HAL_TSO_Livein_3Wire()
1738                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2);  in HAL_TSO_Livein_3Wire()
1741                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3);  in HAL_TSO_Livein_3Wire()
1744                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4);  in HAL_TSO_Livein_3Wire()
1747                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5);  in HAL_TSO_Livein_3Wire()
1750                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6);  in HAL_TSO_Livein_3Wire()
1791         _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_TSIO_MODE);  in HAL_TSO_TsioMode_En()
1803         _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_TSIO2OPIF);  in HAL_TSO_Tsio2Opif_En()
1815         _REG16_SET(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN);  in HAL_TSO_SerialMode_En()
1879     _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_TX_RESET);  in HAL_TSO_SVQBuf_Set()
1881     _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_SVQ_TX_ENABLE);  in HAL_TSO_SVQBuf_Set()
2113         _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);  in HAL_TSO_PowerCtrl()
2163         _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);  in HAL_TSO_PowerCtrl()