1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2011-2013 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halTSIO.c
20 // @brief TS I/O HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "regTSIO.h"
25 #include "halTSIO.h"
26
27 //--------------------------------------------------------------------------------------------------
28 // Driver Compiler Option
29 //--------------------------------------------------------------------------------------------------
30
31 //--------------------------------------------------------------------------------------------------
32 // TSP Hardware Abstraction Layer
33 //--------------------------------------------------------------------------------------------------
34 static REG_Ctrl_TSIO0* _TSIOCtrl0 = NULL;
35 static REG_Ctrl_TSIO1* _TSIOCtrl1 = NULL;
36 static REG_Ctrl_TSIO2* _TSIOCtrl2 = NULL;
37 static REG_Ctrl_TSIO3* _TSIOCtrl3 = NULL;
38 static REG_Ctrl_TSIO_LOCDEC* _TSIOCtrlLOCDEC = NULL;
39 static REG_Ctrl_TSO0* _TSOCtrl0 = NULL;
40 static REG_Ctrl_TSO2* _TSOCtrl2 = NULL;
41 static REG_Ctrl_TSO3* _TSOCtrl3 = NULL;
42 static REG_Ctrl_CHIPTOP* _TSIOCHIPTOP = NULL;
43 static REG_Ctrl_CLOCKGEN0* _TSIO_CLKGEN0 = NULL;
44 static REG_Ctrl_TSIO_PHY* _TSIOCtrlPHY = NULL;
45 static REG_Ctrl_TSP8* _TSPCtrl8 = NULL;
46 static REG_Ctrl_STRLD* _TSIO_STRLD = NULL;
47
48 static MS_VIRT _u32TSIORegBase = 0;
49
50 //-------------------------------------------------------------------------------------------------
51 // Debug Message
52 //-------------------------------------------------------------------------------------------------
53 #define HAL_TSIO_DBGMSG(_level,_f) do {if(_u32TSIODbgLevel >= (_level)) (_f);} while(0)
54 static MS_U32 _u32TSIODbgLevel = E_HAL_TSIO_DBG_LEVEL_WARN;
55
56
57 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFF); \
58 (reg)->H = ((value) >> 16); } while(0)
59
60 #define _HAL_REG16_W(reg, value) { (reg)->data = (MS_U16)((value) & 0xFFFF); }
61
62 //--------------------------------------------------------------------------------------------------
63 // Macro of bit operations
64 //--------------------------------------------------------------------------------------------------
65 #define HAS_FLAG(flag, bit) ((flag) & (bit))
66 #define SET_FLAG(flag, bit) ((flag)|= (bit))
67 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit)))
68 #define SET_FLAG1(flag, bit) ((flag)| (bit))
69 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit)))
70
71
72 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value));
73 #define _REG32_SET(reg, value); _HAL_REG32_W(reg, SET_FLAG1(_HAL_REG32_R(reg), value));
74 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value));
75 #define _REG32_CLR(reg, value); _HAL_REG32_W(reg, RESET_FLAG1(_HAL_REG32_R(reg), value));
76 #define _REG16_SET_MASK(reg, value, mask, shift); _HAL_REG16_W(reg, (_HAL_REG16_R(reg)& ~mask) | ((value << shift) & mask));
77 #define _REG32_SET_MASK(reg, value, mask, shift); _HAL_REG32_W(reg, (_HAL_REG32_R(reg)& ~mask) | ((value << shift) & mask));
78 #define _TSIO_SGDMAIN_PIDFLT_ADDR(FltId) (REG_SGDMAIN_PIDFLT_BASE + ((FltId) << 2))
79
80 //--------------------------------------------------------------------------------------------------
81 // Analog phase table
82 //--------------------------------------------------------------------------------------------------
83 typedef struct
84 {
85 MS_U8 u8Phase_Digital;
86 MS_U8 u8Delay1T;
87 MS_U8 u8Corse;
88 MS_U8 u8Fine;
89 }ANALOG_PHASE_SETTING;
90
91 static MS_U8 u8Phasetable = 0;
92
93 #if 1 //new
94 ANALOG_PHASE_SETTING SETTING[ANALOG_PHASE_TABLE][ANALOG_PHASE_NUM] =
95 {
96 //200M
97 {
98 { 0, 0, 0, 0},
99 { 1, 0, 0, 4},
100 { 2, 0, 0, 4},
101 { 3, 0, 0, 4},
102 { 4, 0, 1, 0},
103 { 5, 0, 1, 0},
104 { 6, 0, 1, 4},
105 { 7, 0, 1, 4},
106 { 8, 0, 1, 4},
107 { 9, 0, 2, 0},
108 {10, 0, 2, 0},
109 {11, 0, 2, 4},
110 {12, 0, 2, 4},
111 {13, 0, 2, 4},
112 {14, 0, 3, 0},
113 {15, 0, 3, 0},
114 {16, 0, 3, 4},
115 {17, 0, 3, 4},
116 {18, 0, 3, 4},
117 {19, 1, 0, 0},
118 {20, 1, 0, 0},
119 {21, 1, 0, 4},
120 {22, 1, 0, 4},
121 {23, 1, 0, 4},
122 {24, 1, 1, 0},
123 {25, 1, 1, 0},
124 {26, 1, 1, 4},
125 {27, 1, 1, 4},
126 {28, 1, 1, 4},
127 {29, 1, 2, 0},
128 {30, 1, 2, 0},
129 {31, 1, 2, 4},
130 {32, 1, 2, 4},
131 {33, 1, 2, 4},
132 {34, 1, 3, 0},
133 {35, 1, 3, 0},
134 {36, 1, 3, 4},
135 {37, 1, 3, 4},
136 {38, 1, 3, 4},
137 {39, 0, 0, 0},
138 },
139
140 //100M
141 {
142 { 0, 0, 0, 0},
143 { 1, 0, 0, 4},
144 { 2, 0, 0, 4},
145 { 3, 0, 1, 4},
146 { 4, 0, 2, 0},
147 { 5, 0, 2, 0},
148 { 6, 0, 2, 4},
149 { 7, 0, 2, 4},
150 { 8, 0, 3, 4},
151 { 9, 0, 4, 0},
152 {10, 0, 4, 0},
153 {11, 0, 4, 4},
154 {12, 0, 4, 4},
155 {13, 0, 5, 4},
156 {14, 0, 6, 0},
157 {15, 0, 6, 0},
158 {16, 0, 6, 4},
159 {17, 0, 6, 4},
160 {18, 0, 7, 4},
161 {19, 1, 0, 0},
162 {20, 1, 0, 0},
163 {21, 1, 0, 4},
164 {22, 1, 0, 4},
165 {23, 1, 1, 4},
166 {24, 1, 2, 0},
167 {25, 1, 2, 0},
168 {26, 1, 2, 4},
169 {27, 1, 2, 4},
170 {28, 1, 3, 4},
171 {29, 1, 4, 0},
172 {30, 1, 4, 0},
173 {31, 1, 4, 4},
174 {32, 1, 4, 4},
175 {33, 1, 5, 4},
176 {34, 1, 6, 0},
177 {35, 1, 6, 0},
178 {36, 1, 6, 4},
179 {37, 1, 6, 4},
180 {38, 1, 7, 4},
181 {39, 0, 0, 0},
182 },
183 //50M
184 {
185 { 0, 0, 0, 0},
186 { 1, 0, 1, 4},
187 { 2, 0, 2, 4},
188 { 3, 0, 3, 4},
189 { 4, 0, 4, 0},
190 { 5, 0, 4, 0},
191 { 6, 0, 5, 4},
192 { 7, 0, 6, 4},
193 { 8, 0, 7, 4},
194 { 9, 0, 8, 0},
195 {10, 0, 8, 0},
196 {11, 0, 9, 4},
197 {12, 0, 10, 4},
198 {13, 0, 11, 4},
199 {14, 0, 12, 0},
200 {15, 0, 12, 0},
201 {16, 0, 13, 4},
202 {17, 0, 14, 4},
203 {18, 0, 15, 4},
204 {19, 1, 0, 0},
205 {20, 1, 0, 0},
206 {21, 1, 1, 4},
207 {22, 1, 2, 4},
208 {23, 1, 3, 4},
209 {24, 1, 4, 0},
210 {25, 1, 4, 0},
211 {26, 1, 5, 4},
212 {27, 1, 6, 4},
213 {28, 1, 7, 4},
214 {29, 1, 8, 0},
215 {30, 1, 8, 0},
216 {31, 1, 9, 4},
217 {32, 1, 10, 4},
218 {33, 1, 11, 4},
219 {34, 1, 12, 0},
220 {35, 1, 12, 0},
221 {36, 1, 13, 4},
222 {37, 1, 14, 4},
223 {38, 1, 15, 4},
224 {39, 0, 0, 0},
225 },
226 //25M
227 {
228 { 0, 0, 0, 0},
229 { 1, 0, 1, 4},
230 { 2, 0, 3, 4},
231 { 3, 0, 5, 4},
232 { 4, 0, 8, 0},
233 { 5, 0, 8, 0},
234 { 6, 0, 9, 4},
235 { 7, 0, 11, 4},
236 { 8, 0, 13, 4},
237 { 9, 0, 16, 0},
238 {10, 0, 16, 0},
239 {11, 0, 17, 4},
240 {12, 0, 19, 4},
241 {13, 0, 21, 4},
242 {14, 0, 24, 0},
243 {15, 0, 24, 0},
244 {16, 0, 25, 4},
245 {17, 0, 27, 4},
246 {18, 0, 29, 4},
247 {19, 1, 0, 0},
248 {20, 1, 0, 0},
249 {21, 1, 1, 4},
250 {22, 1, 3, 4},
251 {23, 1, 5, 4},
252 {24, 1, 8, 0},
253 {25, 1, 8, 0},
254 {26, 1, 9, 4},
255 {27, 1, 11, 4},
256 {28, 1, 13, 4},
257 {29, 1, 16, 0},
258 {30, 1, 16, 0},
259 {31, 1, 17, 4},
260 {32, 1, 19, 4},
261 {33, 1, 21, 4},
262 {34, 1, 24, 0},
263 {35, 1, 24, 0},
264 {36, 1, 25, 4},
265 {37, 1, 27, 4},
266 {38, 1, 29, 4},
267 {39, 0, 0, 0},
268 },
269 };
270 #else
271 //old phase table
272 ANALOG_PHASE_SETTING SETTING[ANALOG_PHASE_TABLE][ANALOG_PHASE_NUM] =
273 {
274 //200M
275 {
276 { 0, 0, 0, 0},
277 { 1, 0, 0, 0},
278 { 2, 0, 0, 5},
279 { 3, 0, 0, 5},
280 { 4, 0, 0, 7},
281 { 5, 0, 1, 0},
282 { 6, 0, 1, 0},
283 { 7, 0, 1, 5},
284 { 8, 0, 1, 5},
285 { 9, 0, 1, 7},
286 {10, 0, 2, 0},
287 {11, 0, 2, 0},
288 {12, 0, 2, 5},
289 {13, 0, 2, 5},
290 {14, 0, 2, 7},
291 {15, 0, 3, 0},
292 {16, 0, 3, 0},
293 {17, 0, 3, 5},
294 {18, 0, 3, 5},
295 {19, 0, 3, 7},
296 {20, 1, 0, 0},
297 {21, 1, 0, 0},
298 {22, 1, 0, 5},
299 {23, 1, 0, 5},
300 {24, 1, 0, 7},
301 {25, 1, 1, 0},
302 {26, 1, 1, 0},
303 {27, 1, 1, 5},
304 {28, 1, 1, 5},
305 {29, 1, 1, 7},
306 {30, 1, 2, 0},
307 {31, 1, 2, 0},
308 {32, 1, 2, 5},
309 {33, 1, 2, 5},
310 {34, 1, 2, 7},
311 {35, 1, 3, 0},
312 {36, 1, 3, 0},
313 {37, 1, 3, 5},
314 {38, 1, 3, 5},
315 {39, 1, 3, 7},
316 },
317
318 //100M
319 {
320 { 0, 0, 0, 0},
321 { 1, 0, 0, 5},
322 { 2, 0, 0, 7},
323 { 3, 0, 1, 0},
324 { 4, 0, 1, 5},
325 { 5, 0, 2, 0},
326 { 6, 0, 2, 5},
327 { 7, 0, 2, 7},
328 { 8, 0, 3, 0},
329 { 9, 0, 3, 5},
330 {10, 0, 4, 0},
331 {11, 0, 4, 5},
332 {12, 0, 4, 7},
333 {13, 0, 5, 0},
334 {14, 0, 5, 5},
335 {15, 0, 6, 0},
336 {16, 0, 6, 5},
337 {17, 0, 6, 7},
338 {18, 0, 7, 0},
339 {19, 0, 7, 5},
340 {20, 1, 0, 0},
341 {21, 1, 0, 5},
342 {22, 1, 0, 7},
343 {23, 1, 1, 0},
344 {24, 1, 1, 5},
345 {25, 1, 2, 0},
346 {26, 1, 2, 5},
347 {27, 1, 2, 7},
348 {28, 1, 3, 0},
349 {29, 1, 3, 5},
350 {30, 1, 4, 0},
351 {31, 1, 4, 5},
352 {32, 1, 4, 7},
353 {33, 1, 5, 0},
354 {34, 1, 5, 5},
355 {35, 1, 6, 0},
356 {36, 1, 6, 5},
357 {37, 1, 6, 7},
358 {38, 1, 7, 0},
359 {39, 1, 7, 5},
360 },
361 //50M
362 {
363 { 0, 0, 0, 0},
364 { 1, 0, 0, 7},
365 { 2, 0, 1, 5},
366 { 3, 0, 2, 5},
367 { 4, 0, 3, 5},
368 { 5, 0, 4, 0},
369 { 6, 0, 4, 7},
370 { 7, 0, 5, 5},
371 { 8, 0, 6, 5},
372 { 9, 0, 7, 5},
373 {10, 0, 8, 0},
374 {11, 0, 8, 7},
375 {12, 0, 9, 5},
376 {13, 0, 10, 5},
377 {14, 0, 11, 5},
378 {15, 0, 12, 0},
379 {16, 0, 12, 7},
380 {17, 0, 13, 5},
381 {18, 0, 14, 5},
382 {19, 0, 15, 5},
383 {20, 1, 0, 0},
384 {21, 1, 0, 7},
385 {22, 1, 1, 5},
386 {23, 1, 2, 5},
387 {24, 1, 3, 5},
388 {25, 1, 4, 0},
389 {26, 1, 4, 7},
390 {27, 1, 5, 5},
391 {28, 1, 6, 5},
392 {29, 1, 7, 5},
393 {30, 1, 8, 0},
394 {31, 1, 8, 7},
395 {32, 1, 9, 5},
396 {33, 1, 10, 5},
397 {34, 1, 11, 5},
398 {35, 1, 12, 0},
399 {36, 1, 12, 7},
400 {37, 1, 13, 5},
401 {38, 1, 14, 5},
402 {39, 1, 15, 5},
403 },
404 //25M
405 {
406 { 0, 0, 0, 0},
407 { 1, 0, 1, 7},
408 { 2, 0, 3, 5},
409 { 3, 0, 5, 0},
410 { 4, 0, 6, 5},
411 { 5, 0, 8, 0},
412 { 6, 0, 9, 7},
413 { 7, 0, 11, 5},
414 { 8, 0, 13, 0},
415 { 9, 0, 14, 5},
416 {10, 0, 16, 0},
417 {11, 0, 17, 7},
418 {12, 0, 19, 5},
419 {13, 0, 21, 0},
420 {14, 0, 22, 5},
421 {15, 0, 24, 0},
422 {16, 0, 25, 7},
423 {17, 0, 27, 5},
424 {18, 0, 29, 0},
425 {19, 0, 30, 5},
426 {20, 1, 0, 0},
427 {21, 1, 1, 7},
428 {22, 1, 3, 5},
429 {23, 1, 5, 0},
430 {24, 1, 6, 5},
431 {25, 1, 8, 0},
432 {26, 1, 9, 7},
433 {27, 1, 11, 5},
434 {28, 1, 13, 0},
435 {29, 1, 14, 5},
436 {30, 1, 16, 0},
437 {31, 1, 17, 7},
438 {32, 1, 19, 5},
439 {33, 1, 21, 0},
440 {34, 1, 22, 5},
441 {35, 1, 24, 0},
442 {36, 1, 25, 7},
443 {37, 1, 27, 5},
444 {38, 1, 29, 0},
445 {39, 1, 30, 5},
446 },
447 };
448 #endif
449 //--------------------------------------------------------------------------------------------------
450 // Implementation
451 //--------------------------------------------------------------------------------------------------
_HAL_REG32_R(REG32_TSIO * reg)452 static MS_U32 _HAL_REG32_R(REG32_TSIO *reg)
453 {
454 MS_U32 value = 0;
455 value = (reg)->H << 16;
456 value |= (reg)->L;
457 return value;
458 }
459
_HAL_REG16_R(REG16_TSIO * reg)460 static MS_U16 _HAL_REG16_R(REG16_TSIO *reg)
461 {
462 MS_U16 value = 0;
463 value = (reg)->data;
464 return value;
465 }
466
467 //=======================================================
468 // General API
469 //=======================================================
HAL_TSIO_SetBank(MS_VIRT u32BankAddr)470 void HAL_TSIO_SetBank(MS_VIRT u32BankAddr)
471 {
472 _u32TSIORegBase = u32BankAddr;
473 _TSIOCtrl0 = (REG_Ctrl_TSIO0*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO0); // 0x171A
474 _TSIOCtrl1 = (REG_Ctrl_TSIO1*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO1); // 0x171B
475 _TSIOCtrl2 = (REG_Ctrl_TSIO2*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO2); // 0x171C
476 _TSIOCtrl3 = (REG_Ctrl_TSIO3*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO3); // 0x1739
477 _TSIOCtrlLOCDEC = (REG_Ctrl_TSIO_LOCDEC*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO_LOCDEC); // 0x171E
478 _TSOCtrl0 = (REG_Ctrl_TSO0*)(_u32TSIORegBase+ REG_CTRL_BASE_TSO0); //0x1706
479 _TSOCtrl2 = (REG_Ctrl_TSO2*)(_u32TSIORegBase+ REG_CTRL_BASE_TSO2); // 0x1539
480 _TSOCtrl3 = (REG_Ctrl_TSO3*)(_u32TSIORegBase+ REG_CTRL_BASE_TSO3); // 0x171D
481 _TSIOCHIPTOP = (REG_Ctrl_CHIPTOP*)(_u32TSIORegBase+ REG_CTRL_BASE_CHIPTOP); // 0x101E
482 _TSIO_CLKGEN0 = (REG_Ctrl_CLOCKGEN0*)(_u32TSIORegBase+ REG_CTRL_BASE_CLOCKGEN0); // 0x100B
483 _TSIOCtrlPHY = (REG_Ctrl_TSIO_PHY*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO_PHY); // 0x171F
484 _TSPCtrl8 = (REG_Ctrl_TSP8 *)(_u32TSIORegBase+ 0xC4E00UL); // TSP8 0x1627
485 _TSIO_STRLD = (REG_Ctrl_STRLD*)(_u32TSIORegBase+ REG_CTRL_BASE_STRLD); //STRLD 0x1029
486 }
487
HAL_TSIO_DbgLevel(EN_HAL_TSIO_DBGMSG_LEVEL eLevel)488 void HAL_TSIO_DbgLevel(EN_HAL_TSIO_DBGMSG_LEVEL eLevel)
489 {
490 _u32TSIODbgLevel = eLevel;
491 }
492
HAL_TSIO_ClkOpen(MS_BOOL bEnable)493 void HAL_TSIO_ClkOpen(MS_BOOL bEnable)
494 {
495 if (bEnable)
496 {
497 //tsp clk
498 _REG16_CLR(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSP), REG_CLKGEN0_TSP_DISABLE_CLOCK);
499 _REG16_SET_MASK(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSP), 0, REG_CLKGEN0_TSP_CLKSOURCE_MASK, REG_CLKGEN0_TSP_CLKSOURCE_SHIFT);
500
501 //TSP boot clk set
502 _REG16_CLR(&(_TSIOCHIPTOP->REG_TOP_TSIO), REG_TOP_TSIO_TSP_BOOT_CLK_SEL);
503
504 //ckg tsp tsio
505 _REG16_CLR(&(_TSIOCtrl0->CKG_TSP_TSIO), TSIO0_CKG_TSP_TSIO);
506
507 //tsio clk
508 _REG16_CLR(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSIO), REG_CLKGEN0_TSIO_DISABLE_CLOCK);
509 _REG16_SET_MASK(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSIO), 0, REG_CLKGEN0_TSIO_CLKSOURCE_MASK, REG_CLKGEN0_TSIO_CLKSOURCE_SHIFT);
510 }
511 else
512 {
513 //tsio clk
514 _REG16_SET(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSIO), REG_CLKGEN0_TSIO_DISABLE_CLOCK);
515 }
516 }
HAL_TSIO_PowerInit(void)517 void HAL_TSIO_PowerInit(void)
518 {
519 //_HAL_REG16_W(&(_TSIOCtrl0->AD_TX_CONFIG0),0x0000); // fpga default value
520 //_HAL_REG16_W(&(_TSIOCtrl0->AD_RX_CONFIG0),0x0000); // fpga default value
521 //_REG16_SET(&(_TSIOCtrl0->AD_TX_CONFIG0),TSIO0_PD_SMC_LDO_FPGA); // fpga setting
522 //_HAL_REG16_W(&(_TSIOCtrl0->MAX_PERIOD_OF_PKT_SYNC),0x0000); // for test
523 }
524
HAL_TSIO_Reset(void)525 void HAL_TSIO_Reset(void)
526 {
527 _REG16_CLR(&(_TSIOCtrl0->SW_RSTZ), TSIO0_SW_RSTZ);//low active
528 _REG16_SET(&(_TSIOCtrl0->SW_RSTZ), TSIO0_SW_RSTZ);
529 }
530
HAL_TSIO_Tx2Rx_InsertCTS(MS_BOOL bEnable)531 void HAL_TSIO_Tx2Rx_InsertCTS(MS_BOOL bEnable)
532 {
533 if (bEnable)
534 {
535 _REG16_SET(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_INSERT_CTS_IN_TX);
536 }
537 else
538 {
539 _REG16_CLR(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_INSERT_CTS_IN_TX);
540 }
541 }
542
HAL_TSIO_Tx2Rx_Direct8(MS_BOOL bEnable)543 void HAL_TSIO_Tx2Rx_Direct8(MS_BOOL bEnable)
544 {
545 if (bEnable)
546 {
547 _REG16_SET(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_TX_DIRECT_RX_8);
548 }
549 else
550 {
551 _REG16_CLR(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_TX_DIRECT_RX_8);
552 }
553 }
554
HAL_TSIO_Tx2Rx_Direct16(MS_BOOL bEnable)555 void HAL_TSIO_Tx2Rx_Direct16(MS_BOOL bEnable)
556 {
557 if (bEnable)
558 {
559 _REG16_SET(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_TX_DIRECT_RX_16);
560 _REG16_SET(&(_TSIOCtrl0->PUH_CONFIG1), TSIO0_PUH_CONFIG1_VCC_POWER_GOOD_SET_HIGHT);
561 _REG16_SET(&(_TSIOCtrl0->PUH_CONFIG1), TSIO0_PUH_CONFIG1_TSIO_RX_DATA_VALID_SET_HIGH);
562 }
563 else
564 {
565 _REG16_CLR(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_TX_DIRECT_RX_16);
566 _REG16_CLR(&(_TSIOCtrl0->PUH_CONFIG1), TSIO0_PUH_CONFIG1_VCC_POWER_GOOD_SET_HIGHT);
567 _REG16_CLR(&(_TSIOCtrl0->PUH_CONFIG1), TSIO0_PUH_CONFIG1_TSIO_RX_DATA_VALID_SET_HIGH);
568 }
569 }
570
HAL_TSIO_Tx2Rx_Loopback(MS_BOOL bEnable)571 void HAL_TSIO_Tx2Rx_Loopback(MS_BOOL bEnable)
572 {
573 if (bEnable)
574 {
575 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_18), 0x20,TSIO_PHY_18_TEST_TSIO_MASK, TSIO_PHY_18_TEST_TSIO_SHIFT); // loopback
576
577 }
578 else
579 {
580 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_18), 0,TSIO_PHY_18_TEST_TSIO_MASK, TSIO_PHY_18_TEST_TSIO_SHIFT);
581 }
582 }
583
HAL_TSIO_StuffingSID_Set(MS_U8 u8Stuffing_sid)584 void HAL_TSIO_StuffingSID_Set(MS_U8 u8Stuffing_sid)
585 {
586 _REG16_SET_MASK(&(_TSIOCtrl0->TX_CONFIG0), u8Stuffing_sid, TSIO0_STUFF_SVID_MASK, TSIO0_STUFF_SVID_SHIFT);
587 }
588
HAL_TSIO_Decrypt_Set(MS_BOOL bEnable)589 void HAL_TSIO_Decrypt_Set(MS_BOOL bEnable)
590 {
591 if (bEnable)
592 {
593 _REG16_CLR(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_DECRYPT_DISABLE);
594 }
595 else
596 {
597 _REG16_SET(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_DECRYPT_DISABLE);
598 }
599
600 //_REG16_SET(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_BIT_TRAINING_BYPASS);
601 _REG16_SET(&(_TSIOCtrl1->PKT_SYNC_CTRL),TSIO1_PKT_SYNC_EN);
602 }
603
HAL_TSIO_Threshold_Set(MS_U8 u8Threshold)604 void HAL_TSIO_Threshold_Set(MS_U8 u8Threshold)
605 {
606 _REG16_SET_MASK(&(_TSIOCtrl1->TSIO_SYNC_THRESHOLD), (u8Threshold-1), TSIO1_TSIO_N_SYNC_MASK, TSIO1_TSIO_N_SYNC_SHIFT);
607 _REG16_SET_MASK(&(_TSIOCtrl1->TSIO_SYNC_THRESHOLD), (u8Threshold-1), TSIO1_TSIO_SYNC_CNT_MASK, TSIO1_TSIO_SYNC_CNT_SHIFT);
608 }
609
HAL_TSIO_BypassMerge_Set(MS_BOOL bEnable)610 void HAL_TSIO_BypassMerge_Set(MS_BOOL bEnable)
611 {
612 if(bEnable)
613 {
614 _REG16_CLR(&(_TSIOCtrl3->TSIO_PKT_MERGE_CONFIG), TSIO3_NO_NEED_MERGE_BYPASS_SM);
615 _REG16_CLR(&(_TSIOCtrl3->TSIO_BYPASS_MERGE_DISABLE), TSIO3_BYPASS_MERGE_DIABLE);
616 }
617 else
618 {
619 _REG16_SET(&(_TSIOCtrl3->TSIO_PKT_MERGE_CONFIG), TSIO3_NO_NEED_MERGE_BYPASS_SM);
620 _REG16_SET(&(_TSIOCtrl3->TSIO_BYPASS_MERGE_DISABLE), TSIO3_BYPASS_MERGE_DIABLE);
621 }
622 }
623
HAL_TSIO_SIDBypassSMCMergeEnable(MS_U8 u8Sid,MS_BOOL bEnable)624 void HAL_TSIO_SIDBypassSMCMergeEnable(MS_U8 u8Sid, MS_BOOL bEnable)
625 {
626 MS_U16 u16SvidBypassSMCEnableBit[4];
627
628 u16SvidBypassSMCEnableBit[0] = _HAL_REG16_R(&(_TSIOCtrl3->TSIO_SVID_BYPASS_SMC_EN[0]));
629 u16SvidBypassSMCEnableBit[1] = _HAL_REG16_R(&(_TSIOCtrl3->TSIO_SVID_BYPASS_SMC_EN[1]));
630 u16SvidBypassSMCEnableBit[2] = _HAL_REG16_R(&(_TSIOCtrl3->TSIO_SVID_BYPASS_SMC_EN[2]));
631 u16SvidBypassSMCEnableBit[3] = _HAL_REG16_R(&(_TSIOCtrl3->TSIO_SVID_BYPASS_SMC_EN[3]));
632
633 MS_U64 u64Mask = 0;
634 MS_U64 u64Data = u16SvidBypassSMCEnableBit[0] + ((MS_U64)u16SvidBypassSMCEnableBit[1] << 16)
635 + ((MS_U64)u16SvidBypassSMCEnableBit[2] << 32) + ((MS_U64)u16SvidBypassSMCEnableBit[3] << 48);
636
637 if (bEnable)
638 {
639 u64Mask = (MS_U64)(0x1) << u8Sid;
640 u64Data |= u64Mask;
641 }
642 else
643 {
644 u64Mask = ~((MS_U64)(0x1) << u8Sid);
645 u64Data &= u64Mask;
646 }
647
648 u16SvidBypassSMCEnableBit[0] = (u64Data & 0x000000000000FFFF);
649 u16SvidBypassSMCEnableBit[1] = (u64Data & 0x00000000FFFF0000)>>16;
650 u16SvidBypassSMCEnableBit[2] = (u64Data & 0x0000FFFF00000000)>>32;
651 u16SvidBypassSMCEnableBit[3] = (u64Data & 0xFFFF000000000000)>>48;
652
653 _HAL_REG16_W(&(_TSIOCtrl3->TSIO_SVID_BYPASS_SMC_EN[0]), u16SvidBypassSMCEnableBit[0]);
654 _HAL_REG16_W(&(_TSIOCtrl3->TSIO_SVID_BYPASS_SMC_EN[1]), u16SvidBypassSMCEnableBit[1]);
655 _HAL_REG16_W(&(_TSIOCtrl3->TSIO_SVID_BYPASS_SMC_EN[2]), u16SvidBypassSMCEnableBit[2]);
656 _HAL_REG16_W(&(_TSIOCtrl3->TSIO_SVID_BYPASS_SMC_EN[3]), u16SvidBypassSMCEnableBit[3]);
657 }
658
HAL_TSIO_CTS_En(MS_BOOL bEnable)659 void HAL_TSIO_CTS_En(MS_BOOL bEnable)
660 {
661 if(bEnable)
662 {
663 _REG16_CLR(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_CTS_DISABLE);
664 }
665 else
666 {
667 _REG16_SET(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_CTS_DISABLE);
668 }
669 }
670
671 //=======================================================
672 // SGDMA_IN API
673 //=======================================================
HAL_TSIO_SGDMAIN_Reset(void)674 void HAL_TSIO_SGDMAIN_Reset(void)
675 {
676 _REG16_CLR(&(_TSOCtrl3->SW_RSTZ),TSO3_SW_RSTZ); //low active
677 _REG16_SET(&(_TSOCtrl3->SW_RSTZ),TSO3_SW_RSTZ);
678 }
679
HAL_TSIO_SGDMAIN_LastPktBuf_Set(MS_U32 u32Head,MS_U32 u32Tail)680 void HAL_TSIO_SGDMAIN_LastPktBuf_Set(MS_U32 u32Head, MS_U32 u32Tail)
681 {
682 _HAL_REG32_W(&(_TSOCtrl3->LAST_PKT_STR2MI_HEAD), (u32Head >> TSIO_MIU_BUS)&0xFFFFFFFF);
683 _HAL_REG32_W(&(_TSOCtrl3->LAST_PKT_STR2MI_TAIL), (u32Tail >> TSIO_MIU_BUS)&0xFFFFFFFF);
684
685 _REG16_SET(&(_TSOCtrl3->LAST_PKT),TSO3_LAST_PKT_STR2MI_RST_WADR);
686 _REG16_CLR(&(_TSOCtrl3->LAST_PKT),TSO3_LAST_PKT_STR2MI_RST_WADR);
687
688 _REG16_SET(&(_TSOCtrl3->LAST_PKT),TSO3_LAST_PKT_STR2MI_EN);
689 }
690
HAL_TSIO_SGDMAIN_SGVQBuf_Set(MS_U32 u32BufAddr,MS_U32 u32BufSize)691 void HAL_TSIO_SGDMAIN_SGVQBuf_Set(MS_U32 u32BufAddr, MS_U32 u32BufSize)
692 {
693 _HAL_REG32_W(&(_TSOCtrl3->SGVQ1_BASE), (u32BufAddr >> TSIO_MIU_BUS)&0xFFFFFFFF);
694 _HAL_REG16_W(&(_TSOCtrl3->SGVQ1_SIZE_200BYTE), (u32BufSize / TSIO_SVQ_UNIT_SIZE));
695
696 _REG16_SET(&(_TSOCtrl3->SGVQ1_TX_CONFIG), TSO3_TX_CONFIG_TX_RESET);
697 _REG16_CLR(&(_TSOCtrl3->SGVQ1_TX_CONFIG), TSO3_TX_CONFIG_TX_RESET);
698 _REG16_SET(&(_TSOCtrl3->SGVQ1_TX_CONFIG), TSO3_TX_CONFIG_SVQ_TX_ENABLE);
699 }
700
HAL_TSIO_SGDMAIN_VC_Open(MS_U32 u32Addr,MS_U8 u8Chid,MS_U8 u8Sid,MS_BOOL bTSmode,MS_BOOL bPriority,MS_BOOL bFlush,MS_BOOL bNewPkt)701 void HAL_TSIO_SGDMAIN_VC_Open(MS_U32 u32Addr, MS_U8 u8Chid, MS_U8 u8Sid, MS_BOOL bTSmode,
702 MS_BOOL bPriority, MS_BOOL bFlush, MS_BOOL bNewPkt)
703 {
704 //Set CMD
705 _REG16_SET_MASK(&(_TSOCtrl3->ACPU_CMD), u8Chid, TSO3_ACPU_CMD_ACPU_VC_ID_MASK, TSO3_ACPU_CMD_ACPU_VC_ID_SHIFT);
706 if (bNewPkt)
707 {
708 _REG16_SET(&(_TSOCtrl3->ACPU_CMD), TSO3_ACPU_CMD_START_A_NEW_PACKAGE);
709 }
710 else
711 {
712 _REG16_CLR(&(_TSOCtrl3->ACPU_CMD), TSO3_ACPU_CMD_START_A_NEW_PACKAGE);
713 }
714 _REG16_SET(&(_TSOCtrl3->ACPU_CMD), TSO3_ACPU_CMD_ACPU_RW);
715 _REG16_SET(&(_TSOCtrl3->ACPU_CMD), TSO3_ACPU_CMD_ACPU_ACTIVE);
716 if (bPriority)
717 {
718 _REG16_SET(&(_TSOCtrl3->ACPU_CMD), TSO3_ACPU_CMD_M_PRIORITY);
719 }
720 else
721 {
722 _REG16_CLR(&(_TSOCtrl3->ACPU_CMD), TSO3_ACPU_CMD_M_PRIORITY);
723 }
724
725 //Set FLAG
726 if (bTSmode)
727 {
728 _REG16_SET(&(_TSOCtrl3->ACPU_FLAG), TSO3_ACPU_FLAG_PKT_MODE_188);
729 }
730 else
731 {
732 _REG16_CLR(&(_TSOCtrl3->ACPU_FLAG), TSO3_ACPU_FLAG_PKT_MODE_188);
733 }
734 if (bFlush)
735 {
736 _REG16_SET(&(_TSOCtrl3->ACPU_FLAG), TSO3_ACPU_FLAG_LAST_NODE_FLUSH);
737 }
738 else
739 {
740 _REG16_CLR(&(_TSOCtrl3->ACPU_FLAG), TSO3_ACPU_FLAG_LAST_NODE_FLUSH);
741 }
742 _REG16_SET(&(_TSOCtrl3->ACPU_FLAG), TSO3_ACPU_FLAG_INTERRUPT_ENABLE);
743 _REG16_SET_MASK(&(_TSOCtrl3->ACPU_FLAG), u8Sid, TSO3_ACPU_FLAG_SERVICE_ID_MASK, TSO3_ACPU_FLAG_SERVICE_ID_SHIFT);
744
745 //Write Addr
746 _HAL_REG32_W(&(_TSOCtrl3->ACPU_WDATA), u32Addr);
747
748 //Trigger
749 _REG16_SET(&(_TSOCtrl3->ACPU_ACTIVE), TSO3_ACPU_ACTIVE);
750 }
751
HAL_TSIO_SGDMAIN_VC_Close(MS_U8 u8Chid)752 void HAL_TSIO_SGDMAIN_VC_Close(MS_U8 u8Chid)
753 {
754 //Set CMD
755 _REG16_SET_MASK(&(_TSOCtrl3->ACPU_CMD), u8Chid, TSO3_ACPU_CMD_ACPU_VC_ID_MASK, TSO3_ACPU_CMD_ACPU_VC_ID_SHIFT);
756 _REG16_SET(&(_TSOCtrl3->ACPU_CMD), TSO3_ACPU_CMD_ACPU_RW);
757 _REG16_CLR(&(_TSOCtrl3->ACPU_CMD), TSO3_ACPU_CMD_ACPU_ACTIVE);
758
759 //Trigger
760 _REG16_SET(&(_TSOCtrl3->ACPU_ACTIVE), TSO3_ACPU_ACTIVE);
761 }
762
HAL_TSIO_SGDMAIN_Global_Pacing(void)763 void HAL_TSIO_SGDMAIN_Global_Pacing(void)
764 {
765 //golobal tick unit, 192 = 1us
766 _REG16_SET_MASK(&(_TSOCtrl3->GLOBAL_TICK_COUNT_SET), 192, TSO3_GLOBAL_TICK_COUNT_SET_MASK, TSO3_GLOBAL_TICK_COUNT_SET_SHIFT);
767 }
768
HAL_TSIO_SGDMAIN_VC_Pacing(MS_U8 u8Chid,MS_BOOL bTSmode,MS_U32 Pacing)769 void HAL_TSIO_SGDMAIN_VC_Pacing(MS_U8 u8Chid, MS_BOOL bTSmode, MS_U32 Pacing)
770 {
771 if (Pacing == 0 || u8Chid >= TSIO_SERVICE_NUM)
772 {
773 return;
774 }
775
776 MS_U16 u16Wdata = 0;
777 if (bTSmode)
778 {
779 u16Wdata = (1000000/(Pacing /188 /8));
780 }
781 else
782 {
783 u16Wdata = (1000000/(Pacing /192 /8));
784 }
785
786 _REG16_SET_MASK(&(_TSOCtrl3->TICK_COUNT_SET[u8Chid]), u16Wdata, TSO3_TICK_COUNT_SET_MASK, TSO3_TICK_COUNT_SET_SHIFT);
787 }
788
HAL_TSIO_SGDMAIN_Start(void)789 void HAL_TSIO_SGDMAIN_Start(void)
790 {
791 _REG16_SET(&(_TSOCtrl3->SGCTRL_START), TSO3_SGCTRL_START);
792 }
793
HAL_TSIO_SGDMAIN_IntRead(MS_U8 u8Chid,MS_U16 * u16Status)794 void HAL_TSIO_SGDMAIN_IntRead(MS_U8 u8Chid, MS_U16 *u16Status)
795 {
796 MS_BOOL bINT = false;
797 MS_U64 VC_INT = (MS_U64)_HAL_REG16_R(&(_TSOCtrl3->SGDMA_IN_VC_INT[0]))+
798 ((MS_U64)_HAL_REG16_R(&(_TSOCtrl3->SGDMA_IN_VC_INT[1])) << 16)+
799 ((MS_U64)_HAL_REG16_R(&(_TSOCtrl3->SGDMA_IN_VC_INT[2])) << 32)+
800 ((MS_U64)_HAL_REG16_R(&(_TSOCtrl3->SGDMA_IN_VC_INT[3])) << 48);
801
802 bINT = (VC_INT & ((MS_U64)(0x1) << u8Chid)) >> u8Chid;
803 *u16Status = bINT;
804 }
805
HAL_TSIO_SGDMAIN_IntClr(MS_U8 u8Chid)806 void HAL_TSIO_SGDMAIN_IntClr(MS_U8 u8Chid)
807 {
808 _REG16_SET_MASK(&(_TSOCtrl3->PACE_DBG), u8Chid, TSO3_SGDMA_IN_VC_INT_VC_ID_MASK, TSO3_SGDMA_IN_VC_INT_VC_ID_SHIFT);
809 _REG16_SET(&(_TSOCtrl3->PACE_DBG), TSO3_SGDMA_IN_VC_INT_CLR);
810 _REG16_SET(&(_TSOCtrl3->SGDMA_IN), TSO3_SGDMA_IN_VC_INT_TRIGGER);
811 }
812
HAL_TSIO_SGDMAIN_IntAll(void)813 MS_U64 HAL_TSIO_SGDMAIN_IntAll(void)
814 {
815 MS_U64 VC_INT = (MS_U64)_HAL_REG16_R(&(_TSOCtrl3->SGDMA_IN_VC_INT[0]))+
816 ((MS_U64)_HAL_REG16_R(&(_TSOCtrl3->SGDMA_IN_VC_INT[1])) << 16)+
817 ((MS_U64)_HAL_REG16_R(&(_TSOCtrl3->SGDMA_IN_VC_INT[2])) << 32)+
818 ((MS_U64)_HAL_REG16_R(&(_TSOCtrl3->SGDMA_IN_VC_INT[3])) << 48);
819
820 return VC_INT;
821 }
822
HAL_TSIO_SGDMAIN_IntClrAll(void)823 void HAL_TSIO_SGDMAIN_IntClrAll(void)
824 {
825 _REG16_SET(&(_TSOCtrl3->SGDMA_IN), TSO3_SGDMA_IN_INT_CLR);
826 _REG16_CLR(&(_TSOCtrl3->SGDMA_IN), TSO3_SGDMA_IN_INT_CLR);
827 }
828
HAL_TSIO_SGDMAIN_ReadSram(MS_U8 u8Chid,HAL_SGDMA_SRAM eSram)829 MS_U32 HAL_TSIO_SGDMAIN_ReadSram(MS_U8 u8Chid, HAL_SGDMA_SRAM eSram)
830 {
831 MS_U32 u32Data = 0;
832 if (eSram >= HAL_SGDMA_SRAM_MAX)
833 {
834 return 0;
835 }
836
837 //Set cmd
838 _REG16_SET_MASK(&(_TSOCtrl3->ACPU_CMD), u8Chid, TSO3_ACPU_CMD_ACPU_VC_ID_MASK, TSO3_ACPU_CMD_ACPU_VC_ID_SHIFT);
839 _REG16_SET_MASK(&(_TSOCtrl3->ACPU_CMD), eSram, TSO3_ACPU_CMD_ACPU_POSITION_MASK, TSO3_ACPU_CMD_ACPU_POSITION_SHIFT);
840 _REG16_CLR(&(_TSOCtrl3->ACPU_CMD), TSO3_ACPU_CMD_ACPU_RW);
841 _REG16_CLR(&(_TSOCtrl3->ACPU_CMD), TSO3_ACPU_CMD_ACPU_ACTIVE);
842
843 //Trigger
844 _REG16_SET(&(_TSOCtrl3->ACPU_ACTIVE), TSO3_ACPU_ACTIVE);
845
846 u32Data = _HAL_REG32_R(&(_TSOCtrl3->ACPU_RDATA));
847 return u32Data;
848 }
849
HAL_TSIO_SGDMAIN_ReadDbg(HAL_SGDMAIN_DBG eDbg)850 MS_U16 HAL_TSIO_SGDMAIN_ReadDbg(HAL_SGDMAIN_DBG eDbg)
851 {
852 MS_U16 u16Data = 0;
853
854 if (eDbg >= HAL_SGDMAIN_DBG_MAX)
855 {
856 return 0;
857 }
858
859 _REG16_SET_MASK(&(_TSOCtrl3->SGDMA_IN), eDbg, TSO3_SGDMA_IN_DBG_SEL_MASK, TSO3_SGDMA_IN_DBG_SEL_SHIFT);
860 u16Data = _HAL_REG16_R(&(_TSOCtrl3->SGDMA_IN_DBG));
861 return u16Data;
862 }
863
HAL_TSIO_SGDMAIN_PidFltEnable(MS_U8 u8Sid,MS_BOOL bEnable)864 void HAL_TSIO_SGDMAIN_PidFltEnable(MS_U8 u8Sid, MS_BOOL bEnable)
865 {
866 MS_U16 u16PidFltEnableBit[4];
867
868 u16PidFltEnableBit[0] = _HAL_REG16_R(&(_TSOCtrl2->SG_PDFLT_SVID_EN[0]));
869 u16PidFltEnableBit[1] = _HAL_REG16_R(&(_TSOCtrl2->SG_PDFLT_SVID_EN[1]));
870 u16PidFltEnableBit[2] = _HAL_REG16_R(&(_TSOCtrl2->SG_PDFLT_SVID_EN[2]));
871 u16PidFltEnableBit[3] = _HAL_REG16_R(&(_TSOCtrl2->SG_PDFLT_SVID_EN[3]));
872
873 MS_U64 u64Mask = 0;
874 MS_U64 u64Data = u16PidFltEnableBit[0] + ((MS_U64)u16PidFltEnableBit[1] << 16)
875 + ((MS_U64)u16PidFltEnableBit[2] << 32) + ((MS_U64)u16PidFltEnableBit[3] << 48);
876
877 if (bEnable)
878 {
879 u64Mask = (MS_U64)(0x1) << u8Sid;
880 u64Data |= u64Mask;
881 }
882 else
883 {
884 u64Mask = ~((MS_U64)(0x1) << u8Sid);
885 u64Data &= u64Mask;
886 }
887
888 u16PidFltEnableBit[0] = (u64Data & 0x000000000000FFFF);
889 u16PidFltEnableBit[1] = (u64Data & 0x00000000FFFF0000)>>16;
890 u16PidFltEnableBit[2] = (u64Data & 0x0000FFFF00000000)>>32;
891 u16PidFltEnableBit[3] = (u64Data & 0xFFFF000000000000)>>48;
892
893 _HAL_REG16_W(&(_TSOCtrl2->SG_PDFLT_SVID_EN[0]), u16PidFltEnableBit[0]);
894 _HAL_REG16_W(&(_TSOCtrl2->SG_PDFLT_SVID_EN[1]), u16PidFltEnableBit[1]);
895 _HAL_REG16_W(&(_TSOCtrl2->SG_PDFLT_SVID_EN[2]), u16PidFltEnableBit[2]);
896 _HAL_REG16_W(&(_TSOCtrl2->SG_PDFLT_SVID_EN[3]), u16PidFltEnableBit[3]);
897 }
898
_HAL_TSIO_SGDMAIN_PageTableIndW(MS_U32 u32Addr,MS_U32 u32Wdata)899 static void _HAL_TSIO_SGDMAIN_PageTableIndW(MS_U32 u32Addr, MS_U32 u32Wdata)
900 {
901 // addr
902 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
903 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_ADDR_H), (u32Addr >> 16));
904
905 // Wdata
906 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_WDATA_L), (u32Wdata & 0x0000FFFF));
907 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_WDATA_H), (u32Wdata >> 16));
908
909 // Wen
910 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_EN), TSO0_PDTABLE_W_EN);
911 }
912
_HAL_TSIO_SGDMAIN_PageTableIndR_H(MS_U32 u32Addr)913 static MS_U16 _HAL_TSIO_SGDMAIN_PageTableIndR_H(MS_U32 u32Addr)
914 {
915 // addr
916 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
917 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_ADDR_H), (u32Addr >> 16));
918
919 // Ren
920 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_EN), TSO0_PDTABLE_R_EN);
921
922 // Rdata
923 return _HAL_REG16_R(&(_TSOCtrl2->SG_PDTABLE_RDATA_H));
924 }
925
_HAL_TSIO_SGDMAIN_PageTableIndR(MS_U32 u32Addr)926 static MS_U16 _HAL_TSIO_SGDMAIN_PageTableIndR(MS_U32 u32Addr)
927 {
928 // addr
929 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
930 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_ADDR_H), (u32Addr >> 16));
931
932 // Ren
933 _HAL_REG16_W(&(_TSOCtrl0->PDTABLE_EN), TSO0_PDTABLE_R_EN);
934
935 // Rdata
936 return _HAL_REG16_R(&(_TSOCtrl2->SG_PDTABLE_RDATA));
937 }
938
HAL_TSIO_SGDMAIN_Flt_SetPid(MS_U16 u16FltId,MS_U16 u16PID)939 void HAL_TSIO_SGDMAIN_Flt_SetPid(MS_U16 u16FltId, MS_U16 u16PID)
940 {
941 MS_U32 u32Temp = 0;
942
943 u32Temp = TSO0_ONE_MASK + (MS_U32)(u16PID & TSO0_PID_MASK);
944 u32Temp |= (MS_U32)((_HAL_TSIO_SGDMAIN_PageTableIndR_H(_TSIO_SGDMAIN_PIDFLT_ADDR(u16FltId))&TSO2_PDTABLE_RDATA_H_MASK)<<16);
945 _HAL_TSIO_SGDMAIN_PageTableIndW(_TSIO_SGDMAIN_PIDFLT_ADDR(u16FltId), u32Temp);
946 }
947
HAL_TSIO_SGDMAIN_Flt_SetSid(MS_U16 u16FltId,MS_U8 u8Sid)948 void HAL_TSIO_SGDMAIN_Flt_SetSid(MS_U16 u16FltId, MS_U8 u8Sid)
949 {
950 MS_U32 u32Temp = 0;
951
952 u32Temp = (((MS_U32)u8Sid<<TSO0_SVID_SHIFT) & TSO0_SVID_MASK);
953 u32Temp |= (MS_U32)_HAL_TSIO_SGDMAIN_PageTableIndR(_TSIO_SGDMAIN_PIDFLT_ADDR(u16FltId));
954 _HAL_TSIO_SGDMAIN_PageTableIndW(_TSIO_SGDMAIN_PIDFLT_ADDR(u16FltId), u32Temp);
955 }
956
HAL_TSIO_SGDMAIN_Pause(MS_BOOL bEnable)957 void HAL_TSIO_SGDMAIN_Pause(MS_BOOL bEnable)
958 {
959 if (bEnable)
960 {
961 _REG16_SET(&(_TSOCtrl3->SGDMA_IN), TSO3_SGDMA_IN_PAUSE);
962 }
963 else
964 {
965 _REG16_CLR(&(_TSOCtrl3->SGDMA_IN), TSO3_SGDMA_IN_PAUSE);
966 }
967 }
968
969 //=======================================================
970 // SGDMA_OUT API
971 //=======================================================
HAL_TSIO_SGDMAOUT_Init(void)972 void HAL_TSIO_SGDMAOUT_Init(void)
973 {
974 _REG16_CLR(&(_TSIOCtrl2->TSIO_PVR_CONFIG), TSIO2_PVR_STR2MI_EN);
975 _REG16_SET(&(_TSIOCtrl2->TSIO_PVR_CONFIG), TSIO2_PVR_STR2MI_RST_WADR);
976 _REG16_CLR(&(_TSIOCtrl2->TSIO_PVR_CONFIG), TSIO2_PVR_STR2MI_RST_WADR);
977 _REG16_SET_MASK(&(_TSIOCtrl2->TSIO_PVR_CONFIG), 1, TSIO2_PVR_BURST_LEN_MASK, TSIO2_PVR_BURST_LEN_SHIFT); // for fixed ccp error
978 _REG16_SET(&(_TSIOCtrl2->TSIO_PVR_CONFIG), TSIO2_PVR_DMA_FLUSH_EN); // for fixed ccp error
979 _REG16_SET(&(_TSIOCtrl2->TSIO_PVR_CONFIG), TSIO2_PVR_STR2MI_EN);
980 }
981
HAL_TSIO_SGDMAOUT_VC_Open(MS_U32 u32Addr,MS_U8 u8Chid,MS_BOOL bSecurity)982 void HAL_TSIO_SGDMAOUT_VC_Open(MS_U32 u32Addr, MS_U8 u8Chid, MS_BOOL bSecurity)
983 {
984 //Set cmd
985 _REG16_SET_MASK(&(_TSIOCtrl2->ACPU_CMD), u8Chid, TSIO2_ACPU_CMD_VC_ID_MASK, TSIO2_ACPU_CMD_VC_ID_SHIFT);
986 _REG16_SET(&(_TSIOCtrl2->ACPU_CMD), TSIO2_ACPU_CMD_CLR);
987 _REG16_SET(&(_TSIOCtrl2->ACPU_CMD), TSIO2_ACPU_CMD_RW);
988 _REG16_SET(&(_TSIOCtrl2->ACPU_CMD), TSIO2_ACPU_CMD_ACTIVE);
989
990 //Set flag
991 _REG16_SET(&(_TSIOCtrl2->ACPU_FLAG), TSIO2_ACPU_FLAG_INTERRUPT_ENABLE);
992 _REG16_SET_MASK(&(_TSIOCtrl2->ACPU_FLAG), 0x18, TSIO2_ACPU_FLAG_MOBF_MASK, TSIO2_ACPU_FLAG_MOBF_SHIFT);
993 if (bSecurity)
994 {
995 _REG16_SET(&(_TSIOCtrl2->ACPU_FLAG), TSIO2_ACPU_FLAG_SECURE_FLAG);
996 }
997 else
998 {
999 _REG16_CLR(&(_TSIOCtrl2->ACPU_FLAG), TSIO2_ACPU_FLAG_SECURE_FLAG);
1000 }
1001 _REG16_SET(&(_TSIOCtrl2->ACPU_FLAG), TSIO2_ACPU_FLAG_DMA_END_CONTINUE_DMA);
1002
1003 //Write Addr
1004 _HAL_REG32_W(&(_TSIOCtrl2->ACPU_WDATA), u32Addr);
1005
1006 //Trigger
1007 _REG16_SET(&(_TSIOCtrl2->ACPU_ACTIVE), TSIO2_ACPU_ACTIVE);
1008 }
1009
HAL_TSIO_SGDMAOUT_VC_Close(MS_U8 u8Chid)1010 void HAL_TSIO_SGDMAOUT_VC_Close(MS_U8 u8Chid)
1011 {
1012 //Set cmd
1013 _REG16_SET_MASK(&(_TSIOCtrl2->ACPU_CMD), u8Chid, TSIO2_ACPU_CMD_VC_ID_MASK, TSIO2_ACPU_CMD_VC_ID_SHIFT);
1014 _REG16_SET(&(_TSIOCtrl2->ACPU_CMD), TSIO2_ACPU_CMD_RW);
1015 _REG16_SET(&(_TSIOCtrl2->ACPU_CMD), TSIO2_ACPU_CMD_CLR);
1016 _REG16_CLR(&(_TSIOCtrl2->ACPU_CMD), TSIO2_ACPU_CMD_ACTIVE);
1017
1018 //Trigger
1019 _REG16_SET(&(_TSIOCtrl2->ACPU_ACTIVE), TSIO2_ACPU_ACTIVE);
1020 }
1021
HAL_TSIO_SGDMAOUT_Start(void)1022 void HAL_TSIO_SGDMAOUT_Start(void)
1023 {
1024 _REG16_SET(&(_TSIOCtrl2->VCFSM_START), TSIO2_VCFSM_START);
1025 }
1026
HAL_TSIO_SGDMAOUT_IntRead(MS_U8 u8Chid,MS_U16 * u16Status)1027 void HAL_TSIO_SGDMAOUT_IntRead(MS_U8 u8Chid, MS_U16 *u16Status)
1028 {
1029 MS_BOOL bINT = false;
1030 MS_U64 VC_INT = (MS_U64)_HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_VC_INT[0]))+
1031 ((MS_U64)_HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_VC_INT[1])) << 16)+
1032 ((MS_U64)_HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_VC_INT[2])) << 32)+
1033 ((MS_U64)_HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_VC_INT[3])) << 48);
1034
1035 bINT = (VC_INT & ((MS_U64)(0x1) << u8Chid)) >> u8Chid;
1036 if (bINT)
1037 {
1038 _REG16_SET_MASK(&(_TSIOCtrl2->SGDMA_OUT_VC_STATUS_SEL), u8Chid, TSIO2_SGDMA_OUT_VC_STATUS_SEL_MASK, TSIO2_SGDMA_OUT_VC_STATUS_SEL_SHIFT);
1039 *u16Status = _HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_VC_STATUS));
1040 }
1041 else
1042 {
1043 *u16Status = 0;
1044 }
1045 }
1046
HAL_TSIO_SGDMAOUT_IntRead_2(MS_U8 u8Chid,MS_U16 * u16Status)1047 void HAL_TSIO_SGDMAOUT_IntRead_2(MS_U8 u8Chid, MS_U16 *u16Status)
1048 {
1049 _REG16_SET_MASK(&(_TSIOCtrl2->SGDMA_OUT_VC_STATUS_SEL), u8Chid, TSIO2_SGDMA_OUT_VC_STATUS_SEL_MASK, TSIO2_SGDMA_OUT_VC_STATUS_SEL_SHIFT);
1050 *u16Status = _HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_VC_STATUS));
1051 }
1052
HAL_TSIO_SGDMAOUT_IntClr(MS_U8 u8Chid)1053 void HAL_TSIO_SGDMAOUT_IntClr(MS_U8 u8Chid)
1054 {
1055 _REG16_SET_MASK(&(_TSIOCtrl2->SGDMA_OUT_INFO), u8Chid, TSIO2_SGDMA_OUT_VC_INT_VC_ID_MASK, TSIO2_SGDMA_OUT_VC_INT_VC_ID_SHIFT);
1056 _REG16_SET(&(_TSIOCtrl2->SGDMA_OUT_INFO), TSIO2_SGDMA_OUT_VC_INT_CLR);
1057 _REG16_SET(&(_TSIOCtrl2->SGDMA_OUT_CTRL), TSIO2_SGDMA_OUT_VC_INT_TRIGGER);
1058 }
1059
HAL_TSIO_SGDMAOUT_IntAll(void)1060 MS_U64 HAL_TSIO_SGDMAOUT_IntAll(void)
1061 {
1062 MS_U64 VC_INT = (MS_U64)_HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_VC_INT[0]))+
1063 ((MS_U64)_HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_VC_INT[1])) << 16)+
1064 ((MS_U64)_HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_VC_INT[2])) << 32)+
1065 ((MS_U64)_HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_VC_INT[3])) << 48);
1066
1067 return VC_INT;
1068 }
1069
HAL_TSIO_SGDMAOUT_IntClrAll(void)1070 void HAL_TSIO_SGDMAOUT_IntClrAll(void)
1071 {
1072 _REG16_SET(&(_TSIOCtrl2->SGDMA_OUT_CTRL), TSIO2_SGDMA_OUT_INT_CLR);
1073 _REG16_CLR(&(_TSIOCtrl2->SGDMA_OUT_CTRL), TSIO2_SGDMA_OUT_INT_CLR);
1074 }
1075
HAL_TSIO_SGDMAOUT_ReadSram(MS_U8 u8Chid,HAL_SGDMA_SRAM eSram,MS_BOOL bLSB)1076 MS_U32 HAL_TSIO_SGDMAOUT_ReadSram(MS_U8 u8Chid, HAL_SGDMA_SRAM eSram, MS_BOOL bLSB)
1077 {
1078 MS_U32 u32Data = 0;
1079 if (eSram >= HAL_SGDMA_SRAM_MAX)
1080 {
1081 return 0;
1082 }
1083
1084 //Set cmd
1085 _REG16_SET_MASK(&(_TSIOCtrl2->ACPU_CMD), u8Chid, TSIO2_ACPU_CMD_VC_ID_MASK, TSIO2_ACPU_CMD_VC_ID_SHIFT);
1086 _REG16_SET_MASK(&(_TSIOCtrl2->ACPU_CMD), eSram, TSIO2_ACPU_CMD_RD_POSITION_MASK, TSIO2_ACPU_CMD_RD_POSITION_SHIFT);
1087 _REG16_CLR(&(_TSIOCtrl2->ACPU_CMD), TSIO2_ACPU_CMD_RW);
1088 _REG16_CLR(&(_TSIOCtrl2->ACPU_CMD), TSIO2_ACPU_CMD_ACTIVE);
1089 if (bLSB)
1090 {
1091 _REG16_SET(&(_TSIOCtrl2->ACPU_CMD), TSIO2_ACPU_CMD_RD_ADDR_LSB);
1092 }
1093 else
1094 {
1095 _REG16_CLR(&(_TSIOCtrl2->ACPU_CMD), TSIO2_ACPU_CMD_RD_ADDR_LSB);
1096 }
1097
1098 //Trigger
1099 _REG16_SET(&(_TSIOCtrl2->ACPU_ACTIVE), TSIO2_ACPU_ACTIVE);
1100
1101 u32Data = _HAL_REG32_R(&(_TSIOCtrl2->ACPU_RDATA));
1102 return u32Data;
1103 }
1104
HAL_TSIO_SGDMAOUT_ReadDbg(HAL_SGDMAOUT_DBG eDbg)1105 MS_U16 HAL_TSIO_SGDMAOUT_ReadDbg(HAL_SGDMAOUT_DBG eDbg)
1106 {
1107 MS_U16 u16Data = 0;
1108
1109 if (eDbg >= HAL_SGDMAOUT_DBG_MAX)
1110 {
1111 return 0;
1112 }
1113
1114 _REG16_SET_MASK(&(_TSIOCtrl2->SGDMA_OUT_CTRL), eDbg, TSIO2_SGDMA_OUT_DBG_SEL_MASK, TSIO2_SGDMA_OUT_DBG_SEL_SHIFT);
1115 u16Data = _HAL_REG16_R(&(_TSIOCtrl2->SGDMA_OUT_DBG));
1116 return u16Data;
1117 }
1118
HAL_TSIO_SGDMAOUT_Pause(MS_BOOL bEnable)1119 void HAL_TSIO_SGDMAOUT_Pause(MS_BOOL bEnable)
1120 {
1121 if (bEnable)
1122 {
1123 _REG16_SET(&(_TSIOCtrl2->SGDMA_OUT_CTRL), TSIO2_SGDMA_OUT_PAUSE);
1124 }
1125 else
1126 {
1127 _REG16_CLR(&(_TSIOCtrl2->SGDMA_OUT_CTRL), TSIO2_SGDMA_OUT_PAUSE);
1128 }
1129 }
1130
1131 //=======================================================
1132 // SVID table API
1133 //=======================================================
HAL_TSIO_SVIDTBL_Set(MS_U8 u8Tblid,MS_U8 u8Sid,MS_U8 u8Sourceid,MS_BOOL bLive)1134 void HAL_TSIO_SVIDTBL_Set(MS_U8 u8Tblid, MS_U8 u8Sid, MS_U8 u8Sourceid, MS_BOOL bLive)
1135 {
1136 if (u8Tblid >= TSIO_SERVICE_NUM)
1137 {
1138 return;
1139 }
1140
1141 _REG16_SET_MASK(&(_TSIOCtrl1->SVID_SRCID[u8Tblid]), u8Sourceid, TSIO1_SOURCE_ID_MASK, TSIO1_SOURCE_ID_SHIFT);
1142 _REG16_SET_MASK(&(_TSIOCtrl1->SVID_SRCID[u8Tblid]), u8Sid, TSIO1_SERVICE_ID_MASK, TSIO1_SERVICE_ID_SHIFT);
1143
1144 MS_U8 u8Addr = u8Tblid / 8;
1145 MS_U16 u16Shift = 0 ;
1146 switch ((u8Tblid%8))
1147 {
1148 case 0:
1149 u16Shift = TSIO1_LIVE_0_ENABLE;
1150 break;
1151 case 1:
1152 u16Shift = TSIO1_LIVE_1_ENABLE;
1153 break;
1154 case 2:
1155 u16Shift = TSIO1_LIVE_2_ENABLE;
1156 break;
1157 case 3:
1158 u16Shift = TSIO1_LIVE_3_ENABLE;
1159 break;
1160 case 4:
1161 u16Shift = TSIO1_LIVE_4_ENABLE;
1162 break;
1163 case 5:
1164 u16Shift = TSIO1_LIVE_5_ENABLE;
1165 break;
1166 case 6:
1167 u16Shift = TSIO1_LIVE_6_ENABLE;
1168 break;
1169 case 7:
1170 u16Shift = TSIO1_LIVE_7_ENABLE;
1171 default:
1172 break;
1173 }
1174
1175 if (bLive)
1176 {
1177 _REG16_SET(&(_TSIOCtrl1->SVID_INFO[u8Addr]), u16Shift);
1178 }
1179 else
1180 {
1181 _REG16_CLR(&(_TSIOCtrl1->SVID_INFO[u8Addr]), u16Shift);
1182 }
1183 _REG16_SET(&(_TSIOCtrl1->SVID_SRCID[u8Tblid]), TSIO1_ENABLE);
1184 }
1185
1186 //=======================================================
1187 // CC API
1188 //=======================================================
1189
HAL_TSIO_CC_RxClr(void)1190 void HAL_TSIO_CC_RxClr(void)
1191 {
1192 _REG16_SET(&(_TSIOCtrl0->RX_CC_CNTRL), TSIO0_RX_CC_CLR);
1193 _REG16_CLR(&(_TSIOCtrl0->RX_CC_CNTRL), TSIO0_RX_CC_CLR);
1194 }
1195
HAL_TSIO_CC_RxIntClr(void)1196 void HAL_TSIO_CC_RxIntClr(void)
1197 {
1198 _REG16_CLR(&(_TSIOCtrl0->RX_CC_CNTRL), TSIO0_RX_CC_RECEIVE_EN);
1199 _REG16_SET(&(_TSIOCtrl0->RX_CC_CNTRL), TSIO0_RX_CC_INT_CLR);
1200 _REG16_CLR(&(_TSIOCtrl0->RX_CC_CNTRL), TSIO0_RX_CC_INT_CLR);
1201 }
1202
HAL_TSIO_CC_RxEnable(MS_BOOL bEnable)1203 void HAL_TSIO_CC_RxEnable(MS_BOOL bEnable)
1204 {
1205 if (bEnable)
1206 {
1207 _REG16_SET(&(_TSIOCtrl0->RX_CC_CNTRL), TSIO0_RX_CC_INT_EN);
1208 _REG16_SET_MASK(&(_TSIOCtrl0->RX_CC_CNTRL),0xFF,TSIO0_RX_ERR_INT_EN_MASK,TSIO0_RX_ERR_INT_EN_SHIFT);
1209 _REG16_SET(&(_TSIOCtrl0->RX_CC_CNTRL), TSIO0_RX_CC_RECEIVE_EN);
1210 }
1211 else
1212 {
1213 _REG16_SET(&(_TSIOCtrl0->RX_CC_CNTRL), TSIO0_RX_CC_CLR);
1214 _REG16_CLR(&(_TSIOCtrl0->RX_CC_CNTRL), TSIO0_RX_CC_CLR);
1215 _REG16_CLR(&(_TSIOCtrl0->RX_CC_CNTRL), TSIO0_RX_CC_RECEIVE_EN);
1216 }
1217 }
1218
HAL_TSIO_CC_RxInt(void)1219 MS_BOOL HAL_TSIO_CC_RxInt(void)
1220 {
1221 MS_BOOL bRet = FALSE;
1222 if ((_HAL_REG16_R(&(_TSIOCtrl0->RX_CC_STATUS)) & TSIO0_INT_RX_CC) == TSIO0_INT_RX_CC)
1223 {
1224 bRet = TRUE;
1225 }
1226 return bRet;
1227 }
1228
HAL_TSIO_CC_RxErrStatus(void)1229 MS_U16 HAL_TSIO_CC_RxErrStatus(void)
1230 {
1231 return (_HAL_REG16_R(&(_TSIOCtrl0->RX_CC_STATUS)) & TSIO0_ERR_FLAG_MASK);
1232 }
1233
HAL_TSIO_CC_RxReadSize(void)1234 MS_U16 HAL_TSIO_CC_RxReadSize(void)
1235 {
1236 return (_HAL_REG16_R(&(_TSIOCtrl0->RX_CC_SIZE)) & TSIO0_RX_CC_SIZE_MASK);
1237 }
1238
HAL_TSIO_CC_RxReadData(MS_U8 u8Addr)1239 MS_U32 HAL_TSIO_CC_RxReadData(MS_U8 u8Addr)
1240 {
1241 _REG16_SET_MASK(&(_TSIOCtrl0->RX_CC_CNTRL2),u8Addr,TSIO0_RX_ACPU_ADDR_MASK,TSIO0_RX_ACPU_ADDR_SHIFT);
1242 _REG16_SET(&(_TSIOCtrl0->RX_CC_CNTRL2),TSIO0_RX_ACPU_ST);
1243 _REG16_CLR(&(_TSIOCtrl0->RX_CC_CNTRL2),TSIO0_RX_ACPU_ST);
1244
1245 return _HAL_REG32_R(&(_TSIOCtrl0->RX_CC_RDATA));
1246 }
1247
HAL_TSIO_CC_RxReadData_Fast(MS_U8 u8Addr)1248 MS_U32 HAL_TSIO_CC_RxReadData_Fast(MS_U8 u8Addr)
1249 {
1250 _REG16_SET(&(_TSIOCtrl0->RX_CC_CNTRL2),TSIO0_RX_ACPU_ADDR_CONT_TRI);
1251 _REG16_SET_MASK(&(_TSIOCtrl0->RX_CC_CNTRL2),u8Addr,TSIO0_RX_ACPU_ADDR_MASK,TSIO0_RX_ACPU_ADDR_SHIFT);
1252 _REG16_SET(&(_TSIOCtrl0->RX_CC_CNTRL2),TSIO0_RX_ACPU_CONT);
1253
1254 return _HAL_REG32_R(&(_TSIOCtrl0->RX_CC_RDATA));
1255 }
1256
HAL_TSIO_CC_RxReadData_FastEnable(MS_BOOL bEnable)1257 void HAL_TSIO_CC_RxReadData_FastEnable(MS_BOOL bEnable)
1258 {
1259 if (bEnable)
1260 {
1261 _REG16_SET_MASK(&(_TSIOCtrl0->RX_CC_CNTRL2),0,TSIO0_RX_ACPU_ADDR_MASK,TSIO0_RX_ACPU_ADDR_SHIFT);
1262 _REG16_SET(&(_TSIOCtrl0->RX_CC_CNTRL2),TSIO0_RX_ACPU_CONT);
1263 _REG16_SET(&(_TSIOCtrl0->RX_CC_CNTRL2),TSIO0_RX_ACPU_ST);
1264 }
1265 else
1266 {
1267 _REG16_CLR(&(_TSIOCtrl0->RX_CC_CNTRL2),TSIO0_RX_ACPU_CONT);
1268 _REG16_CLR(&(_TSIOCtrl0->RX_CC_CNTRL2),TSIO0_RX_ACPU_ST);
1269 }
1270 }
1271
HAL_TSIO_CC_TxClr(void)1272 void HAL_TSIO_CC_TxClr(void)
1273 {
1274 _REG16_SET(&(_TSIOCtrl0->TX_CC_CNTRL), TSIO0_TX_CC_CLR);
1275 _REG16_CLR(&(_TSIOCtrl0->TX_CC_CNTRL), TSIO0_TX_CC_CLR);
1276 }
1277
HAL_TSIO_CC_TxIntClr(void)1278 void HAL_TSIO_CC_TxIntClr(void)
1279 {
1280 _REG16_SET(&(_TSIOCtrl0->TX_CC_CNTRL), TSIO0_TX_CC_INT_CLR);
1281 _REG16_CLR(&(_TSIOCtrl0->TX_CC_CNTRL), TSIO0_TX_CC_INT_CLR);
1282 }
1283
HAL_TSIO_CC_TxEnable(MS_BOOL bEnable)1284 void HAL_TSIO_CC_TxEnable(MS_BOOL bEnable)
1285 {
1286 if (bEnable)
1287 {
1288 _REG16_SET(&(_TSIOCtrl0->TX_CC_CNTRL), TSIO0_TX_CC_INT_EN);
1289 _REG16_SET(&(_TSIOCtrl0->TX_CC_CNTRL), TSIO0_TX_CC_START);
1290 }
1291 else
1292 {
1293 _REG16_SET(&(_TSIOCtrl0->TX_CC_CNTRL), TSIO0_TX_CC_CLR);
1294 _REG16_CLR(&(_TSIOCtrl0->TX_CC_CNTRL), TSIO0_TX_CC_CLR);
1295 _REG16_CLR(&(_TSIOCtrl0->TX_CC_CNTRL), TSIO0_TX_CC_START);
1296 }
1297 }
1298
HAL_TSIO_CC_TxWriteData(MS_U8 u8Addr,MS_U32 u32Data)1299 void HAL_TSIO_CC_TxWriteData(MS_U8 u8Addr, MS_U32 u32Data)
1300 {
1301 _HAL_REG32_W(&(_TSIOCtrl0->TX_CC_WDATA), u32Data);
1302 _REG16_SET_MASK(&(_TSIOCtrl0->TX_CC_CNTRL2),u8Addr,TSIO0_TX_ACPU_ADDR_MASK,TSIO0_TX_ACPU_ADDR_SHIFT);
1303 _REG16_SET(&(_TSIOCtrl0->TX_CC_CNTRL2),TSIO0_TX_ACPU_RW);
1304 _REG16_SET(&(_TSIOCtrl0->TX_CC_CNTRL2),TSIO0_TX_ACPU_ST);
1305 _REG16_SET_MASK(&(_TSIOCtrl0->TX_CC_CNTRL2),0x00,TSIO0_TX_ACPU_ADDR_MASK,TSIO0_TX_ACPU_ADDR_SHIFT);
1306 _REG16_CLR(&(_TSIOCtrl0->TX_CC_CNTRL2),TSIO0_TX_ACPU_ST);
1307 }
1308
HAL_TSIO_CC_TxWriteData_Fast(MS_U32 u32Data)1309 void HAL_TSIO_CC_TxWriteData_Fast(MS_U32 u32Data)
1310 {
1311 _HAL_REG32_W(&(_TSIOCtrl0->TX_CC_WDATA), u32Data);
1312 }
1313
HAL_TSIO_CC_TxWriteData_FastEnable(MS_BOOL bEnable)1314 void HAL_TSIO_CC_TxWriteData_FastEnable(MS_BOOL bEnable)
1315 {
1316 if (bEnable)
1317 {
1318 _REG16_SET_MASK(&(_TSIOCtrl0->TX_CC_CNTRL2),0,TSIO0_TX_ACPU_ADDR_MASK,TSIO0_TX_ACPU_ADDR_SHIFT);
1319 _REG16_SET(&(_TSIOCtrl0->TX_CC_CNTRL2),TSIO0_TX_ACPU_CONT);
1320 _REG16_SET(&(_TSIOCtrl0->TX_CC_CNTRL2),TSIO0_TX_ACPU_RW);
1321 _REG16_SET(&(_TSIOCtrl0->TX_CC_CNTRL2),TSIO0_TX_ACPU_ST);
1322 }
1323 else
1324 {
1325 _REG16_CLR(&(_TSIOCtrl0->TX_CC_CNTRL2),TSIO0_TX_ACPU_CONT);
1326 _REG16_CLR(&(_TSIOCtrl0->TX_CC_CNTRL2),TSIO0_TX_ACPU_ST);
1327 }
1328 }
1329
HAL_TSIO_CC_TxWriteSize(MS_U16 u16Size)1330 void HAL_TSIO_CC_TxWriteSize(MS_U16 u16Size)
1331 {
1332 _REG16_SET_MASK(&(_TSIOCtrl0->TX_CC_SIZE),u16Size,TSIO0_CC_SIZE_MASK,TSIO0_CC_SIZE_SHIFT);
1333 }
1334
HAL_TSIO_CC_TxInt(void)1335 MS_BOOL HAL_TSIO_CC_TxInt(void)
1336 {
1337 MS_BOOL bRet = FALSE;
1338 if ((_HAL_REG16_R(&(_TSIOCtrl0->TX_CC_STATUS)) & TSIO0_TX_CC_STATUS_INT_TX_CC) == TSIO0_TX_CC_STATUS_INT_TX_CC)
1339 {
1340 bRet = TRUE;
1341 }
1342 return bRet;
1343 }
1344
1345 //=======================================================
1346 // Loc Decrypt API
1347 //=======================================================
1348
HAL_TSIO_LOCDEC_Xiu_Lock(MS_U8 u8Xiu)1349 void HAL_TSIO_LOCDEC_Xiu_Lock(MS_U8 u8Xiu)
1350 {
1351 _REG16_SET_MASK(&(_TSIOCtrlLOCDEC->XIU),u8Xiu,TSIO_LOCDEC_XIU_ID_MASK,TSIO_LOCDEC_XIU_ID_SHIFT);
1352 }
1353
HAL_TSIO_LOCDEC_Xiu_Unlock(void)1354 void HAL_TSIO_LOCDEC_Xiu_Unlock(void)
1355 {
1356 _REG16_SET_MASK(&(_TSIOCtrlLOCDEC->XIU),0,TSIO_LOCDEC_XIU_ID_MASK,TSIO_LOCDEC_XIU_ID_SHIFT);
1357 }
1358
HAL_TSIO_LOCDEC_ScbFixRule(MS_BOOL bEnable)1359 void HAL_TSIO_LOCDEC_ScbFixRule(MS_BOOL bEnable)
1360 {
1361 if (bEnable)
1362 {
1363 _REG16_SET(&(_TSIOCtrlLOCDEC->SCBFIXRULE),TSIO_LOCDEC_SCBFIXRULE);
1364 }
1365 else
1366 {
1367 _REG16_CLR(&(_TSIOCtrlLOCDEC->SCBFIXRULE),TSIO_LOCDEC_SCBFIXRULE);
1368 }
1369 }
1370
HAL_TSIO_LOCDEC_Key_Set(MS_U8 u8Sid,MS_U8 * pKey,MS_U16 u16KeySize,MS_BOOL bOddKey)1371 MS_BOOL HAL_TSIO_LOCDEC_Key_Set( MS_U8 u8Sid, MS_U8 *pKey, MS_U16 u16KeySize, MS_BOOL bOddKey)
1372 {
1373 MS_U16 u16Data = 0;
1374 MS_S16 index = 0;
1375 MS_U8 addr = 0;
1376
1377 if (pKey == NULL || u16KeySize != TSIO_LOCDEC_KEY_LEN)
1378 {
1379 return FALSE;
1380 }
1381
1382 for (index = TSIO_LOCDEC_KEY_LEN-1; index >= 0; index-=2)
1383 {
1384 u16Data = (pKey[index-1]<<8) + pKey[index];
1385 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->SW_KEY[addr]),u16Data);
1386 addr++;
1387 }
1388
1389 _REG16_SET_MASK(&(_TSIOCtrlLOCDEC->CMD),u8Sid,TSIO_LOCDEC_CMD_SERVICE_ID_MASK,TSIO_LOCDEC_CMD_SERVICE_ID_SHIFT);
1390
1391 if (bOddKey)
1392 {
1393 _REG16_SET(&(_TSIOCtrlLOCDEC->CMD), TSIO_LOCDEC_CMD_KEY_SEL);
1394 }
1395 else
1396 {
1397 _REG16_CLR(&(_TSIOCtrlLOCDEC->CMD), TSIO_LOCDEC_CMD_KEY_SEL);
1398 }
1399
1400 _REG16_SET(&(_TSIOCtrlLOCDEC->CMD), TSIO_LOCDEC_CMD_CMD);
1401 _REG16_SET(&(_TSIOCtrlLOCDEC->KT_GO), TSIO_LOCDEC_KT_GO);
1402
1403 return TRUE;
1404 }
1405
HAL_TSIO_LOCDEC_KeySetDone(void)1406 MS_BOOL HAL_TSIO_LOCDEC_KeySetDone(void)
1407 {
1408 return (_HAL_REG16_R(&(_TSIOCtrlLOCDEC->KT_DONE)) & TSIO_LOCDEC_KT_DONE);
1409 }
1410
HAL_TSIO_LOCDEC_KeyEnable(MS_U8 u8Sid,MS_BOOL bEnable)1411 void HAL_TSIO_LOCDEC_KeyEnable(MS_U8 u8Sid, MS_BOOL bEnable)
1412 {
1413 MS_U16 u16KeyEnableBit[4];
1414
1415 u16KeyEnableBit[0] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->KEY_ENABLE_BIT[0]));
1416 u16KeyEnableBit[1] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->KEY_ENABLE_BIT[1]));
1417 u16KeyEnableBit[2] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->KEY_ENABLE_BIT[2]));
1418 u16KeyEnableBit[3] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->KEY_ENABLE_BIT[3]));
1419
1420 MS_U64 u64Mask = 0;
1421 MS_U64 u64Data = u16KeyEnableBit[0] + ((MS_U64)u16KeyEnableBit[1] << 16)
1422 + ((MS_U64)u16KeyEnableBit[2] << 32) + ((MS_U64)u16KeyEnableBit[3] << 48);
1423
1424 if (bEnable)
1425 {
1426 u64Mask = (MS_U64)(0x1) << u8Sid;
1427 u64Data |= u64Mask;
1428 }
1429 else
1430 {
1431 u64Mask = ~((MS_U64)(0x1) << u8Sid);
1432 u64Data &= u64Mask;
1433 }
1434
1435 u16KeyEnableBit[0] = (u64Data & 0x000000000000FFFF);
1436 u16KeyEnableBit[1] = (u64Data & 0x00000000FFFF0000)>>16;
1437 u16KeyEnableBit[2] = (u64Data & 0x0000FFFF00000000)>>32;
1438 u16KeyEnableBit[3] = (u64Data & 0xFFFF000000000000)>>48;
1439
1440 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->KEY_ENABLE_BIT[0]), u16KeyEnableBit[0]);
1441 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->KEY_ENABLE_BIT[1]), u16KeyEnableBit[1]);
1442 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->KEY_ENABLE_BIT[2]), u16KeyEnableBit[2]);
1443 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->KEY_ENABLE_BIT[3]), u16KeyEnableBit[3]);
1444 }
1445
HAL_TSIO_LOCDEC_PrivilegeSlotEnable(MS_U8 u8Sid,MS_BOOL bEnable)1446 void HAL_TSIO_LOCDEC_PrivilegeSlotEnable(MS_U8 u8Sid, MS_BOOL bEnable)
1447 {
1448 MS_U16 u16PrivilegeBit[4];
1449
1450 u16PrivilegeBit[0] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->SLOT_PRIVILEGE[0]));
1451 u16PrivilegeBit[1] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->SLOT_PRIVILEGE[1]));
1452 u16PrivilegeBit[2] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->SLOT_PRIVILEGE[2]));
1453 u16PrivilegeBit[3] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->SLOT_PRIVILEGE[3]));
1454
1455 MS_U64 u64Mask = 0;
1456 MS_U64 u64Data = u16PrivilegeBit[0] + ((MS_U64)u16PrivilegeBit[1] << 16)
1457 + ((MS_U64)u16PrivilegeBit[2] << 32) + ((MS_U64)u16PrivilegeBit[3] << 48);
1458
1459 if (bEnable)
1460 {
1461 u64Mask = (MS_U64)(0x1) << u8Sid;
1462 u64Data |= u64Mask;
1463 }
1464 else
1465 {
1466 u64Mask = ~((MS_U64)(0x1) << u8Sid);
1467 u64Data &= u64Mask;
1468 }
1469
1470 u16PrivilegeBit[0] = (u64Data & 0x000000000000FFFF);
1471 u16PrivilegeBit[1] = (u64Data & 0x00000000FFFF0000)>>16;
1472 u16PrivilegeBit[2] = (u64Data & 0x0000FFFF00000000)>>32;
1473 u16PrivilegeBit[3] = (u64Data & 0xFFFF000000000000)>>48;
1474
1475 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->SLOT_PRIVILEGE[0]), u16PrivilegeBit[0]);
1476 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->SLOT_PRIVILEGE[1]), u16PrivilegeBit[1]);
1477 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->SLOT_PRIVILEGE[2]), u16PrivilegeBit[2]);
1478 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->SLOT_PRIVILEGE[3]), u16PrivilegeBit[3]);
1479 }
1480
HAL_TSIO_LOCDEC_SecureSlotEnable(MS_U8 u8Sid,MS_BOOL bEnable)1481 void HAL_TSIO_LOCDEC_SecureSlotEnable(MS_U8 u8Sid, MS_BOOL bEnable)
1482 {
1483 MS_U16 u16SecureBit[4];
1484
1485 u16SecureBit[0] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->SLOT_SECURE[0]));
1486 u16SecureBit[1] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->SLOT_SECURE[1]));
1487 u16SecureBit[2] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->SLOT_SECURE[2]));
1488 u16SecureBit[3] = _HAL_REG16_R(&(_TSIOCtrlLOCDEC->SLOT_SECURE[3]));
1489
1490 MS_U64 u64Mask = 0;
1491 MS_U64 u64Data = u16SecureBit[0] + ((MS_U64)u16SecureBit[1] << 16)
1492 + ((MS_U64)u16SecureBit[2] << 32) + ((MS_U64)u16SecureBit[3] << 48);
1493
1494 if (bEnable)
1495 {
1496 u64Mask = (MS_U64)(0x1) << u8Sid;
1497 u64Data |= u64Mask;
1498 }
1499 else
1500 {
1501 u64Mask = ~((MS_U64)(0x1) << u8Sid);
1502 u64Data &= u64Mask;
1503 }
1504
1505 u16SecureBit[0] = (u64Data & 0x000000000000FFFF);
1506 u16SecureBit[1] = (u64Data & 0x00000000FFFF0000)>>16;
1507 u16SecureBit[2] = (u64Data & 0x0000FFFF00000000)>>32;
1508 u16SecureBit[3] = (u64Data & 0xFFFF000000000000)>>48;
1509
1510 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->SLOT_SECURE[0]), u16SecureBit[0]);
1511 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->SLOT_SECURE[1]), u16SecureBit[1]);
1512 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->SLOT_SECURE[2]), u16SecureBit[2]);
1513 _HAL_REG16_W(&(_TSIOCtrlLOCDEC->SLOT_SECURE[3]), u16SecureBit[3]);
1514 }
1515
HAL_TSIO_LOCDEC_SetSWKeyProperty(MS_U32 keyProperty)1516 void HAL_TSIO_LOCDEC_SetSWKeyProperty(MS_U32 keyProperty)
1517 {
1518 _HAL_REG32_W(&(_TSIOCtrlLOCDEC->SW_KEY_PROPERTY), keyProperty);
1519 }
1520
1521 //=======================================================
1522 // Get Infomation API
1523 //=======================================================
HAL_TSIO_GetLoselockcnt(void)1524 MS_U16 HAL_TSIO_GetLoselockcnt(void)
1525 {
1526 MS_U16 u16rdata = 0;
1527 u16rdata = _HAL_REG16_R(&(_TSIOCtrl1->LOSE_LOCK_CNT));
1528 return u16rdata;
1529 }
1530
1531 //=======================================================
1532 // Bit training API
1533 //=======================================================
HAL_TSIO_Bittraining_init(void)1534 void HAL_TSIO_Bittraining_init(void)
1535 {
1536 ANALOG_PHASE_SETTING *Setting = &SETTING[u8Phasetable][0];
1537 _REG16_SET_MASK(&(_TSIOCtrl1->CHG_PH_STABLE_TIME), ANALOG_PHASE_GAP, TSIO1_CHG_PH_STABLE_TIME_GUARD_PH_MASK, TSIO1_CHG_PH_STABLE_TIME_GUARD_PH_SHIFT);
1538 MsOS_DelayTask(1);
1539 _REG16_SET(&(_TSIOCtrl1->CHG_PH_STABLE_TIME),TSIO1_CHG_PH_STABLE_TIME_GUARD_PH_LOAD);
1540 MsOS_DelayTask(1);
1541 _REG16_CLR(&(_TSIOCtrl1->CHG_PH_STABLE_TIME),TSIO1_CHG_PH_STABLE_TIME_GUARD_PH_LOAD);
1542 MsOS_DelayTask(1);
1543 _HAL_REG16_W(&(_TSIOCtrl1->BTRAIN_CONFIG3), 0x8000);
1544 MsOS_DelayTask(1);
1545 _HAL_REG16_W(&(_TSIOCtrl1->BTRAIN_CONFIG0), 0x8010);
1546 MsOS_DelayTask(1);
1547 _HAL_REG16_W(&(_TSIOCtrl1->BTRAIN_CONFIG0), 0x0010);
1548 MsOS_DelayTask(1);
1549 _HAL_REG16_W(&(_TSIOCtrl1->BTRAIN_CONFIG3), 0x8010);
1550 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_PH_INFO_SEL);
1551 MsOS_DelayTask(1);
1552 //_REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG4), TSIO1_BTRAIN_CONFIG4_DISABLE_BITTRAIN);
1553 //====skew1====
1554 //Coarse
1555 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_24), Setting[11].u8Corse,
1556 TSIO_PHY_24_LPLL_SKEW1_COARSE_MASK, TSIO_PHY_24_LPLL_SKEW1_COARSE_SHIFT);
1557 MsOS_DelayTask(1);
1558 //Fine
1559 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_23), Setting[11].u8Fine,
1560 TSIO_PHY_23_LPLL_SKEW1_FINE_MASK, TSIO_PHY_23_LPLL_SKEW1_FINE_SHIFT);
1561 MsOS_DelayTask(1);
1562 //Delay1t
1563 if (Setting[11].u8Delay1T)
1564 {
1565 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_SEL_SKEW1_DELAYlt);
1566 }
1567 else
1568 {
1569 _REG16_CLR(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_SEL_SKEW1_DELAYlt);
1570 }
1571 MsOS_DelayTask(1);
1572 }
1573
HAL_TSIO_Bittraining_init_dynamic(void)1574 void HAL_TSIO_Bittraining_init_dynamic(void)
1575 {
1576 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_18), 0x20,TSIO_PHY_18_TEST_TSIO_MASK, TSIO_PHY_18_TEST_TSIO_SHIFT); // loopback
1577 MsOS_DelayTask(1);
1578 _HAL_REG16_W(&(_TSIOCtrl0->AD_TX_CONFIG0), 0x0288);
1579 _HAL_REG16_W(&(_TSIOCtrl0->PRBS_CONFIG0), 0x1007);
1580 _HAL_REG16_W(&(_TSIOCtrl0->AD_RX_CONFIG0), 0x0000);
1581 MsOS_DelayTask(1);
1582 _HAL_REG16_W(&(_TSIOCtrl1->BTRAIN_CONFIG0), 0x9010);
1583 _HAL_REG16_W(&(_TSIOCtrl1->BTRAIN_CONFIG0), 0x1010);
1584 _HAL_REG16_W(&(_TSIOCtrl1->BTRAIN_CONFIG3), 0x8010);
1585 MsOS_DelayTask(1);
1586 }
1587
HAL_TSIO_Bittraining_Getremapstate(void)1588 MS_BOOL HAL_TSIO_Bittraining_Getremapstate(void)
1589 {
1590 MS_U16 u16Data = 0;
1591 MS_BOOL bRet = 0;
1592 u16Data = _HAL_REG16_R(&(_TSIOCtrl0->BTRAIN_ST_0));
1593
1594 bRet = ((u16Data & TSIO0_BTRAIN_ST_0_CHG_PH_START_REMAP) >> TSIO0_BTRAIN_ST_0_CHG_PH_START_REMAP_SHIFT);
1595 return bRet;
1596 }
1597
HAL_TSIO_Bittraining_Setvalue(MS_BOOL bEarly,MS_BOOL bLate)1598 void HAL_TSIO_Bittraining_Setvalue(MS_BOOL bEarly, MS_BOOL bLate)
1599 {
1600 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_DEBUG_REG_LOAD);
1601 //_REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_SW_CH_PH_REMAP);
1602 if (bEarly)
1603 {
1604 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_SW_EARLY);
1605 }
1606 else
1607 {
1608 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_SW_EARLY);
1609 }
1610 if (bLate)
1611 {
1612 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_SW_LATE);
1613 }
1614 else
1615 {
1616 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_SW_LATE);
1617 }
1618 MsOS_DelayTaskUs(1);
1619 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_SW_CHG_PH_DONE);
1620 MsOS_DelayTaskUs(1);
1621 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_SW_CHG_PH_DONE);
1622 MsOS_DelayTaskUs(1);
1623 }
1624
HAL_TSIO_Bittraining_GetPhase(MS_U8 u8Phase)1625 MS_U8 HAL_TSIO_Bittraining_GetPhase(MS_U8 u8Phase)
1626 {
1627 MS_U16 u16Data = 0;
1628 MS_U8 u8Ret = 0;
1629
1630 //0: phase, 1: eraly, 2: late
1631 _REG16_SET_MASK(&(_TSIOCtrl1->BTRAIN_CONFIG3), u8Phase, TSIO1_CHANNEL_SEL_MASK, TSIO1_CHANNEL_SEL_SHIFT);
1632 MsOS_DelayTask(1);
1633 u16Data = _HAL_REG16_R(&(_TSIOCtrl0->PH_INFO_2));
1634 u8Ret = (u16Data & TSIO0_PH_INFO_2_REG_PHASE_MASK) >> TSIO0_PH_INFO_2_REG_PHASE_SHIFT;
1635 return u8Ret;
1636 }
1637
HAL_TSIO_Bittraining_GetElinfo(MS_BOOL bEarly)1638 void HAL_TSIO_Bittraining_GetElinfo(MS_BOOL bEarly)
1639 {
1640 MS_U16 u16Data[3] = {0};
1641
1642 if (bEarly)
1643 {
1644 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_EL_INFO_SEL);
1645 }
1646 else
1647 {
1648 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_EL_INFO_SEL);
1649 }
1650 MsOS_DelayTask(1);
1651
1652 u16Data[0] = _HAL_REG16_R(&(_TSIOCtrl0->EL_INFO[0]));
1653 u16Data[1] = _HAL_REG16_R(&(_TSIOCtrl0->EL_INFO[1]));
1654 u16Data[2] = _HAL_REG16_R(&(_TSIOCtrl0->EL_INFO[2]));
1655
1656 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE, printf("[0x75][0x74][0x73] = [%04X][%04X][%04X]\n",
1657 u16Data[2], u16Data[1], u16Data[0]));
1658 }
1659
HAL_TSIO_Bittraining_GetPhaseinfo(void)1660 void HAL_TSIO_Bittraining_GetPhaseinfo(void)
1661 {
1662 MS_U16 u16Data[4] = {0};
1663
1664 MsOS_DelayTask(1);
1665 u16Data[0] = _HAL_REG16_R(&(_TSIOCtrl0->PH_INFO_0));
1666 u16Data[1] = _HAL_REG16_R(&(_TSIOCtrl0->PH_INFO_1));
1667 u16Data[2] = _HAL_REG16_R(&(_TSIOCtrl0->PH_INFO_2));
1668 u16Data[3] = _HAL_REG16_R(&(_TSIOCtrl0->BTRAIN_ST_0));
1669
1670 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE, printf("[0x70][0x71][0x72][0x79] = [%04X][%04X][%04X][%04X]\n",
1671 u16Data[0], u16Data[1], u16Data[2], u16Data[3]));
1672 }
1673
HAL_TSIO_Bittraining_CheckPrbsErrcnt(void)1674 MS_U16 HAL_TSIO_Bittraining_CheckPrbsErrcnt(void)
1675 {
1676 _HAL_REG16_W(&(_TSIOCtrl0->PRBS_CONFIG0), 0x1000);
1677 MsOS_DelayTask(1);
1678 _HAL_REG16_W(&(_TSIOCtrl0->PRBS_CONFIG0), 0x1007);
1679 MsOS_DelayTask(1);
1680
1681 return _HAL_REG16_R(&(_TSIOCtrl0->DP_PHY_PRBS_ERRCNT));
1682 }
1683
HAL_TSIO_Int_Bittraining_Enable(MS_BOOL bEnable)1684 void HAL_TSIO_Int_Bittraining_Enable(MS_BOOL bEnable)
1685 {
1686 if (bEnable)
1687 {
1688 _REG16_SET(&(_TSIOCtrl1->BTRAIN_INT_EN), TSIO1_BTRAIN_INT_EN);
1689 }
1690 else
1691 {
1692 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_INT_EN), TSIO1_BTRAIN_INT_EN);
1693 }
1694 }
1695
HAL_TSIO_Int_Bittraining_Clear(void)1696 void HAL_TSIO_Int_Bittraining_Clear(void)
1697 {
1698 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR);
1699 MsOS_DelayTask(1);
1700 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR);
1701 MsOS_DelayTask(1);
1702 }
1703
HAL_TSIO_Int_Bittraining_Read(void)1704 MS_BOOL HAL_TSIO_Int_Bittraining_Read(void)
1705 {
1706 MS_U16 u16Data = 0;
1707 MS_BOOL bRet = FALSE;
1708 u16Data = _HAL_REG16_R(&(_TSIOCtrl1->BTRAIN_INT_STATUS));
1709
1710 if (u16Data & TSIO1_GUARD_REACH_MIN)
1711 {
1712 bRet = TRUE;
1713 }
1714
1715 return bRet;
1716 }
1717
HAL_TSIO_DBG_Read(MS_U16 u16Dbg)1718 MS_U32 HAL_TSIO_DBG_Read(MS_U16 u16Dbg)
1719 {
1720 MS_U32 u32Data = 0;
1721 _HAL_REG16_W(&(_TSIOCtrl1->TSIO_DBG_SEL), u16Dbg);
1722 u32Data = _HAL_REG32_R(&(_TSIOCtrl1->TSIO_DEBUG));
1723 return u32Data;
1724 }
1725
1726 //=======================================================
1727 // Interrupt API
1728 //=======================================================
HAL_TSIO_Int_Operation_Read(void)1729 MS_BOOL HAL_TSIO_Int_Operation_Read(void)
1730 {
1731 MS_U16 u16Data = 0;
1732 MS_BOOL bRet = FALSE;
1733 u16Data = _HAL_REG16_R(&(_TSIOCtrl0->PUH_STATUS0));
1734
1735 if (u16Data & TSIO0_PUH_STATUS0_OPERATION)
1736 {
1737 bRet = TRUE;
1738 }
1739
1740 return TRUE;
1741 }
1742
HAL_TSIO_Int_Operation_Enable(MS_BOOL bEnable)1743 void HAL_TSIO_Int_Operation_Enable(MS_BOOL bEnable)
1744 {
1745 if (bEnable)
1746 {
1747 _REG16_SET(&(_TSIOCtrl0->PUH_CONFIG2), TSIO0_PUH_CONFIG2_OPERATION_START_EN);
1748 }
1749 else
1750 {
1751 _REG16_CLR(&(_TSIOCtrl0->PUH_CONFIG2), TSIO0_PUH_CONFIG2_OPERATION_START_EN);
1752 }
1753 }
1754
HAL_TSIO_Int_Operation_Clear(void)1755 void HAL_TSIO_Int_Operation_Clear(void)
1756 {
1757 _REG16_SET(&(_TSIOCtrl0->PUH_CONFIG2), TSIO0_PUH_CONFIG2_OPERATION_START_CLR);
1758 _REG16_CLR(&(_TSIOCtrl0->PUH_CONFIG2), TSIO0_PUH_CONFIG2_OPERATION_START_CLR);
1759 }
1760
1761 //=======================================================
1762 // Analog phase API
1763 //=======================================================
1764
HAL_TSIO_Analogphase_Pllreset(void)1765 void HAL_TSIO_Analogphase_Pllreset(void)
1766 {
1767 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_PD);
1768 MsOS_DelayTask(1);
1769 _REG16_CLR(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_PD);
1770 MsOS_DelayTask(1);
1771 }
1772
_HAL_TSIO_Analogphase_Tableswitch(HAL_TSIO_CLK eClk)1773 static MS_U8 _HAL_TSIO_Analogphase_Tableswitch(HAL_TSIO_CLK eClk)
1774 {
1775 MS_U8 u8Ret = 0;
1776
1777 switch (eClk)
1778 {
1779 default:
1780 case HAL_TSIO_CLK_200M:
1781 u8Ret = 0;
1782 break;
1783
1784 case HAL_TSIO_CLK_100M:
1785 u8Ret = 1;
1786 break;
1787
1788 case HAL_TSIO_CLK_50M:
1789 u8Ret = 2;
1790 break;
1791
1792 case HAL_TSIO_CLK_25M:
1793 u8Ret = 3;
1794 break;
1795 }
1796 return u8Ret;
1797 }
1798
HAL_TSIO_Analogphase_Init(HAL_TSIO_CLK eClk,MS_BOOL bLoopback)1799 void HAL_TSIO_Analogphase_Init(HAL_TSIO_CLK eClk, MS_BOOL bLoopback)
1800 {
1801 MS_BOOL bBit15 = FALSE;
1802 MS_U8 u8DA_OV = 0;
1803 MS_U8 u8DB_OV = 0;
1804
1805 u8Phasetable = _HAL_TSIO_Analogphase_Tableswitch(eClk);
1806
1807 _REG16_CLR(&(_TSIOCtrl0->SW_RSTZ), TSIO0_SW_RST_ANA_RX);
1808
1809 #if (BITTRAINING_SW_MODE_ENABLE == 1)
1810 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_22),TSIO_PHY_22_LPLL_SW_DEBUG_EN);
1811 #endif
1812 MsOS_DelayTask(1);
1813 //toggle to force phase jump, will not bit training done until SW exit
1814 if (bLoopback)
1815 {
1816 _HAL_REG16_W(&(_TSIOCtrl0->PUH_CONFIG1), 0x0869); //for loopback
1817 }
1818 else
1819 {
1820 _HAL_REG16_W(&(_TSIOCtrl0->PUH_CONFIG1), 0x0809);
1821 }
1822 MsOS_DelayTask(1);
1823 _REG16_SET(&(_TSIOCtrl0->SW_RSTZ), TSIO0_SW_RSTZ);
1824 MsOS_DelayTask(1);
1825 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR);
1826 MsOS_DelayTask(1);
1827 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR);
1828 MsOS_DelayTask(1);
1829 _REG16_SET(&(_TSIOCtrl1->BTRAIN_INT_EN), TSIO1_BTRAIN_INT_EN);
1830 #if (BITTRAINING_SW_MODE_ENABLE == 1)
1831 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG0), TSIO1_SW_JUMP_PH_CH);
1832 MsOS_DelayTask(1);
1833 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG0), TSIO1_SW_JUMP_PH_CH);
1834 MsOS_DelayTask(1);
1835 #endif
1836 //_REG16_SET(&(_TSIOCtrl0->AD_TX_CONFIG0), TSIO0_CH_SWAP);
1837 //MsOS_DelayTask(1);
1838
1839 //TSIO_ATOP RX calibration
1840 _HAL_REG16_W(&(_TSIOCtrlPHY->TSIO_PHY_00), 0x807E);
1841 MsOS_DelayTask(1);
1842 _HAL_REG16_W(&(_TSIOCtrlPHY->TSIO_PHY_00), 0x007E);
1843 MsOS_DelayTask(1);
1844 do
1845 {
1846 bBit15 = (_HAL_REG16_R(&(_TSIOCtrlPHY->TSIO_PHY_0B)) & TSIO_PHY_0B_RX_CAL_END) >> TSIO_PHY_0B_RX_CAL_END_SHIFT;
1847 MsOS_DelayTask(1);
1848 }while(!bBit15);
1849 u8DA_OV = (_HAL_REG16_R(&(_TSIOCtrlPHY->TSIO_PHY_0B)) & TSIO_PHY_0B_RX_CAL_DATA_A_MASK) >> TSIO_PHY_0B_RX_CAL_DATA_A_SHIFT;
1850 u8DB_OV = (_HAL_REG16_R(&(_TSIOCtrlPHY->TSIO_PHY_0B)) & TSIO_PHY_0B_RX_CAL_DATA_B_MASK) >> TSIO_PHY_0B_RX_CAL_DATA_B_SHIFT;
1851 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_06), (0x40|u8DA_OV), TSIO_PHY_06_GCR_RX_CA_DA_OV_MASK, TSIO_PHY_06_GCR_RX_CA_DA_OV_SHIFT);
1852 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_06), (0x40|u8DB_OV), TSIO_PHY_06_GCR_RX_CA_DB_OV_MASK, TSIO_PHY_06_GCR_RX_CA_DB_OV_SHIFT);
1853
1854 //TSIO
1855 //_HAL_REG16_W(&(_TSIOCtrlPHY->TSIO_PHY_00), 0x007E);
1856 //MsOS_DelayTask(1);
1857 _HAL_REG16_W(&(_TSIOCtrlPHY->TSIO_PHY_0F), 0x0010);
1858 MsOS_DelayTask(1);
1859 _HAL_REG16_W(&(_TSIOCtrl0->MAX_PERIOD_OF_PKT_SYNC), 0x0000); // for test
1860 MsOS_DelayTask(1);
1861
1862 //LPLL
1863 _HAL_REG16_W(&(_TSIOCtrlPHY->TSIO_PHY_20), 0x0000);
1864 MsOS_DelayTask(1);
1865 _HAL_REG16_W(&(_TSIOCtrlPHY->TSIO_PHY_21), 0x0002);
1866 MsOS_DelayTask(1);
1867 _HAL_REG16_W(&(_TSIOCtrlPHY->TSIO_PHY_22), 0x8138);
1868 MsOS_DelayTask(1);
1869 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_22), u8Phasetable, TSIO_PHY_22_LPLL_SKEW_DIV_MASK,TSIO_PHY_22_LPLL_SKEW_DIV_SHIFT);
1870 MsOS_DelayTask(1);
1871 _REG32_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_30_31), 0x19EB85, TSIO_PHY_30_31_LPLL_SYNTH_SET_MASK, TSIO_PHY_30_31_LPLL_SYNTH_SET_SHIFT);
1872 MsOS_DelayTask(1);
1873
1874 //TSIO
1875 _REG16_SET(&(_TSOCtrl0->TSO_CONFIG5), TSO0_TSIO_MODE);
1876 _REG16_SET(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_INSERT_CTS_IN_TX);
1877 _REG16_SET(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_TURN_OFF_MCM_TSIO);
1878 _HAL_REG16_W(&(_TSIOCtrl0->MAX_PERIOD_OF_SOC_TRAINING), 0x0000);
1879
1880 #if (BITTRAINING_SW_MODE_ENABLE == 1)
1881 if (bLoopback)
1882 {
1883 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_18), 0x20,TSIO_PHY_18_TEST_TSIO_MASK, TSIO_PHY_18_TEST_TSIO_SHIFT); // loopback
1884 MsOS_DelayTask(1);
1885 _HAL_REG16_W(&(_TSIOCtrl0->PUH_CONFIG1), 0x0859); //for loopback
1886 MsOS_DelayTask(1);
1887 }
1888 #else
1889 //====skew====
1890 switch(eClk)
1891 {
1892 default:
1893 case HAL_TSIO_CLK_200M:
1894 //Coarse (200MHz)
1895 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_24), 0x0002,
1896 TSIO_PHY_24_LPLL_SKEW1_COARSE_MASK, TSIO_PHY_24_LPLL_SKEW1_COARSE_SHIFT);
1897 break;
1898 case HAL_TSIO_CLK_100M:
1899 //Coarse (100MHz)
1900 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_24), 0x0004,
1901 TSIO_PHY_24_LPLL_SKEW1_COARSE_MASK, TSIO_PHY_24_LPLL_SKEW1_COARSE_SHIFT);
1902 break;
1903 case HAL_TSIO_CLK_50M:
1904 //Coarse (50MHz)
1905 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_24), 0x0008,
1906 TSIO_PHY_24_LPLL_SKEW1_COARSE_MASK, TSIO_PHY_24_LPLL_SKEW1_COARSE_SHIFT);
1907 break;
1908 case HAL_TSIO_CLK_25M:
1909 //Coarse (25MHz)
1910 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_24), 0x0010,
1911 TSIO_PHY_24_LPLL_SKEW1_COARSE_MASK, TSIO_PHY_24_LPLL_SKEW1_COARSE_SHIFT);
1912 break;
1913 }
1914 MsOS_DelayTaskUs(1);
1915 #endif
1916 _REG16_SET(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_DECRYPT_DISABLE);
1917
1918 //enable operation start interrupt
1919 _REG16_SET(&(_TSIOCtrl0->PUH_CONFIG2), TSIO0_PUH_CONFIG2_OPERATION_START_EN);
1920
1921 //phase DAC power up 10%
1922 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_00), TSIO_PHY_00_REG_REF_SEL);
1923 MsOS_DelayTask(1);
1924 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_02), 3, TSIO_PHY_02_TEST_REG_MASK, TSIO_PHY_02_TEST_REG_SHIFT);
1925 MsOS_DelayTask(1);
1926
1927 }
1928
HAL_TSIO_Analogphase_Exit(void)1929 void HAL_TSIO_Analogphase_Exit(void)
1930 {
1931 //_HAL_REG16_W(&(_TSIOCtrlPHY->TSIO_PHY_00), 0x107E);
1932 //MsOS_DelayTask(1);
1933
1934 _REG16_CLR(&(_TSIOCtrl0->SW_RSTZ), TSIO0_SW_RSTZ);//low active
1935 _REG16_SET(&(_TSIOCtrl0->SW_RSTZ), TSIO0_SW_RST_ANA_RX);
1936 MsOS_DelayTask(1);
1937 }
1938
HAL_TSIO_Analogphase_Set(MS_BOOL bSelect,MS_U8 u8Phase,MS_U8 u8Gap)1939 void HAL_TSIO_Analogphase_Set(MS_BOOL bSelect, MS_U8 u8Phase, MS_U8 u8Gap)
1940 {
1941 MS_U8 u8Phase_pre = 0;
1942 MS_U8 u8Phase_next = 0;
1943 ANALOG_PHASE_SETTING *Setting = &SETTING[u8Phasetable][0];
1944 static MS_BOOL bReset = TRUE;
1945 static MS_U32 u32Count = 0;
1946
1947 if (u8Gap >= ANALOG_PHASE_GAP)
1948 {
1949 u8Gap = ANALOG_PHASE_GAP;
1950 }
1951
1952 if (u8Phase < u8Gap)
1953 {
1954 u8Phase_pre = ANALOG_PHASE_MAX + u8Phase - u8Gap + 1;
1955 }
1956 else
1957 {
1958 u8Phase_pre = u8Phase - u8Gap;
1959 }
1960
1961 u8Phase_next = u8Phase + u8Gap;
1962 if (u8Phase_next > ANALOG_PHASE_MAX)
1963 {
1964 u8Phase_next = u8Phase_next - ANALOG_PHASE_MAX - 1;
1965 }
1966
1967 //phdac reset
1968 if (bReset)
1969 {
1970 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE, printf("phdac Reset\n"));
1971 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_PHDAC_RST);
1972 MsOS_DelayTaskUs(1);
1973 _REG16_CLR(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_PHDAC_RST);
1974 MsOS_DelayTaskUs(1);
1975 bReset = FALSE;
1976 }
1977
1978 MS_U8 u8Skew_phase = 11;
1979 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE,printf("Count [%d]\n",u32Count++));
1980 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE,printf("Phase [%d, %d, %d, %d]\n",u8Skew_phase, u8Phase_pre, u8Phase, u8Phase_next));
1981 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE,printf("Select [%d, %d, %d, %d]\n",bSelect, bSelect, bSelect, bSelect));
1982 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE,printf("Delay1t [%d, %d, %d, %d]\n",Setting[u8Skew_phase].u8Delay1T,
1983 Setting[u8Phase_pre].u8Delay1T, Setting[u8Phase].u8Delay1T, Setting[u8Phase_next].u8Delay1T));
1984 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE,printf("Coarse [%d, %d, %d, %d]\n",Setting[u8Skew_phase].u8Corse,
1985 Setting[u8Phase_pre].u8Corse, Setting[u8Phase].u8Corse, Setting[u8Phase_next].u8Corse));
1986 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE,printf("Fine [%d, %d, %d, %d]\n",Setting[u8Skew_phase].u8Fine,
1987 Setting[u8Phase_pre].u8Fine, Setting[u8Phase].u8Fine, Setting[u8Phase_next].u8Fine));
1988 #if 1
1989 if (bSelect)
1990 {
1991 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_PHDAC_SELECT);
1992 }
1993 else
1994 {
1995 _REG16_CLR(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_PHDAC_SELECT);
1996 }
1997 #endif
1998 //select sw patch
1999 //_REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_PHDAC_SELECT);
2000 MsOS_DelayTaskUs(1);
2001
2002 //====skew1====
2003 //Coarse
2004 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_24), Setting[u8Skew_phase].u8Corse,
2005 TSIO_PHY_24_LPLL_SKEW1_COARSE_MASK, TSIO_PHY_24_LPLL_SKEW1_COARSE_SHIFT);
2006 MsOS_DelayTaskUs(1);
2007 //Fine
2008 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_23), Setting[u8Skew_phase].u8Fine,
2009 TSIO_PHY_23_LPLL_SKEW1_FINE_MASK, TSIO_PHY_23_LPLL_SKEW1_FINE_SHIFT);
2010 MsOS_DelayTaskUs(1);
2011 //Delay1t
2012 if (Setting[u8Skew_phase].u8Delay1T)
2013 {
2014 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_SEL_SKEW1_DELAYlt);
2015 }
2016 else
2017 {
2018 _REG16_CLR(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_SEL_SKEW1_DELAYlt);
2019 }
2020 MsOS_DelayTaskUs(1);
2021
2022 //====skew2====
2023 //Coarse
2024 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_24), Setting[u8Phase_pre].u8Corse,
2025 TSIO_PHY_24_LPLL_SKEW2_COARSE_MASK, TSIO_PHY_24_LPLL_SKEW2_COARSE_SHIFT);
2026 MsOS_DelayTaskUs(1);
2027 //Fine
2028 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_23), Setting[u8Phase_pre].u8Fine,
2029 TSIO_PHY_23_LPLL_SKEW2_FINE_MASK, TSIO_PHY_23_LPLL_SKEW2_FINE_SHIFT);
2030 MsOS_DelayTaskUs(1);
2031 //Delay1t
2032 if (Setting[u8Phase_pre].u8Delay1T)
2033 {
2034 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_SEL_SKEW2_DELAYlt);
2035 }
2036 else
2037 {
2038 _REG16_CLR(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_SEL_SKEW2_DELAYlt);
2039 }
2040 MsOS_DelayTaskUs(1);
2041
2042
2043 //====skew3====
2044 //Coarse
2045 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_25), Setting[u8Phase].u8Corse,
2046 TSIO_PHY_24_LPLL_SKEW3_COARSE_MASK, TSIO_PHY_24_LPLL_SKEW3_COARSE_SHIFT);
2047 MsOS_DelayTaskUs(1);
2048 //Fine
2049 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_23), Setting[u8Phase].u8Fine,
2050 TSIO_PHY_23_LPLL_SKEW3_FINE_MASK, TSIO_PHY_23_LPLL_SKEW3_FINE_SHIFT);
2051 MsOS_DelayTaskUs(1);
2052 //Delay1t
2053 if (Setting[u8Phase].u8Delay1T)
2054 {
2055 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_SEL_SKEW3_DELAYlt);
2056 }
2057 else
2058 {
2059 _REG16_CLR(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_SEL_SKEW3_DELAYlt);
2060 }
2061 MsOS_DelayTaskUs(1);
2062
2063 //====skew4====
2064 //Coarse
2065 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_25), Setting[u8Phase_next].u8Corse,
2066 TSIO_PHY_24_LPLL_SKEW4_COARSE_MASK, TSIO_PHY_24_LPLL_SKEW4_COARSE_SHIFT);
2067 MsOS_DelayTaskUs(1);
2068 //Fine
2069 _REG16_SET_MASK(&(_TSIOCtrlPHY->TSIO_PHY_23), Setting[u8Phase_next].u8Fine,
2070 TSIO_PHY_23_LPLL_SKEW4_FINE_MASK, TSIO_PHY_23_LPLL_SKEW4_FINE_SHIFT);
2071 MsOS_DelayTaskUs(1);
2072 //Delay1t
2073 if (Setting[u8Phase_next].u8Delay1T)
2074 {
2075 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_SEL_SKEW4_DELAYlt);
2076 }
2077 else
2078 {
2079 _REG16_CLR(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_SEL_SKEW4_DELAYlt);
2080 }
2081 MsOS_DelayTaskUs(1);
2082
2083 //select sw patch
2084 //_REG16_CLR(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_PHDAC_SELECT);
2085 //MsOS_DelayTask(1);
2086
2087 //update
2088 _REG16_SET(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_PHDAC_UPDATE);
2089 MsOS_DelayTaskUs(1);
2090 _REG16_CLR(&(_TSIOCtrlPHY->TSIO_PHY_20), TSIO_PHY_20_LPLL_PHDAC_UPDATE);
2091 MsOS_DelayTaskUs(1);
2092 }
2093
HAL_TSIO_Analogphase_Start(void)2094 void HAL_TSIO_Analogphase_Start(void)
2095 {
2096 _HAL_REG16_W(&(_TSIOCtrl0->PUH_CONFIG0), 0x0062);
2097 MsOS_DelayTask(1);
2098 _HAL_REG16_W(&(_TSIOCtrl0->PUH_CONFIG0), 0x0066);
2099 MsOS_DelayTask(1);
2100 _HAL_REG16_W(&(_TSIOCtrl0->PUH_CONFIG0), 0x0000);
2101 MsOS_DelayTask(1);
2102 }
2103
HAL_TSIO_Analogphase_Read(MS_BOOL bEarly)2104 MS_U16 HAL_TSIO_Analogphase_Read(MS_BOOL bEarly)
2105 {
2106 MS_U16 u16Data = 0;
2107 MS_U16 u16ReadCount = 150;
2108 MS_U16 u16index = 0;
2109 MS_U16 u16Count = 0;
2110 MS_U16 u16Temp = 0;
2111
2112 for (u16index = 0; u16index < u16ReadCount; u16index++)
2113 {
2114 if (bEarly)
2115 {
2116 u16Temp = _HAL_REG16_R(&(_TSIOCtrlPHY->TSIO_PHY_12));
2117 if (u16Temp)
2118 {
2119 u16Count++;
2120 }
2121 u16Data |= u16Temp;
2122 }
2123 else
2124 {
2125 u16Temp = _HAL_REG16_R(&(_TSIOCtrlPHY->TSIO_PHY_13));
2126 if (u16Temp)
2127 {
2128 u16Count++;
2129 }
2130 u16Data |= u16Temp;
2131 }
2132 }
2133
2134 if (u16Data)
2135 {
2136 if (bEarly)
2137 {
2138 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE, printf("Early error count = %d \n", u16Count));
2139 }
2140 else
2141 {
2142 HAL_TSIO_DBGMSG(E_HAL_TSIO_DBG_LEVEL_TRACE, printf("Late error count = %d \n", u16Count));
2143 }
2144 }
2145
2146 return u16Data;
2147 }
2148
HAL_TSIO_Analogphase_GetPuhstatus(void)2149 MS_U16 HAL_TSIO_Analogphase_GetPuhstatus(void)
2150 {
2151 MS_U16 u16Data = 0;
2152
2153 u16Data = (_HAL_REG16_R(&(_TSIOCtrl0->PUH_STATUS0)) & TSIO0_PUH_STATUS0_POWER_STATUS_MASK)
2154 >> TSIO0_PUH_STATUS0_POWER_STATUS_SHIFT;
2155
2156 return u16Data;
2157 }
2158
2159
HAL_TSIO_Analogphase_PrbsRead(void)2160 MS_U16 HAL_TSIO_Analogphase_PrbsRead(void)
2161 {
2162 MS_U16 u16Data = 0;
2163
2164 MsOS_DelayTask(1);
2165 _HAL_REG16_W(&(_TSIOCtrl0->PRBS_CONFIG0), 0x1000);
2166 MsOS_DelayTask(1);
2167 _HAL_REG16_W(&(_TSIOCtrl0->PRBS_CONFIG0), 0x1007);
2168 MsOS_DelayTask(1);
2169 u16Data = _HAL_REG16_R(&(_TSIOCtrl0->DP_PHY_PRBS_ERRCNT));
2170
2171 return u16Data;
2172 }
2173
2174 //=======================================================
2175 // TSIO Filter API (use for bypass smc)
2176 //=======================================================
HAL_TSIO_Filter_Enable(MS_U16 u16FltId,MS_BOOL bEnable)2177 void HAL_TSIO_Filter_Enable(MS_U16 u16FltId, MS_BOOL bEnable)
2178 {
2179 if (u16FltId >= TSIO_FILTER_NUM)
2180 return;
2181
2182 if (bEnable)
2183 {
2184 //_REG32_SET(&(_TSIOCtrl3->TSIO_FILTER[u16FltId]), TSIO3_FILTER_USE_PID_IN_FILTERING);
2185 _REG32_SET(&(_TSIOCtrl3->TSIO_FILTER[u16FltId]), TSIO3_FILTER_USE_SERVICE_ID_IN_FILTERING);
2186 _REG32_SET(&(_TSIOCtrl3->TSIO_FILTER[u16FltId]), TSIO3_FILTER_DATA_TO_TSIO_RX);
2187 _REG32_SET(&(_TSIOCtrl3->TSIO_FILTER[u16FltId]), TSIO3_FILTER_ENABLE);
2188 }
2189 else
2190 {
2191 _REG32_CLR(&(_TSIOCtrl3->TSIO_FILTER[u16FltId]), TSIO3_FILTER_ENABLE);
2192 }
2193 }
2194
HAL_TSIO_Filter_SetPid(MS_U16 u16FltId,MS_U16 u16Pid)2195 void HAL_TSIO_Filter_SetPid(MS_U16 u16FltId, MS_U16 u16Pid)
2196 {
2197 if (u16FltId >= TSIO_FILTER_NUM)
2198 return;
2199
2200 _REG32_SET_MASK(&(_TSIOCtrl3->TSIO_FILTER[u16FltId]), u16Pid, TSIO3_FILTER_PID_MASK, TSIO3_FILTER_PID_SHIFT);
2201 }
2202
HAL_TSIO_Filter_SetSid(MS_U16 u16FltId,MS_U8 u8Sid)2203 void HAL_TSIO_Filter_SetSid(MS_U16 u16FltId, MS_U8 u8Sid)
2204 {
2205 if (u16FltId >= TSIO_FILTER_NUM)
2206 return;
2207
2208 _REG32_SET_MASK(&(_TSIOCtrl3->TSIO_FILTER[u16FltId]), u8Sid, TSIO3_FILTER_SERVICE_ID_MASK, TSIO3_FILTER_SERVICE_ID_SHIFT);
2209 }
2210
2211 //=======================================================
2212 // Other API
2213 //=======================================================
HAL_TSIO_RxRecord_Start(MS_BOOL bEnable)2214 void HAL_TSIO_RxRecord_Start(MS_BOOL bEnable)
2215 {
2216 if (bEnable)
2217 {
2218 _HAL_REG16_W(&(_TSIOCtrl1->RXANA_TO_PVR), 0x2);
2219 _REG16_SET(&(_TSIOCtrl2->TSIO_RXANA_TO_PVR_DEBUG), TSIO2_TSIO_RXANA_TO_PVR_DEBG);
2220 }
2221 else
2222 {
2223 _HAL_REG16_W(&(_TSIOCtrl1->RXANA_TO_PVR), 0x0);
2224 _REG16_CLR(&(_TSIOCtrl2->TSIO_RXANA_TO_PVR_DEBUG), TSIO2_TSIO_RXANA_TO_PVR_DEBG);
2225 }
2226 }
2227
HAL_TSIO_RxRecord_Setbuf(MS_U32 u32Headaddr,MS_U32 u32Tailaddr)2228 void HAL_TSIO_RxRecord_Setbuf(MS_U32 u32Headaddr, MS_U32 u32Tailaddr)
2229 {
2230 _REG16_SET(&(_TSIOCtrl2->TSIO_PVR_CONFIG), TSIO2_PVR_STR2MI_EN);
2231 _HAL_REG32_W(&(_TSIOCtrl2->TSIO_PVR_STR2MI_HEAD_DEBUG), u32Headaddr);
2232 _HAL_REG32_W(&(_TSIOCtrl2->TSIO_PVR_STR2MI_TAIL_DEBUG), u32Tailaddr);
2233 _REG16_SET(&(_TSIOCtrl2->TSIO_PVR_CONFIG), TSIO2_PVR_STR2MI_RST_WADR);
2234 _REG16_CLR(&(_TSIOCtrl2->TSIO_PVR_CONFIG), TSIO2_PVR_STR2MI_RST_WADR);
2235 }
2236
HAL_TSIO_TSP_BLK_Set(MS_BOOL bEnable)2237 void HAL_TSIO_TSP_BLK_Set(MS_BOOL bEnable)
2238 {
2239 if(bEnable)
2240 {
2241 _REG16_SET(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO0_BLK_EN);
2242 _REG16_SET(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO1_BLK_EN);
2243 _REG16_SET(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO2_BLK_EN);
2244 _REG16_SET(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO3_BLK_EN);
2245 _REG16_SET(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO4_BLK_EN);
2246 _REG16_SET(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO5_BLK_EN);
2247 }
2248 else
2249 {
2250 _REG16_CLR(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO0_BLK_EN);
2251 _REG16_CLR(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO1_BLK_EN);
2252 _REG16_CLR(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO2_BLK_EN);
2253 _REG16_CLR(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO3_BLK_EN);
2254 _REG16_CLR(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO4_BLK_EN);
2255 _REG16_CLR(&(_TSPCtrl8->HW8_CONFIG3), TSP_TSIF0_TSIO5_BLK_EN);
2256 }
2257 }
2258
HAL_TSIO_STRLD_SET(MS_U8 u8index)2259 void HAL_TSIO_STRLD_SET(MS_U8 u8index)
2260 {
2261 MS_U8 u8Set = 0;
2262
2263 switch (u8index)
2264 {
2265 case 0:
2266 u8Set = 2; //1.75v
2267 break;
2268
2269 case 1:
2270 u8Set = 0; //1.8v
2271 break;
2272
2273 case 2:
2274 u8Set = 1; //1.85v
2275 break;
2276
2277 case 3:
2278 u8Set = 3; //1.9v
2279 break;
2280
2281 default:
2282 return;
2283 }
2284
2285 _REG16_SET_MASK(&(_TSIO_STRLD->REG_STRLD_32), u8Set, TEST_SDLDO_SEL_MASK, TEST_SDLDO_SEL_SHIFT);
2286 }
2287
2288