93 #define _REG16_SET(reg, value);    _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value));  macro
244     _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH);  in HAL_TSO_Init()
251     _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);  in HAL_TSO_Reset_All()
253     _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1);  in HAL_TSO_Reset_All()
890                 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
893 …             _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
896 …             _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
899 …             _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
902 …             _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
905 …             _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL);  in HAL_TSO_Set_PidBypass()
1034     _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ);  in HAL_TSO_Get_Filein_ReadAddr()
1193             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1);  in HAL_TSO_ChIf_ClrByteCnt()
1197             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2);  in HAL_TSO_ChIf_ClrByteCnt()
1201             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3);  in HAL_TSO_ChIf_ClrByteCnt()
1205             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4);  in HAL_TSO_ChIf_ClrByteCnt()
1209             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5);  in HAL_TSO_ChIf_ClrByteCnt()
1213             _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6);  in HAL_TSO_ChIf_ClrByteCnt()
1407         _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);  in HAL_TSO_RW_ValidBlock_Count()
1426         _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);  in HAL_TSO_RW_InvalidBlock_Count()
1503     _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_WLD);  in HAL_TSO_LPcr2_Set()
1515     _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_LOAD);  in HAL_TSO_LPcr2_Get()
1741                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1);  in HAL_TSO_Livein_3Wire()
1744                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2);  in HAL_TSO_Livein_3Wire()
1747                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3);  in HAL_TSO_Livein_3Wire()
1750                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4);  in HAL_TSO_Livein_3Wire()
1753                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5);  in HAL_TSO_Livein_3Wire()
1756                 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6);  in HAL_TSO_Livein_3Wire()
1797         _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE);  in HAL_TSO_TsioMode_En()
1809         _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF);  in HAL_TSO_Tsio2Opif_En()
1821         _REG16_SET(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN);  in HAL_TSO_SerialMode_En()
1885     _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_TX_RESET);  in HAL_TSO_SVQBuf_Set()
1887     _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_SVQ_TX_ENABLE);  in HAL_TSO_SVQBuf_Set()
2119         _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);  in HAL_TSO_PowerCtrl()
2169         _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);  in HAL_TSO_PowerCtrl()
2206             _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR1_READ);  in HAL_TSO_Pcr_Get()
2213             _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR2_READ);  in HAL_TSO_Pcr_Get()
2220             _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR3_READ);  in HAL_TSO_Pcr_Get()
2227             _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR4_READ);  in HAL_TSO_Pcr_Get()
2234             _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR2_CFG31),TSO2_REG_PCR5_READ);  in HAL_TSO_Pcr_Get()
2241             _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR2_CFG31),TSO2_REG_PCR6_READ);  in HAL_TSO_Pcr_Get()
2288                 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR1_RESET);  in HAL_TSO_PcrClr()
2291                 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR2_RESET);  in HAL_TSO_PcrClr()
2294                 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR3_RESET);  in HAL_TSO_PcrClr()
2297                 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR4_RESET);  in HAL_TSO_PcrClr()
2300                 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR5_RESET);  in HAL_TSO_PcrClr()
2303                 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR6_RESET);  in HAL_TSO_PcrClr()
2319         _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1);  in HAL_TSO_Set_SvqBypass()