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Searched refs:_HVD_WriteWordMask (Results 1 – 25 of 68) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DhalHVD_EX.c650 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
651_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
704 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
705_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
744_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
746_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
748_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
750_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
799_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
814_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c592 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
593_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
645 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
646_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
684_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
686_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
688_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
690_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
738_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
752_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DhalHVD_EX.c625 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
626_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
678 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
679_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
717_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
719_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
721_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
723_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
771_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
785_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DhalHVD_EX.c559 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
560_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
612 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
613_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
651_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
653_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
655_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
657_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
705_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
719_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c582 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
583_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
635 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
636_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
674_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
676_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
678_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
680_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
728_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
742_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DhalHVD_EX.c548 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
549_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
601 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
602_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
640_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
642_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
644_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
646_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
694_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
708_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DhalHVD_EX.c548 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
549_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
601 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
602_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
640_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
642_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
644_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
646_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
694_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
708_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c652 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
653_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
705 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
706_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
744_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
746_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
748_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
750_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
798_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
812_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c651 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
652_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
704 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
705_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
743_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
745_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
747_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
749_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
797_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
811_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/hvd_ex/
H A DhalHVD_EX.c373 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
374_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
424 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
425_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
463_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
465_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
467_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
469_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
515_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
529_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/hvd_ex/
H A DhalHVD_EX.c373 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
374_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
424 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
425_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
463_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
465_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
467_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
469_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
515_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
529_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/hvd_ex/
H A DhalHVD_EX.c373 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
374_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
424 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
425_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
463_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
465_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
467_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
469_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
515_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
529_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/hvd_ex/
H A DhalHVD_EX.c373 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
374_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
424 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
425_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
463_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
465_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
467_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
469_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
515_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
529_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/hvd_ex/
H A DhalHVD_EX.c373 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
374_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
424 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
425_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
463_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
465_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
467_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
469_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
515_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
529_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/hvd_ex/
H A DhalHVD_EX.c373 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
374_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
424 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
425_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
463_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
465_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
467_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
469_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
515_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
529_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/hvd_ex/
H A DhalHVD_EX.c373 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
374_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
424 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
425_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
463_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
465_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
467_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
469_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
515_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
529_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/hvd_ex/
H A DhalHVD_EX.c373 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
374_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
424 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
425_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
463_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
465_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
467_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
469_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
515_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
529_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DhalHVD_EX.c625 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUReadptr()
626_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUReadptr()
678 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT); in _HVD_EX_GetBBUWritedptr()
679_HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_… in _HVD_EX_GetBBUWritedptr()
717_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
719_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
721_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
723_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_ResetMainSubBBUWptr()
771_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); … in _HVD_EX_SetBBUWriteptr()
785_HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HVD_EX_MBoxSend()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DhalHVD.c274 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , 0 , HVD_REG_POLL_NAL_RPTR_BIT ); in _HAL_HVD_GetBBUReadptr()
275_HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , HVD_REG_POLL_NAL_RPTR_BIT , HVD_REG_POLL_NAL_RPTR_B… in _HAL_HVD_GetBBUReadptr()
284_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR , HVD_REG_NAL_WPTR_SYNC , HVD_REG_NAL_WPTR_SYNC); // set … in _HAL_HVD_SetBBUWriteptr()
294 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HAL_HVD_MBoxSend()
299 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET); in _HAL_HVD_MBoxSend()
386 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR , HVD_REG_RISC_MBOX0_CLR); in _HAL_HVD_MBoxClear()
389 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR , HVD_REG_RISC_MBOX1_CLR); in _HAL_HVD_MBoxClear()
473 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, 0, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
475 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
659_HVD_WriteWordMask(MVD_REG_STAT_CTRL, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU, MVD_REG_CTRL_RST|MV… in _HAL_HVD_RstMVDParser()
[all …]
H A DhalHVD_sub.c268 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , 0 , HVD_REG_POLL_NAL_RPTR_BIT ); in _HAL_HVD_Sub_GetBBUReadptr()
269_HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , HVD_REG_POLL_NAL_RPTR_BIT , HVD_REG_POLL_NAL_RPTR_B… in _HAL_HVD_Sub_GetBBUReadptr()
278_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR , HVD_REG_NAL_WPTR_SYNC , HVD_REG_NAL_WPTR_SYNC); // set … in _HAL_HVD_Sub_SetBBUWriteptr()
288 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HAL_HVD_Sub_MBoxSend()
293 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET); in _HAL_HVD_Sub_MBoxSend()
380 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR , HVD_REG_RISC_MBOX0_CLR); in _HAL_HVD_Sub_MBoxClear()
383 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR , HVD_REG_RISC_MBOX1_CLR); in _HAL_HVD_Sub_MBoxClear()
467 _HVD_WriteWordMask(HVD_REG_ESB_RPTR_BS2, 0, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_Sub_GetESReadPtr()
469 _HVD_WriteWordMask(HVD_REG_ESB_RPTR_BS2, HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_Sub_GetESReadPtr()
646_HVD_WriteWordMask(MVD_REG_STAT_CTRL, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU, MVD_REG_CTRL_RST|MV… in _HAL_HVD_Sub_RstMVDParser()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DhalHVD.c274 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , 0 , HVD_REG_POLL_NAL_RPTR_BIT ); in _HAL_HVD_GetBBUReadptr()
275_HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , HVD_REG_POLL_NAL_RPTR_BIT , HVD_REG_POLL_NAL_RPTR_B… in _HAL_HVD_GetBBUReadptr()
284_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR , HVD_REG_NAL_WPTR_SYNC , HVD_REG_NAL_WPTR_SYNC); // set … in _HAL_HVD_SetBBUWriteptr()
294 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HAL_HVD_MBoxSend()
299 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET); in _HAL_HVD_MBoxSend()
386 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR , HVD_REG_RISC_MBOX0_CLR); in _HAL_HVD_MBoxClear()
389 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR , HVD_REG_RISC_MBOX1_CLR); in _HAL_HVD_MBoxClear()
473 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, 0, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
475 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
659_HVD_WriteWordMask(MVD_REG_STAT_CTRL, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU, MVD_REG_CTRL_RST|MV… in _HAL_HVD_RstMVDParser()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DhalHVD.c274 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , 0 , HVD_REG_POLL_NAL_RPTR_BIT ); in _HAL_HVD_GetBBUReadptr()
275_HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , HVD_REG_POLL_NAL_RPTR_BIT , HVD_REG_POLL_NAL_RPTR_B… in _HAL_HVD_GetBBUReadptr()
284_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR , HVD_REG_NAL_WPTR_SYNC , HVD_REG_NAL_WPTR_SYNC); // set … in _HAL_HVD_SetBBUWriteptr()
294 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HAL_HVD_MBoxSend()
299 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET); in _HAL_HVD_MBoxSend()
386 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR , HVD_REG_RISC_MBOX0_CLR); in _HAL_HVD_MBoxClear()
389 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR , HVD_REG_RISC_MBOX1_CLR); in _HAL_HVD_MBoxClear()
473 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, 0, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
475 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
659_HVD_WriteWordMask(MVD_REG_STAT_CTRL, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU, MVD_REG_CTRL_RST|MV… in _HAL_HVD_RstMVDParser()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DhalHVD.c274 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , 0 , HVD_REG_POLL_NAL_RPTR_BIT ); in _HAL_HVD_GetBBUReadptr()
275_HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , HVD_REG_POLL_NAL_RPTR_BIT , HVD_REG_POLL_NAL_RPTR_B… in _HAL_HVD_GetBBUReadptr()
284_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR , HVD_REG_NAL_WPTR_SYNC , HVD_REG_NAL_WPTR_SYNC); // set … in _HAL_HVD_SetBBUWriteptr()
294 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HAL_HVD_MBoxSend()
299 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET); in _HAL_HVD_MBoxSend()
386 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR , HVD_REG_RISC_MBOX0_CLR); in _HAL_HVD_MBoxClear()
389 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR , HVD_REG_RISC_MBOX1_CLR); in _HAL_HVD_MBoxClear()
473 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, 0, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
475 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
659_HVD_WriteWordMask(MVD_REG_STAT_CTRL, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU, MVD_REG_CTRL_RST|MV… in _HAL_HVD_RstMVDParser()
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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DhalHVD.c274 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , 0 , HVD_REG_POLL_NAL_RPTR_BIT ); in _HAL_HVD_GetBBUReadptr()
275_HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , HVD_REG_POLL_NAL_RPTR_BIT , HVD_REG_POLL_NAL_RPTR_B… in _HAL_HVD_GetBBUReadptr()
284_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR , HVD_REG_NAL_WPTR_SYNC , HVD_REG_NAL_WPTR_SYNC); // set … in _HAL_HVD_SetBBUWriteptr()
294 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HAL_HVD_MBoxSend()
299 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET); in _HAL_HVD_MBoxSend()
386 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR , HVD_REG_RISC_MBOX0_CLR); in _HAL_HVD_MBoxClear()
389 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR , HVD_REG_RISC_MBOX1_CLR); in _HAL_HVD_MBoxClear()
473 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, 0, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
475 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
659_HVD_WriteWordMask(MVD_REG_STAT_CTRL, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU, MVD_REG_CTRL_RST|MV… in _HAL_HVD_RstMVDParser()
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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DhalHVD.c274 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , 0 , HVD_REG_POLL_NAL_RPTR_BIT ); in _HAL_HVD_GetBBUReadptr()
275_HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , HVD_REG_POLL_NAL_RPTR_BIT , HVD_REG_POLL_NAL_RPTR_B… in _HAL_HVD_GetBBUReadptr()
284_HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR , HVD_REG_NAL_WPTR_SYNC , HVD_REG_NAL_WPTR_SYNC); // set … in _HAL_HVD_SetBBUWriteptr()
294 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET); in _HAL_HVD_MBoxSend()
299 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET); in _HAL_HVD_MBoxSend()
386 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR , HVD_REG_RISC_MBOX0_CLR); in _HAL_HVD_MBoxClear()
389 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR , HVD_REG_RISC_MBOX1_CLR); in _HAL_HVD_MBoxClear()
473 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, 0, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
475 _HVD_WriteWordMask(HVD_REG_ESB_RPTR, HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL); in _HAL_HVD_GetESReadPtr()
659_HVD_WriteWordMask(MVD_REG_STAT_CTRL, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU, MVD_REG_CTRL_RST|MV… in _HAL_HVD_RstMVDParser()
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