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Searched refs:TSP_PVR1_BLOCK_DIS (Results 1 – 25 of 29) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h476 #define TSP_PVR1_BLOCK_DIS 0x00040000 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c2820 …_HAL_REG32_R(&_TspCtrl[0].PVR2_Config)|(TSP_PVR2_PVR_ALIGN_EN|TSP_PVR1_BLOCK_DIS|TSP_PVR2_BLOCK_DI… in HAL_TSP_HwPatch()
3804 …W(&_TspCtrl[0].PVR2_Config, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
3818 …&_TspCtrl[0].PVR2_Config, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
H A DregTSP.h477 #define TSP_PVR1_BLOCK_DIS 0x00040000 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DregTSP.h479 #define TSP_PVR1_BLOCK_DIS 0x00040000UL macro
H A DhalTSP.c3072 TSP_PVR1_BLOCK_DIS | in HAL_TSP_HwPatch()
4164 …W(&_TspCtrl[0].PVR2_Config, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
4178 …&_TspCtrl[0].PVR2_Config, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DregTSP.h471 #define TSP_PVR1_BLOCK_DIS 0x00040000UL macro
H A DhalTSP.c3046 TSP_PVR1_BLOCK_DIS | in HAL_TSP_HwPatch()
4127 …W(&_TspCtrl[0].PVR2_Config, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
4141 …&_TspCtrl[0].PVR2_Config, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DregTSP.h492 #define TSP_PVR1_BLOCK_DIS 0x00040000UL macro
H A DhalTSP.c3020 …nfig, _HAL_REG32_R(&_TspCtrl[0].PVR2_Config)|TSP_PVR2_PVR_ALIGN_EN|TSP_PVR1_BLOCK_DIS|TSP_PVR2_BLO… in HAL_TSP_HwPatch()
4316 …W(&_TspCtrl[0].PVR2_Config, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
4330 …&_TspCtrl[0].PVR2_Config, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DregTSP.h494 #define TSP_PVR1_BLOCK_DIS 0x00040000UL macro
H A DhalTSP.c4571 …W(&_TspCtrl[0].PVR2_Config, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
4585 …&_TspCtrl[0].PVR2_Config, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DregTSP.h494 #define TSP_PVR1_BLOCK_DIS 0x00040000UL macro
H A DhalTSP.c3240 …nfig, _HAL_REG32_R(&_TspCtrl[0].PVR2_Config)|TSP_PVR2_PVR_ALIGN_EN|TSP_PVR1_BLOCK_DIS|TSP_PVR2_BLO… in HAL_TSP_HwPatch()
4588 …W(&_TspCtrl[0].PVR2_Config, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
4602 …&_TspCtrl[0].PVR2_Config, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR1_BLOCK_DIS)); in HAL_TSP_PVR_Fifo_Block_Disable()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DregTSP.h501 #define TSP_PVR1_BLOCK_DIS 0x00040000UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DregTSP.h501 #define TSP_PVR1_BLOCK_DIS 0x00040000UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DregTSP.h382 #define TSP_PVR1_BLOCK_DIS 0x00040000 macro
H A DhalTSP.c4302 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
4316 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h417 #define TSP_PVR1_BLOCK_DIS 0x00040000 macro
H A DhalTSP.c5682 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
5702 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h419 #define TSP_PVR1_BLOCK_DIS 0x00040000 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h451 #define TSP_PVR1_BLOCK_DIS 0x00040000 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h449 #define TSP_PVR1_BLOCK_DIS 0x00040000 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h449 #define TSP_PVR1_BLOCK_DIS 0x00040000 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h453 #define TSP_PVR1_BLOCK_DIS 0x00040000 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h449 #define TSP_PVR1_BLOCK_DIS 0x00040000 macro

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